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M6 <m6@xs4all.nl> wrote: > Perhaps I'll find the time to add your backend to the IDE. For the > moment I'm busy trying to get JTAG support into the IDE. With the > JTAG-option you then can update the Block RAM, and so reprogram the > picoblaze. I'm using XPS and Eclipse for programming my S3. All I had to do was to define a new external program, the command was simply "make -f system.make download". The makefile calls a Xilinx tool to update the bitstream and impact afterwards to download it. I've also configured a keyboard shortcut in Eclipse so I can now save and compile the project with strg+s and download it to the FPGA by pressing strg+alt+s afterwards (I chose this shortcut because of its good accessibility after having strg+s pressed) Perhaps these ideas might reduce some work for you, seizing the existing programs. -- mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver Der Computer ist die Antwort, doch was war eigentlich die Frage?Article: 89701
Anuja, I am not familiar with other vendor's tools, but Xilinx's Impact has a batch interface. If you just want a way to automate programming, you can use Impact w/o the GUI. Stephen Anuja wrote: > Hi All > I want to download bit file to the FPGA to program it w/out using any > GUIs like the JTAG programmer. I need to write some kind of APIs for > this. Could anyone suggest how to do this and what would be the kind of > interface required for the same. please help > AnujaArticle: 89702
mk wrote: > On 22 Sep 2005 08:18:54 -0700, "Giox" <giovanniparodi79@yahoo.it> > wrote: > > >>Hello everybody, I'm interested in the implementation of a 32x32 bit >>multiplier (unsigned values). The target FPGA is Virtex V300e >>I would like to implement a system that is not too big, while I have >>not a lot of timing constraints. Using a behavioral approach I obtain a >>multiplier that needs about 17% of the FPGA, I would like to reduce >>this size and the target frequency is about 70Mhz. >>Where can I find some good manual that can help me in this task? can >>you give me some advice about how to code this device? >>Any help will be appreciated. > > > Suppose you want to calculate p * q. > If p = a * 2^16 + b and q = c * 2^16 + d then > p * q = (a*c * 2^32 + (a*d+b*c) * 2^16 + b * d) which says that you > can use 4 16 bit multipliers to do a 32 bit multiplication or use one > 16 bit multiplier and run it over 4 cycles to get what you want. > Using karatsuba, you might get away with only 3 multipliers and just a few extralogic. SylvainArticle: 89703
Giox wrote:
>Hello everybody, I'm interested in the implementation of a 32x32 bit
>multiplier (unsigned values). The target FPGA is Virtex V300e
>I would like to implement a system that is not too big, while I have
>not a lot of timing constraints. Using a behavioral approach I obtain a
>multiplier that needs about 17% of the FPGA, I would like to reduce
>this size and the target frequency is about 70Mhz.
>Where can I find some good manual that can help me in this task? can
>you give me some advice about how to code this device?
>Any help will be appreciated.
>
>
>
Do you need a result on every cycle of the 70 MHz clock? If not, then
you can do the multiplication over several clock cycles summing the
partial products in an accumulator. Look at the multipliers page on my
website (Under the DSP section) for some guidance on different multipliers.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 89704acetylcholinerd@gmail.com wrote: > > If we break one of those pairs and run a (say) 70 MHz clock > on the + wire and a 70 MHz data stream on the - > Keep it differential. > >I just worry about the SI problems with running a 70 MHz > clock over 1m of cable... > Offhand, for 70 Mhz out and 280 Mbps back, I'd run the drivers as LVDS_EXT, layout for a 3dB differential attenuator at each end of the link (Note 1), use the LVDS_25_DCI on-chip terminations at the receivers, and simulate & prototype before relying on this advice. > >I'll happily take any other suggestions > And now for something completely different... If you can live with 70 Mbps of outgoing data on a cable with bandwidth to spare, try this for a clock recovery scheme (untested, designed-as-I-type-this, probably been done better before): Phase modulate your outgoing 70 Mhz clock's falling edges to encode the data, using a 140 MHz master clock and DDR output regs (Note 2): for a zero, send -___ for a one, send ---_ So 10110 would be ---_-___---_---_-___ Which has the rising edges all neatly lined up with those of the original source clock. At the receiving end, divide this by two (Note 3) with a rising edge FF to get an 35 Mhz clock, which now has no duty cycle modulation. Use the daughtercard DCMs to multiply this 35 MHz clock back to 70 Mhz to re-clock the input data ( a fixed 180 or 270 phase shift should do, this is a forwarded clock so cable prop delay doesn't matter). Also use the DCMs to generate a daughtercard 140 MHz to use as a DDR output clock for your outgoing 280 Mbps data. Back on the motherboard, you'll need a dynamic or cable-length-calibrated fixed phase shift of the master 140 Mhz to re-clock the data, as a two meter round trip cable delay is longer than a bit period at 280 Mbps. have fun, Brian (Note 1) Digikey, 3db 100 ohm diff. 0404, EXB-24AB3CR8X (Note 2) using a good differential osc. to directly clock the output DDR register, without using a DCM, will avoid cascading two DCMs in the overall link. SDR with 280 MHz clock or DDR with 140 Mhz clock. (Note 3) the DCMs have an input divider, which may be rising edge triggeredArticle: 89705
Hi Andre,
There are two separate attributes; one for input registers and one for
output registers.
Use "fast_input_register = on" to put a register that is capturing an input
to the FPGA from an I/O cell into the I/O cell.
Use "fast_output_register = on" to put a register that is storing a value
that drives an I/O cell (either the data port or the OE port) into the I/O
cell.
You can set these attributes either on registers or on I/O cells. So if you
have a bidirectional I/O, and want both the input path and output path
registers for the signals into and out of the I/O cell to be implemented in
the I/O cell, set the altera_attribute on the I/O to be:
"-name fast_input_register = on; -name fast_output_register = on"
Alternatively, you can just set timing constraints on your I/O paths in
Quartus, and it will move registers into the I/O cells if that will improve
your timing. In that case, you don't need to make any fast register
assignments. You should really make I/O timing assignments no matter what,
since (1) you want to know if you violate a constraint on your design, and
(2) there are other I/O timing optimization decisions Quartus makes besides
just where to put the registers connected to an I/O, and those optimizations
need timing constraints to guide them.
Regards,
Vaughn
Altera
[v b e t z (at) altera.com]
<ALuPin@web.de> wrote in message
news:1127388093.247646.196300@g14g2000cwa.googlegroups.com...
Hi Subroto,
I think the use of attributes in VHDL modules can be helpful for the
purpose of
clearness and readability.
Regarding tristate buffers I have the following additional question:
Let's assume the following description of a bidirectional bus with
tristate buffer:
ENTITY xy IS
PORT ( ...
DataInOut : INOUT std_logic_vector(15 downto 0);
...
END xy;
ARCHITECTURE gt OF xy IS
BEGIN
DataInOut <= ls_datareg WHEN ls_drive='1' ELSE (OTHERS => 'Z');
-- with ls_datareg and ls_drive being registers.
END gt;
What does the Altera fitter do if I use the
useioff attribute for the bidirectional DataInOut ?
Does the fitter implement fast input registers as well as fast output
registers ?
Best regards
André
Article: 89706Adrian, I am aware of the tools provided by Xilinx. The reason I make my own is that I just want to know how everything works, and I think it would be nice to have everything in 1 tool for the picoblaze. The 'work' is for me the fun part. Thanks for the suggestion anyways.Article: 89707
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Date: Tuesday, 6th of December 2005
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o Mike Hutton, Altera: 'The Design of Modern FPGA Architectures'
o Steve Wilton, University of British Columbia: 'Power-Aware
Computer-Aided Design (CAD) Techniques for FPGAs'
o Jos Huisken, Silicon Hive (Philips Research): 'Design Methodology
for ANSI-C Programmable Co-Processors'
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Article: 89708Hi Subroto, >The useioff or altera_attribute=3D"fast_output_register=3Don", can be made= on >the submodule of a design because it is really an assignment to a register >to tell it to be packed into the I/O. But the handbook says the following: The useioff synthesis attribute takes a Boolean value and can only be applied to the port declarations of a top-level Verilog HDL module or VHDL entity (it is ignored if applied elsewhere). So is it not possible to use "useioff" in submodules ? Rgds Andr=E9Article: 89709
Hi Jan, Have a look at Dialite (http://www.temento.com/solutions/fpga.php). This product allows you to add instruments like monitors/switches etc at the RTL level which you can then interrogate/control using either a GUI, TCL/C++/Perl or (D)COM interface. The interface is either the native FPGA jtag TAP or a customer one. I believe that FS2 (http://www.fs2.com/) provides something similar, Hans www.ht-lab.com <janbeck@gmail.com> wrote in message news:1127323604.796057.170150@g44g2000cwa.googlegroups.com... > Hi. > I have a simple board with an Spartan 3 FPGA and a AD connected to it. > The board is configured via JTAG using the Xilix Platform Cable USB (24 > Mhz). What I would like to do is to capture the data from the A/D > converter to the computer via JTAG. Does anybody know of a good way to > do this with the Xilinx applications (Chipscope, System Generator, > etc)? Or maybe with a 3rd party tool? > > I appreciate any information, > > JAn >Article: 89710
I'm designing a flash controller, target is ATMEL AT49BV160C. It's a 16-megbit (1M x 16) 3-volt Only Flash Memory. Here's the datasheet : http://www.atmel.com/dyn/resources/prod_documents/doc3367.pdf ---- I use Xilinx FPGA (Spartan 3, XC3S1000 FG456 -4) for the controller, but i cannot find the corresponding Simulation Model (in VHDL) to do the simulation job. Can somebody give me some hints or useful links or especially the similiar Simulation Model than can simulate the ATMEL AT49BV160C flash action. Best regards & Thanks!Article: 89711
To exchange flags (1 bit signals) between two unrelated clocks, a single synchronizer flip flop to clock that signal is used normally. However, under violations of setup/hold times of the flip flop, metastability can occur. On a Virtex2 Pro, does metastability occur often? Does adding a second (or even third) flip flop after the synchronizer flip flop help or is that overcautious? Best Regards, Simon HeinzleArticle: 89712
Thanks a lot, I will read it. Thanks to everyone GioArticle: 89713
i dont want to use Impact.. the project requires me to write APIs in C code such that i can download the bit file w/out using any special softwareArticle: 89714
On Fri, 23 Sep 2005 13:37:11 +0200, Simon Heinzle wrote: > To exchange flags (1 bit signals) between two unrelated clocks, a single > synchronizer flip flop to clock that signal is used normally. However, under > violations of setup/hold times of the flip flop, metastability can occur. > > On a Virtex2 Pro, does metastability occur often? Does adding a second (or > even third) flip flop after the synchronizer flip flop help or is that > overcautious? > > Best Regards, > Simon Heinzle Standard practice is two flip flops not one. It's been decades since I looked at the math but as I recall there is a square law involved, i.e. the probability of a double synchronizer failing is the square of a probability of a single synchronizer failing. Someone who has looked at this more recently then me might say that my math is wrong but in any event there is no question that a double synchronizer is significantly better than a single synchronizer.Article: 89715
I went through all the xapps but i dont think they have mentioned clearly.. also i am trying to code in C .. one thing i dont understand is .. if i code in C .. how is the JTAG cable going to understand the commnads or the signals to be sent ??Article: 89716
Simon Heinzle wrote: > To exchange flags (1 bit signals) between two unrelated clocks, a single > synchronizer flip flop to clock that signal is used normally. However, under > violations of setup/hold times of the flip flop, metastability can occur. > > On a Virtex2 Pro, does metastability occur often? Does adding a second (or > even third) flip flop after the synchronizer flip flop help or is that > overcautious? > > Best Regards, > Simon Heinzle There have been many good threads on this subject. You may want to Google this group for "metastability." That being said, the answer is of course "it depends." The number of stages required depends on your clock rate, the metastability characteristics of the flip-flops, and your required failure tolerance. Generally two stages are used, however it is possible to get away with one if the signal is only used at the next edge of the clock (which is almost like two stages except the second stage may have less tolerance for metastability if there is a LUT between the two stages). In any case, make sure the input is synchronized only once to avoid possible logic errors. This may seem obvious, but if your "single-stage" synchronizer output has many loads the tools may duplicate the flip-flop for you unless you specifically tell them not to. In the case of a two-stage synchronizer, only the second flip-flop might be duplicated as the fist stage has just one load. Also the routing delay from first to second stage can become important at higher frequencies. Just my 2 cents GaborArticle: 89717
"Simon Heinzle" <sheinzle@student.ethz.ch> wrote: >To exchange flags (1 bit signals) between two unrelated clocks, a single >synchronizer flip flop to clock that signal is used normally. However, under >violations of setup/hold times of the flip flop, metastability can occur. > >On a Virtex2 Pro, does metastability occur often? Does adding a second (or >even third) flip flop after the synchronizer flip flop help or is that >overcautious? Xilinx has a application note on this general subject: http://www.xilinx.com/bvdocs/appnotes/xapp094.pdf While adding multiple stages can reduce the risk of a metastable failure, it is not the only way to do so. Both the odds of a metastable failure and the consequences of that failure are important. The odds can be improved by increasing the settling time. See figure two in the application note. To make sure there is enough settling time, typical designs might both put an additional timing constraint between the synchronizer FF and the next FF or FFs, and put physical constraint (LOC or RLOC) on these FFs to position them for minimal delay. The consequences can sometimes be improved by making the rest of the design more robust. Examples might be to design the logic to recover from a metastable failure, to make the software check the data and ignore/correct invalid values, etc. -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 89718
Anuja - Xilinx has a sample program called 'playxsvf' that you can customize to your environment. You use the normal Xilinx tools to create your bitfile, then convert it to a .xsvf file. This is the file that playxsvf downloads. You can get the source code from the Xilinx web site, I believe it came with one of their app notes. You then need to modify the source code to work in your environment. I've modified the original code from Xilinx to work in several different environments including one with some dedicated hardware to do the bit shifting. So look around for playxsvf! John ProvidenzaArticle: 89719
Anuja - I found the XIlinx App note that describes playxsvf - look for XAPP058 John ProvidenzaArticle: 89720
I stumbled across a presentation at MAPLD regarding various C-to-gates tools. The authors at U of F compared several tools to a pure VHDL implementation and discovered that for each application (FIR filtering, N-queens, and radix sorting) a particular C-to-gates tool, usually Handle-C, beat a hardware designer using VHDL. The presentation can be viewed at: http://klabs.org/mapld05/presento/215_holland_p.ppt This goes against my common beliefs regarding hardware designers being many times more efficient. Does anyone have experiences with C-to-gates tools that would bolster or contradict the authors' claims? StephenArticle: 89721
"Anuja" <thakkar.anuja@gmail.com> schrieb im Newsbeitrag news:1127483599.347945.252720@g14g2000cwa.googlegroups.com... > I went through all the xapps but i dont think they have mentioned > clearly.. also i am trying to code in C .. one thing i dont understand > is .. if i code in C .. how is the JTAG cable going to understand the > commnads or the signals to be sent ?? To access the parallel port or USB, you need a driver. Regards FalkArticle: 89722
Was just told about this site at National Semiconductor. Great idea. Means I no longer need to worry too much about my power management for all my Altera FPGA designs - they support Xilinx too ! Check it out at http://www.national.com/appinfo/power/xilinxfpga.htmlArticle: 89723
Hello Moh,
I have only one master So there is no problem of arbitration I guess.
The problem is that the M_request remains constant at '0'. with no
change even when I try to request a master write operation in my
user_logic.vhd
I enable my IP2bus_wrreq high place a valid address and data on the
IP2bus_addr,IP2bus_data,
IP2Bus_Retry <='0';
IP2Bus_Error <='0';
IP2Bus_ToutSup <='0';
IP2Bus_RdAck <='0';
IP2Bus_WrAck <='0';
My only doubt is what address should we assign to IP2IP_addr.
I think thta is the one which gives the problem.
There is absolutely no change in the signal on the OPS-IPIF side.
Thanks
Nitesh
Article: 89724I was present at this presentation at MAPLD a couple of weeks ago and also spoke with several of the authors. I work with Nallatech, one of the companies who gave Brian Holland a product to evaluate. I don't think that you can read from this presentation that any 'C-to-gates' tool is superior to VHDL. Given the time, an experienced VHDL designer will generally do a better job than an automated tool. The key word here though is time. The logic density on FPGAs is increasing at a high rate. The performance of this logic is also increasing. In the past, when balancing Design Time, Performance and Resource Use, automated tools would use up too much precious resource and wouldn't reach the challenging performance targets. As high-level-language hardware-description compilers have improved their performance with respect to resource use and performance, so has the pressure in these areas decreased. This leaves the key area of design time. Where design time is tight, a HLL-HDL compiler might be the only viable option. Take a look at the following presentation and abstract: http://klabs.org/mapld05/presento/220_feifarek_p.ppt http://klabs.org/mapld05/abstracts/220_feifarek_a.html Here a team with experienced VHDL designers and, notably, not C-to-gates iconoclasts, chose to go the Handel-C route on their project. We're not talking a 'Mickey Mouse' project either. We're talking about a system being built to repair the Hubble Space Telescope by Lockheed Martin. Time was short, I believe they were given three years from getting the contract till launch (not long, in space terms). They reported positively on their experiences. One thing they pointed out though, was that it would have been a good idea to have an experienced user of the Handel-C tool onboard from the start. They're useful tools, but they're not gcc-for-FPGAs just yet! I don't think that Brian would claim to be an expert in all the languages he examined for this project, and I don't think anyone's making any claims about this study being the last word in comparing and contrasting these languages to each other and VHDL.
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