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"B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com> wrote in message news:pan.2005.09.27.20.02.31.560444@PleaseDontSpamMEpolybus.com... > On Tue, 27 Sep 2005 12:07:10 -0700, Symon wrote: > > I bet that's what the Army Core of Engineers thought when they designed > the levees in New Orleans. The design spec was for a 200 year event, none > of those guys expected to be around in 200 years. We'll guess what, a 200 > year event is another way of saying that there was a .5% chance of that > event happening in any one year. The chances of two such events in the > same year is .0025 percent, sounds pretty small doesn't it. But it > happened because .0025% isn't zero. > That's a bit of a cheat because I don't believe Rita would have breached the levees on her own. The structures hadn't been properly rebuilt after Katrina. Also, it's possible that multiple big hurricanes in one season aren't statistically independent events. If the summer's sea/weather conditions are good for one hurricane, why not for two? Cheers, Syms.Article: 89826
Some of it depends what size/type device you are using, and how much money you would like to spend. The DO-ML403-EDK-ISE seems to be a good deal if the target is a FX12 part http://www.xilinx.com/xlnx/xebiz/productview.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1210985&iLanguageID=1&category=/Xilinx+Products/Hardware+and+Cables/Development+Boards/Virtex-4+Boards If FPGA's and ASIC's are not in your immediate future, I would pass on Synopsys. Xilinx Synthesizer works pretty well, and is bundled with the implementation tools. The above package comes with a baseX version that limits the size of the device. The full version costs more. Synplicity is regarded very well, and has the advantage of being able to target different vendors as with Synnopsys and Mentor. Don't really have any data on Mentor. BTW. I own Synplicity stock. -Newman Waage wrote: > Hi, > > I are looking to purchase some FPGA software in the very > near term for a project utilizing Xilinix's Virtex-4 device. > > I are relatively new to FPGA design and would appreciate any comments > from those who have experience with Virtex-4 regarding FPGA synthesis > software > options. > > I have looked at Mentor, Synplicity, Synopsis, and Xilinx solutions. > Are there any recommendations for or Against any of the above? > Am I missing a good resonably priceds third party option? > > Thanks, ChrisArticle: 89827
I am looking at Avnet's Xilinx-4 LX Evaluation Kit. Has anyone here worked with this board? Is it worth the Money? Is there a better one out there with a similar price? Does anyone know if you can configure the FPGA via the boards USB. Thanks, ChrisArticle: 89828
I tried the ILA tutorial example exactly the way given in the document. I tried the vio. No luck either. "waiting for core to be armed,slow or stopped clock " I tried the same stuff on a windows machine.Still no luck. I get the same result.Article: 89829
Peter Alfke wrote: > Your wear-out analogy does not apply. I did not use only a wear-out analogy, although I did mention some possibly wear related factors. On the flip side, many circuit components also have infant mortality failure rates. > Metastability failure is > completely statistical and probabilistic. Even when the MTBF > is a million years, the failure can occur in the next second. The same is true of a meteor strike on the circuit under question (given that many are in chaotic orbits), as well as radiation upset events, thermal noise, even someone tripping over the power cord, etc. > That's why I claim that the problem can never be solved. We can > only reduce the probability down to an acceptable level. Then the same must also be true of completely synchronous logic, because various other design issues also have probability factors which must also be reduced to acceptable levels to meet design goals. Good engineering usually involves balancing several risk factors so that all meet acceptable limits, and without wasting extra effort on those that are well away from being the limiting factor. And I'm not saying that metastability is not a problem at all (having had to debug a few poorly designed asynchronous input to synchronous logic circuits in my junior engineer days). But there are a number of papers on the subject which essentially reduce some forms to solved problems for many given reliability levels when using properly designed and characterized flip-flops (as I assume your employer has done) with sufficient delay time and/or delay cycles for resolution with a probability which meets or exceeds that required for the given product reliability. IMHO. YMMV. -- Ron rhn A.T nicholson d.O.t C-o-MArticle: 89830
Why don't you used Chipscope Inserter instead of instantiating ILA and ICON in your design? According to my personnal experience, when Chipscope says "Waiting for Core to be armed, slow or stopped clock", it generally means that your system clock is not working. --------------------------------------------- -- TechwaY -- TechwaY Partners -------------------------------------------Article: 89831
Problem solved. Sorry for taking up space (and bumping)... Left clicking on icon is export and selecting "Program Device" works fine. Cheers! ((miceArticle: 89832
> I need an ARM environment, hopefully a complete ARM9 and bus, on an > FPGA to prototype multiple copies of a custom, loosely coupled, media > signal processor. The MSP is about 50K (real) gates with 16KB of > dual-port memory on each. I'd like to try to hang two of them (total > 100K gates and 32KB dual-port) off an AHB or AHB2 to test the > interprocessor communication with an RTOS plus driver/manager software. > > The old Altera Excalibur looks like the ideal solution, especially if I > can find an old EPXA10 DDR Dev Board. While not identical to what you specified, this still might be of interest to you ... http://www.actel.com/products/ip/ARM7.html KrisArticle: 89833
I tried both ways , instantiating as well as the inserter but still no luck. NiteshArticle: 89834
This has degraded into quibbling over semantics. I have documented quantitative data about the MTBF of metastability (Xilinx app note XAPP094), and I have stated publicly that it is not a real problem in all but very extreme cases. So nobody can say that I advocate scare tactics. It is, however, a fact that, whatever the MTBF, metastability-caused errors are always a (very remote) possibility. Enough said. I will not continue this "discussion". Peter AlfkeArticle: 89835
I'd like to hear from anyone who has experience or knows of any FPGA based implementations of Dolby Digital AC-3 decode (or similar algorithms) on an FPGA. Specifically, I'd like to find out how resource intensive this may be. Any comments would be appreciated. - PCArticle: 89836
"Waage" <chris@ednainc.com> wrote: >I have looked at Mentor, Synplicity, Synopsis, and Xilinx solutions. I've had good experience with Synplicity. Smaller and faster results, easier to use, good technical support. Xilinx does ok. Price is right. Good choice as long as speed and density are not critical, or if speed and density are so critical as to force the designer to map all logic by hand. -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 89837
Subroto Datta wrote: > It's possible that the driver was improperly installed/uninstalled by > the installer. Try running 'bblpt /r' followed by 'bblpt /i' from the > quartus\drivers\i386 directory. > Thank you. It must be this problem. I deleted my printer, and downloaded a new copy and it now works. That was before I saw your answer so I didn't run the bblpt command. vax, 9000Article: 89838
Paul wrote: > Neil, > > We use PVCS for version control with our VHDL, and it works just fine. The > only tricky part is figuring out what files (beyond the vhdl) that your tool > really needs to recreate a particular version, such as constraints, cores, > and project setting files. Since we use 3 different tools (Active-HDL / > Synplicity / Xilinix ISE), it took a while to figure out which files store > which configuration information to truly recreate a project from pvcs. I > would recommend creating the pvcs project folders to exactly mirror your > fpga working folder structure. > > -Paul > QuadTech > Can you tell us a little more? I am just starting a big new FPGA project, using the same set of tools, in a company which doesn't have a methodology for FPGA version control. How can you save a project in a way that a "get all" command prepares the entire environment? I'd like to be able to get all project files to any random root folder and be able to work immediately. I've already seen some problems: * ISE, Synplicity and Active-HDL have their own project files; if the source-files are not in the tool's project folder-tree, the project file records the absolute path to the file. How do you change your project/version root-folder without manually enering all files again in all tools? * CoreGen creates net-lists in its own folders; you have to manually copy them to the ISE root folder.Article: 89839
Ok. So: the jbits is just an illusion and reverse engineering the bitstream is too complex. What about accessing the internal configuration data? what is the degree of complexity and the limits of this approach? Another (which may solve definatly the problem :) ) would create from scratch an open source FPGA :)Article: 89840
Concerning the Bitstreams and the protection of designs. I think that it would be very easy for FPGA vendors to make FPGAs which offer two modes of functionning: a secured mode which uses encrypted bitstreams (for ultra-secret applications :) ) and a "non-secure" mode for use in cases where the protection of the low level infos is not important.Article: 89841
I've got some trouble on installing ise7.1 webpack on the debian linux
system, when I run the .sh file from the command line ,I got following
error:
Cannot register service: RPC: Unable to receive; errno = Connection
refused
unable to register (registryProg, registryVers, tcp)
Wind/U Error (248): Failed to connect to the registry on server
debianDevlin
Wind/U X-toolkit Error: wuDisplay: Can't open display
I use the google search but didn't find any useful information, could
any body do me a faver to help me?
thanks.
Article: 89842PeterC schrieb: > I'd like to hear from anyone who has experience or knows of any FPGA > based implementations of Dolby Digital AC-3 decode (or similar > algorithms) on an FPGA. > > Specifically, I'd like to find out how resource intensive this may be. > Any comments would be appreciated. I believe the processing power requirements of AC-3 decoding are similar to multi channel mp3 decoding. In that case a microblaze processor with some extra hardware for DCT and Huffmann should be sufficient. Of course you can also do a full hardware implementation, but for the software one you can port some open source software decoder. Kolja SulimmaArticle: 89843
Dear all, last year I started to design the back end of a "Small C" compiler for the picoblaze microcontroller. (You can download it on www.poderico.co.uk) I haven't done much for the last two months... but now I'm ready to continue my development. I'm looking for some help in the development. Do you want to help me? The compiler has still some bugs and it will be nice to have a bug free compiler, for all the Picoblaze users :-) How I said the compiler is a version of "small C" Is well coded (considering that I'm an hardware designer :-)) The source code is still not on my webpage, but it will be there soon. I hope to have some follower :-) thanks, FrancescoArticle: 89844
If you can afford the price of Synplicity, I would definitively recommend you Synplify Pro for the quality of its results. The only drawback that I think of is stability. It performs very well but it might (not so rarely) happen that it crashes w/o any result. Fortunately, the support is very reactive to provide us w/ new releases fixing the issues. Has someone a significant experience w/ Amplify (or the new SynplifyPremierDP) from Synplicity? What do you think about it? EricArticle: 89845
francesco_poderico@yahoo.com wrote: > Dear all, > last year I started to design the back end of a "Small C" compiler > for the picoblaze microcontroller. > (You can download it on www.poderico.co.uk) > I haven't done much for the last two months... but now I'm ready to > continue my development. > I'm looking for some help in the development. Do you want to help me? > The compiler has still some bugs and it will be nice to have a > bug free compiler, for all the Picoblaze users :-) > > How I said the compiler is a version of "small C" Is well coded > (considering that I'm an hardware designer :-)) > > The source code is still not on my webpage, but it will be there soon. > > I hope to have some follower :-) > thanks, > Francesco Sounds good - you might want to also look at the Lattice Mico8 - that is opensource, so you can nudge the opcodes. It is quite close to the PicoBlaze, but Mico8 is generally a superset in opcode 'reach'. You can expect them to be more similar than different, as both have 18 bit opcodes, and are designed for FPGA usage. Alfred Arnold has recently added the Mico8 to his AS assembler found here http://john.ccac.rwth-aachen.de:8000/as/download.html -jgArticle: 89846
The one main complaint I have with symplify is the number of warnings and messages it generates... I like to check them off and say "that's ok" ... "that's unnecessary" etc .. but I haven't found a way to turn the unnecessary ones off. Typically this happens on some of my standard modules which might have unused pins or internal blocks which are going to be optimized out, but will leave a signal or two (which will also be optimized away). Altera fixed this with the 'if_used' attribute in AHDL... but that's gone by the wayside since AHDL isn't supported any more. The other annoying one is where ROMS are generated and it optimizes columns out as they aren't unique ... something's you just don't care about :-) Simon "Eric DELAGE" <delage.eric@gmail.com> wrote in message news:1127894398.431062.117290@g49g2000cwa.googlegroups.com... > If you can afford the price of Synplicity, I would definitively > recommend you Synplify Pro for the quality of its results. > > The only drawback that I think of is stability. It performs very well > but it might (not so rarely) happen that it crashes w/o any result. > Fortunately, the support is very reactive to provide us w/ new releases > fixing the issues. > > Has someone a significant experience w/ Amplify (or the new > SynplifyPremierDP) from Synplicity? What do you think about it? > > Eric >Article: 89847
I've a project with a powerpc and some userperipherals (connected through ipif at the plb bus). The plb bus is running at 100 MHz and the powerpc is running at 200 MHz. In a virtex2pro vp30 device (speed grade 5) this design is giving no problems with building (all timing constraints are met). Now I changed the design to use it in a virtex4fx60 (speed grade 10). The plb bus frequency is increased to 125 MHz and the powerpc to 250 MHz. Now I get timing errors. Is this unexpected? (I mean it's only an increase of 25 percent, but the used device is a virtex 4; I was expecting that this small frequency change shouldn't give any problems for a virtex 4). Does anyone have experience with running the plb bus at 125 MHz and using the ipif interface? TIA, FrankArticle: 89848
seabrench@163.com writes: > Hi everyone!Who have been done this aspect?I want to do this,but i > don't how to do.Can you give some advice?For example,i want to do image > feature extraction based on FPGA.I'm a learner.Thank for your ideas. > Image processing can be done in FPGAs. But it sounds like you don't know what image processing you want to do... First figure out what your algorithm is going to do, using Matlab, C-code, pen-and-paper, or whatever tools seem most appropriate. Then figure out what the hardware to do that function will look like. Finally, you can write some VHDL or Verilog for your FPGA! HTH! Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 89849
Phil Hays <Spampostmaster@comcast.net> writes: > "Waage" <chris@ednainc.com> wrote: > > >I have looked at Mentor, Synplicity, Synopsis, and Xilinx solutions. > > I've had good experience with Synplicity. Smaller and faster results, > easier to use, good technical support. > > Xilinx does ok. Price is right. Good choice as long as speed and > density are not critical, or if speed and density are so critical as > to force the designer to map all logic by hand. > I've had one recent experience where XST did better (timing-wise) than Synplicity. Unfortunately, I don't really know why as it was not my code. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt
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