Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"Maki" <veselic@eunet.yu> schrieb im Newsbeitrag news:1128094155.370117.103310@g44g2000cwa.googlegroups.com... > Hello all, > > Anybody knows when we can expect LFXP3 & LFXP6 in regular distributor > channels? > hm XP10 was available last month, I think the XP6 is also available as there are readily available (from stock) eval boards with soldered XP6 on it, so they have been available- only ES as far as I know though. AnttiArticle: 89951
Welcome back Antti :)) Thanks for the info. Have You tried these devices? Any experience? M.Article: 89952
"Maki" <veselic@eunet.yu> schrieb im Newsbeitrag news:1128095038.183000.281450@o13g2000cwo.googlegroups.com... > Welcome back Antti :)) > Thanks for the info. Have You tried these devices? Any experience? > > M. > No. I dont have 60EUR from my pocket for the eval board. (I have too many eval boards already in private posession). I just did see yesterday that the developer of the lattice eval boards who works with MSC has the new XP6 based board in stock available for immediate delivery. But... I do have a board with Lattice EC on my desk, the EC is used PLL and configuration controller to boot a Virtex4, so doing some simple design with the EC was very easy. Knowing Lattice tools from the past (isp1016 !) I did expected it to be easy. As the XP is basically the EC with onchip flash then, then I would not expect much more problem with XP as well. Antti PS a warning for V4 users: check out the datasheet all pins that have _LC_ do not have LVDS output capability (all bank 0..3 on some packages), just a firendly notice to avoid some burned fingers. Its not so clear from the V4 datasheet unless you read it very carefully.Article: 89953
as topic says. any device in any package as chip only (can be bga as long as its not bare die) or soldered on board (that can be partially non functional) as long as jtag pins are connected to accessible points. can somebody help? I can pay as private person (but can not place order). AnttiArticle: 89954
praveen.kantharajapura@gmail.com wrote: > Hi all, > > I have a question on POR(Power on reset generation ) using FPGA. > My FPGA does not have a external Power ON reset , i am planning to > generate a Power ON reset in the FPGA only.Is it really feasible to > do this in an FPGA, and use this as the reset for my logic. > Any suggestions appreciated?? As Antti mentions, most FPGAs nowdays have an asynchronous power on reset built in. Assuming you want an internal synchronous reset, just create a large counter which is will count down once after an asynchronous reset. A synchronous reset would be held until the counter finishes (of course, don't apply the synchronous reset to the countdown counter;)Article: 89955
Kutaj, Lattice offers the free "ispLEVER-Starter" package for PCs at www.latticesemi.com. It provides several modules to download Lattice implementation tools including Precision RTL or Synplify logic synthesis for Lattice FPGAs. After you've studied a VHDL text book, I'd recommend the User Guides from the respective logic synthesis vendors. These will provide practical examples and style guidelines to write good RTL. Cheers, Troy Scott Lattice SemiconductorArticle: 89956
fastgreen2000@yahoo.com wrote: > I'm not sure if this is VHDL or Modelsim issue (other than operator > issue), so I'm posting in both groups. It looks like too simple a case > to ask someone online, but I've been scratching my head too long on > this. I'm relatively new to VHDL (and Modelsim as well). > > In a testbench, I'm doing a simple signal generation : > - assert 'sig1' at a rising edge of a free running clock at some point > - deassert 'sig1' at the next rising edge > - and on the 3rd edge, do some checking, and so on... > > However, the simlation waveform shows that 'sig1' is asserted from 2nd > to 3rd clock edge, instead of being asserted from 1st to 2nd edge. > > What am I doing wrong? I've included both snippets from the testbench > and the debug output. I expected 'sig1' asserted from 314 to 318ns. > Simulation waveform shows assertion from 318 to 322 ns instead. Any > help would be appreciated. I simulated your code with modelsim, and aside from different times: 1st rising edge : 1015000 ps 1st rising edge (again) : 1015000 ps 2nd rising edge : 1023000 ps 3rd rising edge : 1031000 ps I see sig 1 asserted from 1015000 ps to 1023000 ps. So something else appears to be going on in your case.Article: 89957
Hi All, I am developing a board using Virtex FPGA. Right now i am using Protel, but i am not being able to use the "Equilize net lenghts" nor the auto-route. I wonder if there is any software better than protel to develop pcb boards. Does any one know which software xilinx use?? TanksArticle: 89958
Gabor, I've been able to the GUI environments for ISE, ispLEVER, and Quartus with no modifications under Win2000. However, if you run your program executables from the command line, you will need to manage the enviroment variables for ISE and ispLEVER since the tools use similar executable names (NGDBuild, MAP, PAR, etc.). I've also found conflicts between the Actel and Lattice-Editions of Synplify which are provided with the free "starter" tools. Best Regards, Troy Scott Lattice Semiconductor TMEArticle: 89959
I'm doing a proof of concept that requires high quality video out. Either RGB or composite is fine (both would be great). Spartan III or V4 preferred, with add-on modules OK. The ML401 is a great board, and great value, but the rgb output just sucks. Anyone got any recommendations? ThanksArticle: 89960
I'm glad you don't see the same problem, because that would've puzzled others as well. Would you mind posting what your testbench looks like? I initially suspected my clock generation as Zara suggested, but that doesn't quite make sense to me. I'll use process of elimination on differences and see what's causing this. I'll post the result as well. TIA.Article: 89961
Duane Clark wrote: > Andy Peters wrote: > > > > Certainly in ModelSim and ISE, you can specify relative paths as you > > add files to the project. Sometimes I forget and have to manually edit > > the ModelSim project file to make the paths to the sources relative. > > Once it's done, though, it sticks. > > > > Versions of ISE through 6.3 handled relative paths quite well. And the > project file was plain text, another handy thing for making sure what > was going on and making changes. > > With ISE 7.1, I no longer seem to be able to use relative paths. If you > know how to, please let me know! Dunno -- it just works. If you're creating a project with existing sources, make sure that you don't check the "copy to project" option when adding them to the new project. I just did a quick test. I created a new project without adding sources. I then chose the "add existing source" option. I added some sources that are on the same disk drive as the project, and those were added using relative paths. I then added a couple of files that were on a different drive, and those were added using absolute paths. Of course, this is a Windows machine -- maybe if you were on Linux or Solaris, this wouldn't be an issue (no frickin' drive letters). If that's not the case, then, well, complain to Xilinx! > And some bonehead decided to make the > project file into some binary format. Arggh! It's not completely binary; you can open it in a text editor. It does have binary cruft in the beginning, but scroll down and you can see your sources and such listed. But I agree: configuration and project files should always be simple plain text -- no XML, no binary, just good old-fashioned text. And it would be nice if automated tools didn't totally reorder things in those text files. diff is your friend, so make diff's life easier! Tools vendors should strive to make their products revision-control friendly. By that I DON'T mean adding support for Microsoft Visual Source Safe. VSS is not an acceptable revision-control system. -aArticle: 89962
Has anyone else received this error with ISE 7.1i? I added a peripheral to my embedded system, and when I re-synthesize it it XST, I get: ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 798040 kb. Memory problems may require a simple increase in available system memory, or possibly a fix to the software or a special workaround. To troubleshoot or remedy the problem, first: Try increasing your system's RAM. Alternatively, you may try increasing your system's virtual memory or swap space. If this does not fix the problem, please try the following: Search the Answers Database at support.xilinx.com to locate information on this error message. If neither of the above resources produces an available solution, please use Web Support to open a case with Xilinx technical Support off of support.xilinx.com. As it is likely that this may be an unforeseen problem, please be prepared to submit relevant design files if necessary. Any ideas? Thanks, -- Matt +-- |Matthew Plante | University of New Hampshire | InterOperability Lab | Research & Development | SMTP: maplante@iol.unh.edu | Phone: +1-603-862-0203 +-Article: 89963
David Brown wrote: > I have been thinking along the same lines. For the most part, all our > developers will have access to everything (we are a small group) - if > someone deletes something by mistake, it can always be "undeleted" > (that's part of the point of a revision control system!). I also plan > to allow https access from certain home machines (saves any need for a > vpn), and maybe even occasional customers for colabaration projects. One cool feature is that you can give different users different permissions. For example, customers can be given read-only access to the repository, so they can't check things in. > Do you find that subversion works well for binary files too (obviously > without differencing and merging), like object code or pcb design files? It works quite well for binary files. You just have to be real good with comments. Things like "checked in newest version" doesn't tell you anything if you can't diff the files. -aArticle: 89964
henrique.portela@gmail.com wrote: > Hi All, > > I am developing a board using Virtex FPGA. Right now i am using Protel, > but i am not being able to use the "Equilize net lenghts" nor the > auto-route. > I wonder if there is any software better than protel to develop pcb > boards. Does any one know which software xilinx use?? Both features can be considered experimental. There are other packages, not to be considered bargain packages such as protel that are able to do this. Are you sure you want to learn it price ? ReneArticle: 89965
Andy Peters wrote: > You have to be smart about how you create your projects in the first > place. > > Certainly in ModelSim and ISE, you can specify relative paths as you > add files to the project. Sometimes I forget and have to manually edit > the ModelSim project file to make the paths to the sources relative. > Once it's done, though, it sticks. > > Active-HDL sorta drove me bonkers, as it has its own way of organizing > things and I never did figure out how to convince it to use my > particular source tree format. I've looked into Active-HDL project file (.ADF) and it appears to be a simple text, with all files recorded TWICE (files and files.data) - who knows why? I'll try playing with it and see what happens. There is also the compilation-order file, surprisingly called compilation.order. The file-paths in it are already relative. > > Here's how I set up my projects: > > projroot\ > \src\ top level for synthesizable source code > \moduleA some convenient synthesizable module > \moduleB another module > \testbench\ test bench sources, project file, scripts > \modelA behavioral testbench model (an SRAM, perhaps) > \modelB another simulation model (PCI core, maybe) > \fitter\ FPGA constraint, project, build, Makefiles > \synth\ synthesis-tool scripts, project etc files > \docs\ READMEs, theory, explanations, requirements, > etc > > Some points: > > The src directory and its subdirectories contain only synthesizable > sources. > I didn't try creating the tools' folders below the project-root, because most tools create an amazing number of junk files. --- SNIP --- > The fitter directory is where FPGA fitter/P+R tool scripts, constraint, > project and Makefiles are kept. Most of the tools have improved such > that they handle relative paths well and anything that copies a source > file to the fitter directory is BROKEN. Obviously, the tools spit out > a lot of temporary files and report files and create "work" > directories. All you need to keep in the version control repository is > the stuff needed to actually build the chip: constraint files, source > list files, etc. Buried somewhere in the tool documentation should be > a list of the various files used and created by the tool. I do NOT > normally keep final build results (.bit, .mcs, whatever) in the > development trunk. I am using the ISE Project Nav GUI; not very user-friendly, but I can't be bothered to create "scripts" (actually batch files) to run the P&R tools from the command-line (been there, done that). ProjNav (ISE 7.1) has a (sort of) BINARY project file (.ISE). It also has a nasty "feature": if you use the "add source" command from the Modules tag, it adds a link to the file; if you use the same command from the Library Modules tab, it copies the file to the ISE folder. What were they thinking of? If a command is called the same, it should behave the same. I also HATE binary configuration files; they don't allow me to play around with things the S/W should have, but didn't, allow to to do via UI. Well, it could have been worse; they could have kept everything in the Registry, the way most Windows programs do today (and I'd like to shoot the guy who invented the Repository - same idiot mentality as "throw it in the garage, we'll find it there later). --- SNIP --- > > > * CoreGen creates net-lists in its own folders; you have to > > manually copy them to the ISE root folder. > > CoreGen is stupid in that regard. When I use it, I create the CoreGen > project in a temporary directory, extract the files needed, and copy > them to the source directory. If I know that I am going to reuse that > Core, I simply put it into the repository as its own project, and add > it to a chip's source as an external. For example, I have the > PicoBlaze processor source in the repository as its own project. > > -a CoreGen project files are also text, and also appear to contain absolute paths; I'll play with these as well. You still have to copy the generated net-list (EDIF or NGD) to the ISE root-folder. I don't like calling tools from the Proj-Nav; I'd rather use each tool as stand-alone. Synplicity's project files are actually TCL scripts; shouldn't be a problem to use relative paths. A final problem: if I keep each tool's folder-tree as separate sub-folders below the project's root, I still have to copy intermediate files manually (synthesis and coregen net-lists); maybe I'll just add a batch file to do it and keep it as part of the project. I guess that I can't create an environment where a know-nothing user can get a project and just hit a button to build everything; unlike software projects (where the whole project is often built by non-programmers such as QA people), an FPGA project must be built by someone who knows at least a little about the tools. -- Assaf SarfatiArticle: 89966
fastgreen2000@yahoo.com wrote:
> I'm glad you don't see the same problem, because that would've puzzled
> others as well.
>
> Would you mind posting what your testbench looks like? I initially
> suspected my clock generation as Zara suggested, but that doesn't quite
> make sense to me. I'll use process of elimination on differences and
> see what's causing this. I'll post the result as well.
>
> TIA.
>
Watch out for line wrap...
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_textio.all ;
use std.textio.all ;
entity test is
end entity test;
architecture tester of test is
constant CLK_PRD : Time := 10 nS;
signal Clk : std_logic;
signal sig1 : std_logic;
begin
tester_p: process is
file output : text open write_mode is "test.out";
variable L : line;
begin
sig1 <= '0';
wait for 1 uS;
wait until rising_edge(clk);
write (L, string'("1st rising edge : " & time'image(now)));
writeline (output, L);
sig1 <= '1';
write (L, string'("1st rising edge (again) : " & time'image(now)));
writeline (output, L);
-- Wait for the next rising edge, and bring 'sig1' low
wait until rising_edge(clk);
write (L, string'("2nd rising edge : " & time'image(now)));
writeline (output, L);
sig1 <= '0';
-- Wait for the 3rd rising edge
wait until rising_edge(clk);
write (L, string'("3rd rising edge : " & time'image(now)));
writeline (output, L);
end process tester_p;
-- Generate the clock.
clk_gen: process
begin
loop
Clk <= '1' after CLK_PRD/2, '0' after CLK_PRD;
wait for CLK_PRD;
end loop;
end process clk_gen ;
end architecture tester;
Article: 89967"Rene Tschaggelar" <none@none.net> schrieb im Newsbeitrag news:433d7fe4$0$1150$5402220f@news.sunrise.ch... > > I am developing a board using Virtex FPGA. Right now i am using Protel, > > but i am not being able to use the "Equilize net lenghts" nor the > > auto-route. > > I wonder if there is any software better than protel to develop pcb > > boards. Does any one know which software xilinx use?? > > Both features can be considered experimental. > There are other packages, not to be considered > bargain packages such as protel that are able > to do this. Are you sure you want to learn it > price ? And beside, the automatic "Equalize net lenght" in other REALLY expensive EDA packages (lets say from vendor "M") isnt that usefull at all. Best results with minimum trouble is to use a half-automatic tool (such a thing that displays the actual netlength in real time while you move the traces). Been there, done that. Regards FalkArticle: 89968
Can you give me examples of software with that feature?Article: 89969
<henrique.portela@gmail.com> schrieb im Newsbeitrag news:1128106917.840181.240320@g47g2000cwa.googlegroups.com... > Can you give me examples of software with that feature? As I said, vendor "M" (aka Mentor Graphics) has this feature. But the packages are REALLY expensive. I dont know about other (mortal price) software with this feature. Regards FalkArticle: 89970
Thats good Idea, but which boards have u tried before......Article: 89971
Any chance of donation.....Article: 89972
Andy Peters wrote: > Duane Clark wrote: >> ... >> With ISE 7.1, I no longer seem to be able to use relative paths. If you >> know how to, please let me know! > > Dunno -- it just works. If you're creating a project with existing > sources, make sure that you don't check the "copy to project" option > when adding them to the new project. > > I just did a quick test. I created a new project without adding > sources. I then chose the "add existing source" option. I added some > sources that are on the same disk drive as the project, and those were > added using relative paths. That is the way it always worked for me before. But not now :-( > I then added a couple of files that were > on a different drive, and those were added using absolute paths. Of > course, this is a Windows machine -- maybe if you were on Linux or > Solaris, this wouldn't be an issue (no frickin' drive letters). I'm on Linux. Perhaps they added that as a "feature" just for us ;) > > If that's not the case, then, well, complain to Xilinx! If it is working right on Windows, then indeed I think I'll complain.Article: 89973
I would like to write a parameterizeable component in vhdl that would do an N element fixed point dot product. I was wondering if there was a (synthesizable) way to generate a first stage of multiplies (ceil(N/2) multiply blocks), and then ceil(log2(N)) - 1 add stages. I would like to be able to use generics to specify the length of the vector and the bit width (this in turn specifies the length of the MAC pipeline). -- Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 89974
Hi, How does one read back specific bits using JBits 3.0? For example, if I want to read back the contents of the F LUT - how do i go about it? I tried jbits.getCLBBits but I get an configuration exception. Ditto with getTileBits. My sample code looks like this: int lut []; lut =jbits.getCLBBits(0, 1, LUT.CONTENTS[0][LUT.G]); Is this correct? If it is, why do i get the configuration exception? Any help on this would be appreciated. Thanks in advance, Sarnath
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z