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> http://cgi.ebay.de/ws/eBayISAPI.dll?ViewItem&item=5825643507 > > that e-book includes ALL instructions how to get an PCI design up and > running. > the PCI core used there is VERY simple and usually works out of box, you > just assign PCI IO pins and constraint on PCI clock nothing else. > I have tested the PCI core on spartan 3, virtex2, cyclone and max2 boards. Antti, Does this clearly explain how to get an FPGA based PCI core to emulate an LPT port, and does the C++ include the code that talks to it? Nial.Article: 91251
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> schrieb im Newsbeitrag news:4368d700$0$23295$db0fefd9@news.zen.co.uk... > > http://cgi.ebay.de/ws/eBayISAPI.dll?ViewItem&item=5825643507 > > > > that e-book includes ALL instructions how to get an PCI design up and > > running. > > the PCI core used there is VERY simple and usually works out of box, you > > just assign PCI IO pins and constraint on PCI clock nothing else. > > I have tested the PCI core on spartan 3, virtex2, cyclone and max2 boards. > > > Antti, > > Does this clearly explain how to get an FPGA based PCI core to emulate > an LPT port, and does the C++ include the code that talks to it? > YES. it also includes a LPT connected logic analyzer (uses BRAM's). so original software written for LPT connected logic analyzer does run on the PCI board. the PCI LPT is 'Lava PCI LPT' it is recognized by Windows XP nativly no extra driver just regular LPT (with 16 base address !!!) any software that can talk to LPT can talk to the PCI core, and whatever is connected to the virtual LPT wires. I am using the same PCI-LPT with xilinx cable III emulation in MAX2 starterkit as PCI Xlinx Cable III :) Antti PS Nial, I have verified the PCI part of the cores on your cyclone board it worked. the LPT stuff is just later mods not verified on your cyclone board but I am confident it should work as well.Article: 91252
Paul Hartke wrote: > Here is I handle differential clock input with BSB/EDK. Xilinx Answer > Record 19539 discusses the general strategy which uses a pcore that > converts from differential inputs to single net inside the FPGA. Have a > single ended clock in the XBD and generate the design. > Change the following in the generated MHS: > PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK > ... to: > PORT diff_sys_clk_n_pin = diff_sys_clk_n, DIR = INPUT > PORT diff_sys_clk_p_pin = diff_sys_clk_p, DIR = INPUT > ... > And add the following pcore instantiation: > BEGIN DIFF_INPUT_BUF > PARAMETER INSTANCE = DIFF_INPUT_BUF_0 > PARAMETER HW_VER = 1.00.a > PARAMETER INPUT_BUS_WIDTH = 1 > PORT DIFF_INPUT_P = diff_sys_clk_p > PORT DIFF_INPUT_N = diff_sys_clk_n > PORT SINGLE_ENDED_INPUT = dcm_clk_s > END > Then modify the UCF to duplicate the single ended LOC and constraints to > the second differential pin. I've been doing this with the XUPV2P board > for several months and haven't had any issues. > > I've already made an enchancement request to the Xilinx EDK team to > natively support this. Would anyone else find such support useful? > > Paul Thanks Paul, your comment put me on the right track. The answer record 19539 was exactly what I was looking for. Yes, I have been searching the Xilinx website. The only thing I had to add to my design was IOB_STATE=BUF after the two differential ports in the MPD-file. The design is working fine now. regards -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 91253
Project released a beta based on an enhanced TMCC, and is looking for help to bring FpgaC up to a production stable level. Home page at http://fpgac.sourceforge.net/ Project page at http://sourceforge.net/projects/fpgacArticle: 91254
air_bits@yahoo.com wrote: > Project released a beta based on an enhanced TMCC, and is looking for > help > to bring FpgaC up to a production stable level. > > Home page at http://fpgac.sourceforge.net/ > Project page at http://sourceforge.net/projects/fpgac > Why are those guys so keen on C ? Suggesting compatibility with something while having least readability ? ReneArticle: 91255
"bijoy" <pbijoy@rediffmail.com> wrote in message news:ee916ad.-1@webx.sUN8CHnE... > Hi I have a PCI core from xilinx it's ucf is done for spartan-3-200 device > > want to port the same design to spartan-3e250 device. > > have changed the pin assignment but was getting the following error during > place and route. " Phase 1.1 ERROR:Place:207 - Due to SelectIO banking > constraints, the IOBs in your design cannot be automatically placed." and > there were timing errors too, > > how can i port the design to another device, may i get some direction to > proceed in this regard > > Thanks in advance > > rgds bijoy It shouldn't be tough to get things running. If you look at the pad report generated during place & route, you'll find the banks and what the tool believes the VCCO should be for those banks. You may have an I/O from somewhere else in your design that wants to share a bank with the PCI pins but doesn't use the 3.3V. The Spartan-3E has a bunch of input-only pins that you need to keep track of since most of the PCI signals are I/O. Also, your config file has a bit that will put the "PCI_LOGIC" block back into use; the Spartan-3 dropped the feature but the Spartan-3E brought it back. You can look at FPGA Editor to see the expected placement of the I/Os relative to the PCI_LOGIC block assuming you're not using the free Xilinx tools (which don't have the FPGA Editor if I recall correctly).Article: 91256
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:r16af.26$Ge6.159@news-west.eli.net... > "bijoy" <pbijoy@rediffmail.com> wrote in message > news:ee916ad.-1@webx.sUN8CHnE... >> Hi I have a PCI core from xilinx it's ucf is done for spartan-3-200 >> device >> >> want to port the same design to spartan-3e250 device. >> >> have changed the pin assignment but was getting the following error >> during place and route. " Phase 1.1 ERROR:Place:207 - Due to SelectIO >> banking constraints, the IOBs in your design cannot be automatically >> placed." and there were timing errors too, >> >> how can i port the design to another device, may i get some direction to >> proceed in this regard >> >> Thanks in advance >> >> rgds bijoy > > It shouldn't be tough to get things running. If you look at the pad > report generated during place & route, you'll find the banks and what the > tool believes the VCCO should be for those banks. You may have an I/O > from somewhere else in your design that wants to share a bank with the PCI > pins but doesn't use the 3.3V. > > The Spartan-3E has a bunch of input-only pins that you need to keep track > of since most of the PCI signals are I/O. Also, your config file has a > bit that will put the "PCI_LOGIC" block back into use; the Spartan-3 > dropped the feature but the Spartan-3E brought it back. You can look at > FPGA Editor to see the expected placement of the I/Os relative to the > PCI_LOGIC block assuming you're not using the free Xilinx tools (which > don't have the FPGA Editor if I recall correctly). > Hi John, the the PCI_LOGIC is undocumented FPGA primitive do you happen to have addtional info about it? is useable in non xilinx design by using hard macro wrapper around it or by other means? AnttiArticle: 91257
Hi ! I need advice to build a very small firmware which will detect if a clock signal is active or not. Indeed, My FPGA (V2Pro) is connected to other devices/boards and receives a clock signal. However, this clock signal is not active at the begining and I would like to inform other devices/boards if clock signal is ready or not. My question is : How can I do to know if a signal clock is active? I thought to implement a counter driven by this clock. But this will not ensure me that signal is a clock at X MHz. May I use a DCM, and look at the LOCKED signal? All ideas are welcomed. Thank you.Article: 91258
My head is spinning... One should only use one of the edges in a clock domain, right? But if I have a memory read set up at "posedge clk". verilog ex. always @(posedge clk) ram_adress<=8'h00; Where do I do the acual reading of the result of this if I'm not allowed to use the negedge of the clock? Having another "always @(posedge)" for the reading doesn't make any sense to me. Could any kind soul explain this to me? Please. Also I've searched the forums regarding gated clocks, but couldn't find any info about it (thought I did a while ago, but it seems to be lost). How do I go about creating a clock with half of the frequency of the clock coming in to the fpga? This is how I do it now, and that's not right, is it? [code:1:faaa777181] reg px=1'b0; always @(posedge clk) begin px<=px+1'b1; end assign pixelClock=px; [/code:1:faaa777181] Also, I create more clocks in the same way, with different phases (using both the pos- and negedge). If someone could point me in the right direction I would be very pleased. Cheers! ((miceArticle: 91259
On a sunny day (2 Nov 2005 07:56:39 -0800) it happened air_bits@yahoo.com wrote in <1130946999.695784.287900@g14g2000cwa.googlegroups.com>: >Project released a beta based on an enhanced TMCC, and is looking for >help >to bring FpgaC up to a production stable level. > >Home page at http://fpgac.sourceforge.net/ >Project page at http://sourceforge.net/projects/fpgac > Interesting. here is something to think about from the libc.info from gcc C. maybe you already support these? I recently found out it is better to use these in C then 'int' and 'short', as some programs I wrote stopped working when compiled on AMD 64.... (header file structures with 'int' and 'short' and 'BYTE' ). Integers ======== The C language defines several integer data types: integer, short integer, long integer, and character, all in both signed and unsigned varieties. The GNU C compiler extends the language to contain long long integers as well. The C integer types were intended to allow code to be portable among machines with different inherent data sizes (word sizes), so each type may have different ranges on different machines. The problem with this is that a program often needs to be written for a particular range of integers, and sometimes must be written for a particular size of storage, regardless of what machine the program runs on. To address this problem, the GNU C library contains C type definitions you can use to declare integers that meet your exact needs. Because the GNU C library header files are customized to a specific machine, your program source code doesn't have to be. These `typedef's are in `stdint.h'. If you require that an integer be represented in exactly N bits, use one of the following types, with the obvious mapping to bit size and signedness: * int8_t * int16_t * int32_t * int64_t * uint8_t * uint16_t * uint32_t * uint64_t _________________________________________ Usenet Zone Free Binaries Usenet Server More than 140,000 groups Unlimited download http://www.usenetzone.com to open accountArticle: 91260
Keep away from gated clocks until you know how a clocked system works. I would recommend to start at http://www.answers.com/sequential%20logic for an introduction. -- Brian mice wrote: > My head is spinning... > One should only use one of the edges in a clock domain, right? > > But if I have a memory read set up at "posedge clk". > verilog ex. > > always @(posedge clk) > ram_adress<=8'h00; > > Where do I do the acual reading of the result of this if I'm not > allowed to use the negedge of the clock? > Having another "always @(posedge)" for the reading doesn't make any > sense to me. > Could any kind soul explain this to me? Please. > > Also I've searched the forums regarding gated clocks, but couldn't > find any info about it (thought I did a while ago, but it seems to be > lost). > How do I go about creating a clock with half of the frequency of the > clock coming in to the fpga? > This is how I do it now, and that's not right, is it? > [code:1:faaa777181] > reg px=1'b0; > always @(posedge clk) > begin > px<=px+1'b1; > end > assign pixelClock=px; > [/code:1:faaa777181] > Also, I create more clocks in the same way, with different phases > (using both the pos- and negedge). > > If someone could point me in the right direction I would be very > pleased. > > Cheers! > ((mice >Article: 91261
"mice" <miti0200@student.miun-dot-se.no-spam.invalid> wrote in message news:edudncK3N_3AafXeRVn_vQ@giganews.com... > My head is spinning... > One should only use one of the edges in a clock domain, right? > > But if I have a memory read set up at "posedge clk". > verilog ex. > > always @(posedge clk) > ram_adress<=8'h00; > > Where do I do the acual reading of the result of this if I'm not > allowed to use the negedge of the clock? > Having another "always @(posedge)" for the reading doesn't make any > sense to me. > Could any kind soul explain this to me? Please. > Dear Rodents, I sold my soul long ago, and even then it wasn't kind! However, I'll try and help. OK, it's important your clock has very little skew. This means it arrives at all the FFs at the same time. Fogs provide a special low skew feature for this purpose. Look for BUFG on Xilinx's website. Also, it's important that your FFs have short hold times. You'll find FPGAs' FFs are of this type. This means you can use the rising edge of your clock to clock all the FFs in your design, without getting race conditions and the like. The delay from one FF to the next is enough to meet the hold condition, provide your skew is low enough. If your clock is too fast, or the delays too long, you won't meet the setup condition, but that's another subject... HTH, Syms.Article: 91262
Fogs = FPGAs. Bloody spell-checker.Article: 91263
Antti, I have no documentation on the functionality of the block. I only know that it's included or excluded in the Xilinx PCI cores through the PCI .cfg file. Others have wondered about explicit functionality before - you might find something with Google. Generally, it's used to provide clock enables to the data lines combinatorially based on the PCI interface IRDY and TRDY (and other core) signals since these have the most stressed timing in PCI. - John_H "Antti Lukats" <antti@openchip.org> wrote in message news:dkart4$h85$1@online.de... > Hi John, > > the the PCI_LOGIC is undocumented FPGA primitive do you happen to have > addtional info about it? > is useable in non xilinx design by using hard macro wrapper around it or > by other means? > > AnttiArticle: 91264
Hi bijoy,
My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE
(TM) PCI compatible (replacement) PCI IP core called BDS XPCI PCI IP core.
While the current release of the BDS XPCI PCI IP core (Ver. 1.0.0)
doesn't come with a constraint file for Spartan-3 or Spartan-3E, we have
done Post Place & Route simulation of BDS XPCI PCI IP core in Spartan-3,
and has functioned properly.
Therefore, we should be able to port it to Spartan-3E relatively easily,
and we can also specifically create a UCF constraint file for the
particular Spartan-3E part you have.
The BDS XPCI32 PCI IP core commercial perpetual license version normally
costs $3,000 for domestic customers/$3,600 for foreign customers, but as
an introductory pricing, we will offer it for $2,000 for domestic
customers/$2,400 for foreign customers.
Only the first few customers will get the introductory pricing, so if
you are interested, we recommend that you contact us right away.
For other interested ordinary FPGA users, we offer BDS XPCI32
PCI IP core is available for as little as $100 for non-commercial,
non-profit, personal use, and the same 64-bit version BDS XPCI64 PCI IP
core (Includes BDS XPCI32 PCI IP core) goes for $200.
Since the pricing starts at only $100, it is ideal for HDL learners,
FPGA beginners, FPGA hobbyists, computer hardware enthusiasts, or
student graduation projects.
BDS XPCI PCI IP core comes with a PCI testbench for Verilog HDL which
allows the user to simulate the design extensively on HDL simulators
before firing up the FPGA.
ModelSim including ModelSim XE is supported by BDS XPCI PCI IP core, and
the next release of BDS XPCI PCI IP core will support a $50 Verilog HDL
simulator called Veritak by Sugawara Systems
(http://www.sugawara-systems.com) as a low cost alternative to ModelSim
XE. (Current version doesn't function properly in Veritak, but the
problem has been fixed.)
VHDL support is currently poor, but VHDL porting of reference designs
and PCI testbench should be available in a month. (Porting has been
taking a little longer than expected.)
BDS XPCI PCI IP core officially supports the following PCI boards.
- Insight Electronics Spartan-II 150 PCI (Already discontinued)
- Insight Electronics Spartan-II 200 PCI Development Kit
http://www.memec.com/uploaded/SpartanII200PCI.pdf
BDS XPCI PCI IP core "unofficially" supports the following PCI boards.
- Avnet Xilinx Spartan-3 Evaluation Kit
http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D7816%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html
http://www.em.avnet.com/ctf_shared/evk/df2df2usa/Xilinx%20Spartan-3%20Evaluation%20Kit%20-%20Brief%20022504F.pdf
- Enterpoint Broaddown2 Development Board
http://www.enterpoint.co.uk/moelbryn/broaddown2.html
So with BDS XPCI PCI IP core, almost anyone can make their own PCI
device for about $450 to $550. ($300 to $400 for the board + $100 for
BDS XPCI32 PCI IP core + $50 for Veritak.)
For commercial users who want to modify a Xilinx LogiCORE PCI or want to
convert a design that uses Xilinx LogiCORE PCI to an ASIC (FPGA to ASIC
conversion), BDS XPCI PCI IP core is also available in Verilog HDL RTL.
For more information, visit Brace Design Solutions website at
http://www.bracedesignsolutions.com.
Kevin Brace
bijoy wrote:
> Hi I have a PCI core from xilinx it's ucf is done for spartan-3-200 device
>
> want to port the same design to spartan-3e250 device.
>
> have changed the pin assignment but was getting the following error during place and route. " Phase 1.1 ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed." and there were timing errors too,
>
> how can i port the design to another device, may i get some direction to proceed in this regard
>
> Thanks in advance
>
> rgds bijoy
--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available
for as little as $100 for non-commercial, non-profit, personal use.
http://www.bracedesignsolutions.com
Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.
Article: 91265Hi seb_tech_fr > May I use a DCM, and look at the LOCKED signal? Would not help: you'd need 3 valid input clock-cycles before releasing DCM's reset (at least for Spartan3) - so knowing that you have 3 valid input clocks means, that you already know that the clock is valid. Perhaps, you could build a statemachine: periodically reset the DCM for some ns and waiting for some ms for the DCM to lock (have a look at the datasheet for worst case timing) and re-apply a reset if DCM hasn't locked yet (but you would need a reference-clock for the statemachine)... But if you have a reference-clock, you could use this clock for one counter that periodically resets a second counter driven by your input-clock: define your input clock as valid as soon (as long) as the second counter is within a specific boundary just before he sees the very next reset.. Hope, I didn't describe my idea too complex... Cheers JochenArticle: 91266
Hi John_H, We have figured out how to use PCILOGIC in our Xilinx (TM) LogiCORE (TM) PCI compatible PCI IP core called BDS XPCI PCI IP core. It basically gives very fast routing for IOB Output FF's CE (Clock Enable) input, but as many already know, it is supported by Virtex, Virtex-E, Spartan-II, and Spartan-IIE only. Xilinx dropped the support of PCILOGIC starting in Virtex-II. Kevin Brace John_H wrote: > Antti, > > I have no documentation on the functionality of the block. I only know that > it's included or excluded in the Xilinx PCI cores through the PCI .cfg file. > Others have wondered about explicit functionality before - you might find > something with Google. Generally, it's used to provide clock enables to the > data lines combinatorially based on the PCI interface IRDY and TRDY (and > other core) signals since these have the most stressed timing in PCI. > > - John_H > > > "Antti Lukats" <antti@openchip.org> wrote in message > news:dkart4$h85$1@online.de... > >>Hi John, >> >>the the PCI_LOGIC is undocumented FPGA primitive do you happen to have >>addtional info about it? >>is useable in non xilinx design by using hard macro wrapper around it or >>by other means? >> >>Antti > > > -- Brace Design Solutions Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available for as little as $100 for non-commercial, non-profit, personal use. http://www.bracedesignsolutions.com Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.Article: 91267
Memory Question:
The memory data output will be delayed by one clock cycle positive edge
from the address input.
Your code would look like
always @(posedge clk)
begin
ram_address<=8'h00;
data_register <= data_in_from_mem;
end
On the first positive clock edge you would provide the first address to
the memory. On the second positive edge you would read in the data of
the first address and simultaneously provide the second address to the
memory. Third positive edge => read in data (address2) and give out
address3 simultaneously.
--------------
Clock/2:
Xilinx specific info
If you want to divide down the clock entering your FPGA use a Digital
Clock Manager (DCM). You input your external clock to the DCM, set a
parameter to tell the DCM to divide your clock by 2 and take the
divided clock out of the CLKDV output.
You could also create clocks with different phases with the DCM. Read
up on its documents.
Gated Clocks:
Xilinx Specific
Instead of using gated clocks, you could use the CE input on the Flip
Flop. Your flip flip will still be clocked by the signal clocking the
rest of the FPGA.
regards
Kunal@Xilinx
Article: 91268
Hi bijoy,
My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE
(TM) PCI compatible (replacement) PCI IP core called BDS XPCI PCI IP core.
Assuming that your project's PCI interface is target only (no
initiator), and uses only one BAR (Base Address Register), BDS XPCI32
PCI IP core should occupy roughly 580 LUTs and 250 FFs.
That should translate roughly 290 Slices (580 / 2 = 290).
Of course, if your project uses initiator mode, the LUT consumption will
be much higher.
If the number we presented is not satisfactory, we have several
ideas to reducing the LUT count such as:
* Using multiplexer instead of internal tri-state buffers for
configuration register part of the PCI IP core
* Completely getting rid of initiator capability by removing initiator
related logic
* (I personally don't like it, but . . .) Getting rid of parity checking
capability
Obviously, the custom version will cost more money than the regular
version because we will have to customize it, but let us know if you are
interested.
For more information, visit Brace Design Solutions website at
http://www.bracedesignsolutions.com.
Kevin Brace
bijoy wrote:
> Hi My company wanted to buy PCI core(33Mhz), and it should be fitted
in spartan-3 fpga and should not take not more than 350 slices Does any
one have got any idea from where i can get this PCI core ? pls mail to
pbijoy@rediffmail.com
>
> rgds bijoy
--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available
for as little as $100 for non-commercial, non-profit, personal use.
http://www.bracedesignsolutions.com
Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.
Article: 91269On Wed, 2 Nov 2005 10:29:53 -0800, "Symon" <symon_brewer@hotmail.com> wrote: >Fogs = FPGAs. Bloody spell-checker. > An earlier incarnation of Word used to replace my former boss's name, Geoff, with "Goof." This was not only unfair but potentially career-limiting. The only thing worse than the spell checker is the grammar checker. Bob Perlman Cambrian Design WorksArticle: 91270
Antti Lukats wrote: > > the the PCI_LOGIC is undocumented FPGA primitive do you happen to have > addtional info about it? > is useable in non xilinx design by using hard macro wrapper around it or by > other means? > It is fairly easy to find out what the macro does and to use it; at least this procedure used to work;) I have not tried it with a recent version of the Xilinx tools. First of all, look at the macro in with FPGA editor. It will show the name of the module, and the name of the pins. Create a new design and instantiate just the macro, as a black box, and connect the inputs and outputs to FPGA pins. Generate the FPGA; the tools understand the macro. Run ngd2vhdl (or ngd2ver). The result should be an HDL model of the macro, which you can now use for simulation.Article: 91271
Rene Tschaggelar wrote: > Why are those guys so keen on C ? Suggesting > compatibility with something while having least > readability ? > > Rene The description at the project page pretty much says it all: "C provides an excellent alternative to VHDL/Verilog for algorithmic expression of tasks targeting FPGAs for reconfigurable computing." Project page at http://sourceforge.net/projects/fpga The object is to use FPGAs as computing engines, and less concerned about how to describe circuits in an HDL for synthesis, as most hardware designers would with VHDL or Verilog. VHDL and Verilog are the rough equivalent of programming in assemenbly language, as the implementation languages are directly expressing clocks, registers and wires which adds a tremendous design state factor and skill level in their use. Simplifed C to netlist compilers, such as FpgaC are attempting to hide most of synthesis details, to ease the design burden for hardware implementations of applications which have rich algorithmic complexity. These applications range from doing network stacks in FPGAs for wire speed performance at gigabit rates, to richly parallel algorithms such as searching which are performance limited by the serial nature of traditional CPU/Memory architectures. FPGAs in this decade are simply building blocks for high performance computing, not just a dense PLD to express hardware funtions for the logic designer.Article: 91272
mice wrote: > My head is spinning... > One should only use one of the edges in a clock domain, right? > > But if I have a memory read set up at "posedge clk". > verilog ex. > > always @(posedge clk) > ram_adress<=8'h00; > > Where do I do the acual reading of the result of this if I'm not > allowed to use the negedge of the clock? The question you're asking is, "when is the read data word available?" If it's a synchronous RAM, then your answer has to be "on the next rising edge of the clock." If it's an asynchronous RAM, then the answer is, "do a timing analysis," but the usual method is to choose a clock frequency such that the read data word is available on the next rising clock edge. > Having another "always @(posedge)" for the reading doesn't make any > sense to me. > Could any kind soul explain this to me? Please. It's actually the simplest way to do it. Of course you could read the data (from an async RAM) on the falling edge of the clock, but you have to ensure that the data are valid at that time. > Also I've searched the forums regarding gated clocks, but couldn't > find any info about it (thought I did a while ago, but it seems to be > lost). > How do I go about creating a clock with half of the frequency of the > clock coming in to the fpga? In a modern FPGA, use one of the built-in clock divider/multiplier blocks. They're free and they work. -aArticle: 91273
This is easy if you have a continuously-running clock somewhere. If you don't, you can easily detect when the clock starts for the first time after power-on ( have the clock advance a 2-bit counter that you had reset during power-on.) But if you also want to detect if the clock has diappeared later on, you need some timing element somewhere. There is no mystery, it's all very logical, and your sharp Gallic analytical mind will understand that... Cheers Peter Alfke, XilinxArticle: 91274
"Kevin Brace" <sa0les1@brac2ed3esi4gns5olut6ions.com> wrote in message news:lJ8af.3419$Lv.658@newssvr23.news.prodigy.net... <snip> > ... but as many already know, it is supported by Virtex, Virtex-E, > Spartan-II, and Spartan-IIE only. > Xilinx dropped the support of PCILOGIC starting in Virtex-II. <snip> But they brought it back in Spartan-3E !
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