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ppirrip wrote: > Hi all, > > I am trying to get into FPGA development, just wonder besides "FPGAs > are fun" (http://www.fpga4fun.com/WhatAreFPGAs.html) and opencores.org, > is there any other sites I can find good introductary materials? My > main interested is CPU cores and floating point units for DSP/control > type of applications. It's not a website, but a good book on computer architecture would probably help in the kind of stuff that you're interested in. Not FPGA-specific, but easy to apply in an FPGA. JeremyArticle: 91226
Ray Andraka skrev: > Marco wrote: > > > > >I understand... so a way to do it could be buying a analog devices ad7400 > >(isolated sigma delta modulator (1 bit out)) and building the digital filter > >into the fpga to obtain 16 bit output data. > > > >What do you think about it? > > > > > > > > > That works just fine, and it can be done in a small FPGA with careful > design. I did an 8 channel one in an XC2S15 using external DS modulators. > I wonder what the intended application is for the ad7400, why the isolation, why only the DS modulator wouldn't most people get a whole ADC when they have to add a chip anyway? Why did you use it instead of a full ADC, Ray? -LasseArticle: 91227
Yeah it does. But i may have to try this 20-30times each time I wish to turn it on. -- ---------------------------------------------- Posted with NewsLeecher v3.0 Final * Binary Usenet Leeching Made Easy * http://www.newsleecher.com/?usenet ----------------------------------------------Article: 91228
Ray Andraka wrote: > Gee, I'm just hoping they didn't break anything. It took 4 service > packs to get 7.1 to a usable state. Obviously I'd hope so too. Correctness is more important to me than new features. It's a shame that this isn't true of mainstream software purchasers (or at least that the software vendors don't think it is).Article: 91229
Mike Treseler wrote: > Yes. Your example has a width mismatch. Those above do not. Try it > and see. Not quite sure what point you're making here Mike?!? Anyway, to kill the thread, let's agree to disagree. I come from a software background, which might explain why I'm lazy and spoilt with feature-rich languages and powerful pre-processors. ;) Regards, MarkArticle: 91230
Marco wrote: > "John Monro" <johnmonro@optusnet.com.au> wrote in message > news:43671713$0$25854$afc38c87@news.optusnet.com.au... > >>Marco wrote: >> >>>>Marco, >>>>I am afraid not. While the input circuit is differential, the rest of a >>>>LVDS buffer is optimised for digital performance, and not for the >>>>characteristics we require in a good operational amplifier. >>>>A LVDS buffer would make a worse integrator than the cheapest op. amp. so >>>>why bother? >>>> >>>>Regards, >>>>John >>> >>> >>>Hi John, >>>sorry for my terrible scheme. >>> >>>Please watch the picture at the link: >>> >>>http://www.maxim-ic.com/images/appnotes/1870/A237Fig04.gif >>> >>>That should be more clear. >>> >>>I thought that I could replace the 1-bit dac using a LVCMOS25 out pin >>>(without dac because it is only 1 bit) and connecting it to the negative >>>input of LVDS25. >>> >>>What do you think about it? >>> >>>Is it possible? >>> >>>Many Thanks >>>Marco >> >>Marco, >>Unfortunately, the DAC output voltage needs to be very well defined and >>noise-free, even though it is derived from a one-bit value, and no digital >>output is able to achieve this. >> >>I don't think there is any chance of realising CD-quality (16-bit) audio >>by trying to make a digital chip perform any analog functions at all. >>Digital noise on the ground and supply lines for example make it a >>hopeless job at the quality level you want. >> >>If it is essential to use a single chip, you could investigate the Lattice >>Semiconductor programmable combined analog/digital chips. >> >> >>Regards, >>John > > > > I understand... so a way to do it could be buying a analog devices ad7400 > (isolated sigma delta modulator (1 bit out)) and building the digital filter > into the fpga to obtain 16 bit output data. > > What do you think about it? > > Marko, I see that other contributors have already answered your question, and I agree with their comments. My guess is that you are undertaking this as a tecnhnical challenge. and are not expecting any particular economic or performance benefits. Good luck with the project. Regards, John MonroArticle: 91231
Hi,
I am trying to use a bidirectional bus, declared as inout in my vhdl
code. When running on FPGA eveything works, except that bus. The bus is
dead all the time and can not be read.
I have tried changing that port to in only, and eveything works fine.
I understand that for an inout port, tristate needs to declared. Still,
that doesn't help.
If anyone could please help out, it'd be much appreciated.
Thank you for your attention.
below is my code
--------------------------------------------------------------------------------
-- SubModule USB
-- Created 16/10/2005 6:51:41 PM
--------------------------------------------------------------------------------
Library IEEE;
Use IEEE.Std_Logic_1164.all;
use ieee.std_logic_unsigned.all;
entity USB is
port (
PORTB : inout std_logic_vector(7 downto 0);
CLK : in std_logic;
RST : in std_logic;
CS : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
A : in std_logic_vector(15 downto 0);
WR : in std_logic;
RD : in std_logic;
IFCLK : in std_logic;
FIFOADR : out std_logic_vector(1 downto 0);
FLAGA : in std_logic;
FLAGB : in std_logic;
FLAGC : in std_logic;
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
PKTEND : out std_logic;
RESET : out std_logic;
WAIT_ST : out std_logic);
end USB;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of USB is
signal SLRD_buffer : std_logic;
signal SLWR_buffer : std_logic;
signal OE :std_logic;
begin
FIFOADR( 1 downto 0) <=b"10" when ((WR = '1' and CS = '1') and A(1
downto 0) = b"11") else b"00";
SLOE<='1' when ((RD='1' and CS = '1') and A(1 downto 0) = b"01")else
'0';
SLRD<= '1' when (CS='1' and RD='1' and A(1 downto 0) = b"01") else '0';
OE<='1' when (WR='1' and CS = '1') else '0';
PORTB<=DI when (OE='1') else "ZZZZZZZZ";
DO<= x"01" when (A(1 downto 0)=b"00" and FLAGA='1' ) else
--EP2empty
x"00" when (A(1 downto 0)=b"00" and FLAGA='0' ) else --EP2 not
empty
x"01" when (A(1 downto 0)=b"10" and FLAGB='1' ) else --EP6 full
x"00" when (A(1 downto 0)=b"10" and FLAGB='0' ) else --EP6 not
full
PORTB ;
RESET<='1';
PKTEND <='0';
SLWR<='0';
end behaviour;
Article: 91232I. Ulises Hernandez wrote: > Hello guys, > > Has anyone used the DXP and DXN pins in Virtex-4 yet? If so and if the > results were all right, what external sensor did you use...? > > Thanks in advance, I've used it on a number of V2 and V2P FPGAs. All have worked, although there was a board at Agilent that (presumably) had a noise issue and would read about 20 degrees high. Moral: follow the layout recommendations in the monitor chip data sheet. I prefer to use something like the LM87, as this allows me to monitor the supply rails as well. Regards, AllanArticle: 91233
On 1 Nov 2005 18:17:45 -0800, liaobojie@gmail.com wrote:
(..)
>--------------------------------------------------------------------------------
>-- SubModule USB
>-- Created 16/10/2005 6:51:41 PM
>--------------------------------------------------------------------------------
>Library IEEE;
>Use IEEE.Std_Logic_1164.all;
>use ieee.std_logic_unsigned.all;
add these two lines:
library UNISIM;
use UNISIM.VComponents.all;
>
>entity USB is
> port (
> PORTB : inout std_logic_vector(7 downto 0);
> CLK : in std_logic;
> RST : in std_logic;
> CS : in std_logic;
> DI : in std_logic_vector(7 downto 0);
> DO : out std_logic_vector(7 downto 0);
> A : in std_logic_vector(15 downto 0);
> WR : in std_logic;
> RD : in std_logic;
> IFCLK : in std_logic;
> FIFOADR : out std_logic_vector(1 downto 0);
> FLAGA : in std_logic;
> FLAGB : in std_logic;
> FLAGC : in std_logic;
> SLOE : out std_logic;
> SLRD : out std_logic;
> SLWR : out std_logic;
> PKTEND : out std_logic;
> RESET : out std_logic;
> WAIT_ST : out std_logic);
>end USB;
>--------------------------------------------------------------------------------
>
>--------------------------------------------------------------------------------
>architecture behaviour of USB is
>
>signal SLRD_buffer : std_logic;
>signal SLWR_buffer : std_logic;
>signal OE :std_logic;
>
add this line
signal portb_in,portb_out:std_logic_vector(7 downto 0);
>
>
>begin
>
>FIFOADR( 1 downto 0) <=b"10" when ((WR = '1' and CS = '1') and A(1
>downto 0) = b"11") else b"00";
>SLOE<='1' when ((RD='1' and CS = '1') and A(1 downto 0) = b"01")else
>'0';
>SLRD<= '1' when (CS='1' and RD='1' and A(1 downto 0) = b"01") else '0';
>
>OE<='1' when (WR='1' and CS = '1') else '0';
change this line:
>PORTB<=DI when (OE='1') else "ZZZZZZZZ";
to this other:
portbio:for i in portb'range generate
portbio_bit:IOBUF(I=>portb_out(i),O=>portb_in(i),T=>OE,IO=>PORTB(i));
end generate;
>
>DO<= x"01" when (A(1 downto 0)=b"00" and FLAGA='1' ) else
>--EP2empty
> x"00" when (A(1 downto 0)=b"00" and FLAGA='0' ) else --EP2 not
>empty
> x"01" when (A(1 downto 0)=b"10" and FLAGB='1' ) else --EP6 full
> x"00" when (A(1 downto 0)=b"10" and FLAGB='0' ) else --EP6 not
>full
change this line:
> PORTB ;
to
portb_in;
>RESET<='1';
>PKTEND <='0';
>
>SLWR<='0';
>
>end behaviour;
That should do it. Sometimes you must instantiate primitives if you
want to control what you are doing.
Article: 91234The problem is most likely related to Xilinx Solution Record 22179 (see http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=22179). We are working on updating the CF card with demos that have the tieoff value set correctly. For your own designs follow the Solution Record to use the proper settings and you should not see any problems when powering the board on. - Peter kdfake@spam.com wrote: > Yeah it does. But i may have to try this 20-30times each time I wish > to turn it on.Article: 91235
Are you using Reset for PLL ? Rgds Andr=E9Article: 91236
Thanks guys, I'll use it. Regards, Ulises <allanherriman@hotmail.com> wrote in message news:1130899910.307957.266410@f14g2000cwb.googlegroups.com... > I. Ulises Hernandez wrote: >> Hello guys, >> >> Has anyone used the DXP and DXN pins in Virtex-4 yet? If so and if the >> results were all right, what external sensor did you use...? >> >> Thanks in advance, > > I've used it on a number of V2 and V2P FPGAs. All have worked, > although there was a board at Agilent that (presumably) had a noise > issue and would read about 20 degrees high. > Moral: follow the layout recommendations in the monitor chip data > sheet. > > I prefer to use something like the LM87, as this allows me to monitor > the supply rails as well. > > Regards, > Allan >Article: 91237
Hello, I developed a wee Gigabit MAC but with quite a different setup, Virtex 2 Pro (with my MAC + Internal MGT - 16 bit wide @ 62.5MHz) + Copper SFPs (with embedded Marvell 88E1111 in SGMII mode) <=> PC I did use Ethereal, and noticed that crc errored packets were filtered out, not sure if it was the SFP, the PHY in the PC or the PC driver, I'm positive that packets were not getting to Ethereal at all. I also noticed that packets smaller than 64 bytes were also filtered out and I am pretty sure it was the Driver in my PC. For testing I used a ping frame... --=============================================-- --IP DA (192.168.0.85 : c0.a8.00.55) --IP SA (192.168.0.33 : c0.a8.00.21) --Header Length & IPv4 = x"4500" --IP Datagram = x"0800" --SA = 12.34.56.78.9a.bc (it doesn't really matter) --DA = 00.0d.88.b5.88.71 (change it to yours, it doesn't really matter in promiscous mode) --=============================================-- constant C_GBE_DATA : word32_array(18 downto 0) := ( X"68697071", X"64656667", X"77616263", X"73747576", X"6f707172", X"6b6c6d6e", X"6768696a", X"63646566", X"04006162", X"485c0100", X"00550800", X"0021c0a8", X"96b3c0a8", X"00002001", X"003c8247", X"08004500", X"56789abc", X"88711234", X"000d88b5" ); Bytes go out like: 00 - 0d - d8 - b5 - 88 - 71 ... FCS for the packet above => X"257eaf61" On thing I recommend is using loopback if your PHY supports it, and also the internal CRC if the PHY provides one (just for testing) before trying to send packets to your PC. Regards, -- Ignacio Ulises Hernandez " I'm not normally a praying man, but if you're up there, please save me, Superman!" - Homer Simpson ;O) "ashwin" <achiluka@gmail.com> wrote in message news:1130865877.899697.324060@g44g2000cwa.googlegroups.com... > Hello everyone, > > I am sending an ethernet packet(64 bytes) from the fpga to the PC > in order to test the ETHERNET PHY chip onboard. > The interface from the fpga to the ethernet PHY for the data is 4 > bits. > > My PC mac address is 00-01-80-3F-6C-E6 > > a)So should i send the LSBs first like > in this order, 6,E,C,6,F,3,0,8,1,0,0,0 or the MSBs first > > > b) I have installed ethereal software on my PC and i am unable to > detect the ethernet packet in it. > 1) I am pretty sure my CRC is wrong for whatever data i have, so > can ethereal still detect even when crc is wrong? > > 2)i used the scope , and i am able to see some data going from > fpga to the ethernet PHY. But the nothing gets detected in the PC. What > could be the reason? > > One of the member in this group recommended not to see the data > coming out of the ETHERNET phy , since its at 125 mhz and its not > being detect correctly using a scope. > > > 3)Can anyone compute the crc check for whole ethernet packet for which > my destination addres is as above? Data doesnt matter,it can be any > value.?Source address also doesnt matter, since it is fpga mac address. > > 4) Can anyone guide me on hardware implementation of crc using > vhdl >Article: 91238
Hi I have a PCI core from xilinx it's ucf is done for spartan-3-200 device want to port the same design to spartan-3e250 device. have changed the pin assignment but was getting the following error during place and route. " Phase 1.1 ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed." and there were timing errors too, how can i port the design to another device, may i get some direction to proceed in this regard Thanks in advance rgds bijoyArticle: 91239
When you buy the Core, you normally get a user Id and a passwd to access the private section in Xilinx website so that you can change the UCF online, I think? You can also contact the guy who sold you the core in the first place. Regards, -- Ignacio Ulises Hernandez " I'm not normally a praying man, but if you're up there, please save me, Superman!" - Homer Simpson ;O) "bijoy" <pbijoy@rediffmail.com> wrote in message news:ee916ad.-1@webx.sUN8CHnE... > Hi I have a PCI core from xilinx it's ucf is done for spartan-3-200 device > > want to port the same design to spartan-3e250 device. > > have changed the pin assignment but was getting the following error during > place and route. " Phase 1.1 ERROR:Place:207 - Due to SelectIO banking > constraints, the IOBs in your design cannot be automatically placed." and > there were timing errors too, > > how can i port the design to another device, may i get some direction to > proceed in this regard > > Thanks in advance > > rgds bijoyArticle: 91240
Hi First of all i would like to Thank You for your immediate response. The problem i am facing is different, we have got a PCI core from xilinx for demo purpose with a ucf and for spartan-3 200 device. Now we want to try the same in the spartan-3e-250 device due to some cost consideration, but pci core ucf generator is not available now with xilinx for this particular family, spartan-3e is relattiviely new and there is no ucf file made for porting PCI core to this device, so i have to manually do the ucf generation from the ucf given for the spartan-3-200 device. This is my real problem, i am trying all my option in my hand, but i am not familiar with the ucf files and especially for designs of pci core and its internal signals and the timing requuirements are not available to me. regards bijoyArticle: 91241
Hi all, I'm doing a project on a Virtex-2P-40. The FPGA is fed with a differential clock pair and I am not quite sure how to tell EDK that this is the case. I have tried to use a small custom made core to connect the two clock inputs (pins H18 and J18) to an IBUFGDS primitive, but that is not understood by the synthesis which connects the inputs to two different BUFGP primitives prior to my small IBUF-core. In my oppinion the clock should be connected to a IBUFGDS and the output from the buffer should be connected to the DCM. I'm feeling clueless, and would sure appreciate any input on this matter leading me in the right direction. Regards -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 91242
"bijoy" <pbijoy@rediffmail.com> schrieb im Newsbeitrag news:ee916ad.1@webx.sUN8CHnE... > Hi First of all i would like to Thank You for your immediate response. > > The problem i am facing is different, we have got a PCI core from xilinx for demo purpose with a ucf and for spartan-3 200 device. > > Now we want to try the same in the spartan-3e-250 device due to some cost consideration, but pci core ucf generator is not available now with xilinx for this particular family, spartan-3e is relattiviely new and there is no ucf file made for porting PCI core to this device, so i have to manually do the ucf generation from the ucf given for the spartan-3-200 device. > > This is my real problem, i am trying all my option in my hand, but i am not familiar with the ucf files and especially for designs of pci core and its internal signals and the timing requuirements are not available to me. > > regards bijoy http://cgi.ebay.de/ws/eBayISAPI.dll?ViewItem&item=5825643507 that e-book includes ALL instructions how to get an PCI design up and running. the PCI core used there is VERY simple and usually works out of box, you just assign PCI IO pins and constraint on PCI clock nothing else. I have tested the PCI core on spartan 3, virtex2, cyclone and max2 boards. its not a solution for your problem, but its an EASY way to test an existing PCI FPGA board. AnttiArticle: 91243
"Johan Bernspång" <xjohbex@xfoix.se> schrieb im Newsbeitrag news:dka7nj$l7t$1@mercur.foi.se... > Hi all, > > I'm doing a project on a Virtex-2P-40. The FPGA is fed with a > differential clock pair and I am not quite sure how to tell EDK that > this is the case. I have tried to use a small custom made core to > connect the two clock inputs (pins H18 and J18) to an IBUFGDS primitive, > but that is not understood by the synthesis which connects the inputs to > two different BUFGP primitives prior to my small IBUF-core. In my > oppinion the clock should be connected to a IBUFGDS and the output from > the buffer should be connected to the DCM. > > I'm feeling clueless, and would sure appreciate any input on this matter > leading me in the right direction. > > Regards > -- > ----------------------------------------------- > Johan Bernspång, xjohbex@xfoix.se > Research engineer if the clock goes to DCM you need to make sure the DCM wrapper does not include a bufg in the clock input, then you just create a user logic with lvds clock buf. thats it. must work. anttiArticle: 91244
On Wed, 02 Nov 2005 12:25:40 +0100, Johan Bernspång <xjohbex@xfoix.se> wrote: >Hi all, > >I'm doing a project on a Virtex-2P-40. The FPGA is fed with a >differential clock pair and I am not quite sure how to tell EDK that >this is the case. I have tried to use a small custom made core to >connect the two clock inputs (pins H18 and J18) to an IBUFGDS primitive, >but that is not understood by the synthesis which connects the inputs to >two different BUFGP primitives prior to my small IBUF-core. In my >oppinion the clock should be connected to a IBUFGDS and the output from >the buffer should be connected to the DCM. > >I'm feeling clueless, and would sure appreciate any input on this matter >leading me in the right direction. > >Regards I think you should change the synthesis option /Xilinx specific options/add I/O buffers to falseArticle: 91245
Johan Bernspång wrote: > Hi all, > > I'm doing a project on a Virtex-2P-40. The FPGA is fed with a > differential clock pair and I am not quite sure how to tell EDK that > this is the case. I have tried to use a small custom made core to > connect the two clock inputs (pins H18 and J18) to an IBUFGDS primitive, > but that is not understood by the synthesis which connects the inputs to > two different BUFGP primitives prior to my small IBUF-core. In my > oppinion the clock should be connected to a IBUFGDS and the output from > the buffer should be connected to the DCM. > > I'm feeling clueless, and would sure appreciate any input on this matter > leading me in the right direction. > > Regards I have had the same problem! Seems that there should be a way in the User Constraints file to specify this! -EliArticle: 91246
I have problems getting ChipScope to work with the Xilinx ML401 kit. I have been trying to find a solution at "Xilinx answer records" and the closest thing to a solution I came was the record 20060. This solution helps propably if you are designing a processor system, but right now I am testing some vhdl designs with ChipScope and it does not seam to help me there. This problem is actually a bit urgent for me to overcome, so thanks to any input that brings me closer to a solution. I use ISE version 7.1.04i and ChipScope version 7.1i Raymond BakkenArticle: 91247
It works. I installed ChipScope SP 7.1.04i and the problem seams to be solved there RaymondArticle: 91248
Antti Lukats wrote: > "Johan Bernspång" <xjohbex@xfoix.se> schrieb im Newsbeitrag > news:dka7nj$l7t$1@mercur.foi.se... > >>Hi all, >> >>I'm doing a project on a Virtex-2P-40. The FPGA is fed with a >>differential clock pair and I am not quite sure how to tell EDK that >>this is the case. I have tried to use a small custom made core to >>connect the two clock inputs (pins H18 and J18) to an IBUFGDS primitive, >>but that is not understood by the synthesis which connects the inputs to >>two different BUFGP primitives prior to my small IBUF-core. In my >>oppinion the clock should be connected to a IBUFGDS and the output from >>the buffer should be connected to the DCM. >> >>I'm feeling clueless, and would sure appreciate any input on this matter >>leading me in the right direction. >> >>Regards >>-- >>----------------------------------------------- >>Johan Bernspång, xjohbex@xfoix.se >>Research engineer > > > if the clock goes to DCM you need to make sure the DCM wrapper does not > include a bufg in the clock input, then you just create a user logic with > lvds clock buf. thats it. must work. > > antti > > > > Well, I thought so too. (No additional bufg is included in the DCM wrapper). But EDK is adding buffers during the synthesis on all global I/Os regardless on what is defined in the UCF file. (Zara: I can't find where in EDK I set the I/O-buffer option you mentioned, and I still want all other global I/Os to have buffers). Examing the system.vhd file gives the following information. If I define the ports refclk_p and refclk_n as clock signals in the MHS file (SIGIS = CLK) the synthesis is connecting the ports to BUFGPs before connecting the signals to my IBUFGDS-core. When the SIGIS = CLK is omitted the ports are connected to ordinary IBUFs. In ISE this issue isn't even an issue, there should be a way to work this out in EDK as well. The Xilinx dev boards ML40x have connectors for external differential clock inputs...it must work somehow. Regards -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 91249
Here is I handle differential clock input with BSB/EDK. Xilinx Answer Record 19539 discusses the general strategy which uses a pcore that converts from differential inputs to single net inside the FPGA. Have a single ended clock in the XBD and generate the design. Change the following in the generated MHS: PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK ... to: PORT diff_sys_clk_n_pin = diff_sys_clk_n, DIR = INPUT PORT diff_sys_clk_p_pin = diff_sys_clk_p, DIR = INPUT ... And add the following pcore instantiation: BEGIN DIFF_INPUT_BUF PARAMETER INSTANCE = DIFF_INPUT_BUF_0 PARAMETER HW_VER = 1.00.a PARAMETER INPUT_BUS_WIDTH = 1 PORT DIFF_INPUT_P = diff_sys_clk_p PORT DIFF_INPUT_N = diff_sys_clk_n PORT SINGLE_ENDED_INPUT = dcm_clk_s END Then modify the UCF to duplicate the single ended LOC and constraints to the second differential pin. I've been doing this with the XUPV2P board for several months and haven't had any issues. I've already made an enchancement request to the Xilinx EDK team to natively support this. Would anyone else find such support useful? Paul Johan Bernspång wrote: > > Hi all, > > I'm doing a project on a Virtex-2P-40. The FPGA is fed with a > differential clock pair and I am not quite sure how to tell EDK that > this is the case. I have tried to use a small custom made core to > connect the two clock inputs (pins H18 and J18) to an IBUFGDS primitive, > but that is not understood by the synthesis which connects the inputs to > two different BUFGP primitives prior to my small IBUF-core. In my > oppinion the clock should be connected to a IBUFGDS and the output from > the buffer should be connected to the DCM. > > I'm feeling clueless, and would sure appreciate any input on this matter > leading me in the right direction. > > Regards > -- > ----------------------------------------------- > Johan Bernspång, xjohbex@xfoix.se > Research engineer > > Swedish Defence Research Agency - FOI > Division of Command & Control Systems > Department of Electronic Warfare Systems > > www.foi.se > > Please remove the x's in the email address if > replying to me personally. > -----------------------------------------------
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