Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
no, i've connected them according to what you've mentioned. But translation error is still there. CMOSArticle: 90901
If you want to suppress the warnings use 'EDIT > MESSAGE FILTERS' in ISE KunalArticle: 90902
Depending on the package, there are either 240 or 320 available I/O, and (almost) all of them have their own ISERDES. Peter Alfke, Xilinx ApplicationsArticle: 90903
Gert Baars wrote: >Fine, thanks for reply. I am aware that VHDL is a matter of specifying. >If you can recommend documents or books, please don't hesitate. "Essential VHDL" http://www.vahana.com/vhdl.htm -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 90904
you are an idiot ! No one in their right mind would design a processor like that with an implementation goal of putting it in a FPGA. Simon "raph" <raphael.ponsard@ac-grenoble.fr> wrote in message news:435ca17a$0$20868$636a55ce@news.free.fr... > Hi Folks, > > For educational purpose (Von Neumann demo), I am looking for a System On > Chip Processor : > - very simple > - gate level design (no VHDL, only gates AND,NAND, and low level boxes > as shifter, ...) > - running system (spartan 3 or other low cost xilinx or altera demo board) > > regards > RaphArticle: 90905
raph wrote: > Hi Folks, > > For educational purpose (Von Neumann demo), I am looking for a System On > Chip Processor : > - very simple > - gate level design (no VHDL, only gates AND,NAND, and low level boxes > as shifter, ...) > - running system (spartan 3 or other low cost xilinx or altera demo board) Well, no AND or NAND but perhaps close enough for government work. http://klabs.org/history/ech/agc_schematics/ -- rk, Just an OldEngineer "These are highly complicated pieces of equipment almost as complicated as living organisms. In some cases, they've been designed by other computers. We don't know exactly how they work." -- Scientist in Michael Crichton's 1973 movie, WestworldArticle: 90906
That seems like a fair price for 50.. "Dom Gilligan" <dg2036@hotmail.com> wrote in message news:huppl1pnlitvu8evdl8i9ql7d2bn7lp5js@4ax.com... > Can anyone give me a general idea on pricing and availability for low > volumes (~50) of the XC3S4000-5FG900? The only online price I can find > is $242 from Avnet, for the -4 part (no -5), no stock, 8 weeks > leadtime. > > Thanks - > > DomArticle: 90907
Kolja Sulimma wrote:
Mike Lewis wrote: >Lionel Damez wrote: > > Is it possible to do that with
the EDK interface, or do I have to export > > my design to Projet Navigator(ISE)?
> The tool is telling you that 16 won't fit ... I doubt there is much
you can > do other than reduce the number of instances of the processor.
> > Mike
- The logic for 16 microblazes fits. - A single microblaze is routable.
- The communication between the prozessors is systolic.
From that information I would say that floorplanning is very likely to
yield a routable design. This means that you tell the placer beforehand
were in which reagion of the chip it should put each processor and the
corresponding memory.
You can not do that from EDK AFAIK.
Kolja Sulimma
Thank you very much!
One other question :
The EDK tool generates a system with a flat hierarchy. If I add some constraints like closed area groups in the "system.ucf" in order to separate the processor subsystems, will that help for successful place and route?
Lionel Damez
Article: 90908I know this isn't exactly comp.arch.cpld... does anyone know of a COTS solution for programming a (Xilinx) CPLD without using PC + Windows + Impact etc etc. (a stand alone chunk of hardware with a way for me to give it a set of bit files and a Program button would be nice) I want to load one bit-file into a device to run a test, then once the test is finished load a second bit-file - but i'm investigating a stand alone solution not using a PC + Cable + Software etc etc. Any pointers are welcome. Thanks! Ben Benjamin TODD ABCOIN CERN - European Organisation for Nuclear Research, Accelerator and Beam Controls - Infrastructure division. Building 864:1A01, Meyrin Geneva 23, Switzerland, CH-1211.Article: 90909
I have recoded a xilinx reference of UART and tested it in VIRTEX II.The reference is in VHDL.And It can reach 115K when communication with PC. If you interested it, you can contact me at zhang.young@gmail.com.Article: 90910
"Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> schrieb im Newsbeitrag news:djkmeg$mdo$1@sunnews.cern.ch... > I know this isn't exactly comp.arch.cpld... > > does anyone know of a COTS solution for programming a (Xilinx) CPLD without > using PC + Windows + Impact etc etc. (a stand alone chunk of hardware with a > way for me to give it a set of bit files and a Program button would be nice) > > I want to load one bit-file into a device to run a test, then once the test > is finished load a second bit-file - but i'm investigating a stand alone > solution not using a PC + Cable + Software etc etc. > > Any pointers are welcome. > Thanks! > Ben > Benjamin TODD Hi Ben, as usually YES/NO. :) 1) if you badly want then you can use SystemACE to program PLDs in the way you described. its not very reasonable but its sure is possible. 2) there is no direct COTS solution I think. you can use any small MCU to re-configure the PLDs solutions for that exist. reloading an PLD with test conf each time at power up isnt very nice thing todo in generic. sure it depend on the PLD in use. I think with machXO you have an option to load the flash or the PLD (what is actually ram based) anttiArticle: 90911
Hi, we have a "Video Monitor On-Screen Display" device from Motorola Semiconductors. (MC141581P2) The problem is that this device has been discontinued. Instead of looking for a new device we are thinking about implementing our own OSD device in a FPGA. Where do you think could arise problems when using a FPGA ? I think the main drawback is that FPGAs are not able to generate stable clocks out off a internal PLL when the input clock of the PLL changes dynamically. Is that correct ? Or do such PLLs exist in FPGAs ? Thank you for your opinion. Rgds Andr=E9Article: 90912
dear all
I am trying to measuring power consumpsion with VCD and NCD
information, in Xpower 6.3.03i, Appication version G.35, Virtex II pro.
And following report appeared. There seems to be something incorrect.
Especially logic power is '0'. Does anyone have this experience?
Thankyou again.
------------------------------------------------------
WARNING:Power:410 - No thermal characteristics available for this
device / package combination.
WARNING:Power:163 - PowerVcd_Dump: Declaration of variable
'counter_tb.u_counter.en1' ignored, identifier code '!' is already in
use by 'counter_tb.t_en'!
WARNING:Power:164 - PowerVcd_Dump: Subsequent redeclarations of this or
other identifier codes will be ignored without comment.
WARNING:PowerEstimator:127 - Power estimate is considered inaccurate.
To see details, generate an advanced report with the "-v -a" switch.
WARNING:Power:762 - Only 87% of the design signals have been set.
WARNING:Power:763 - Only 87% of the design signals toggle.
Power summary: I(mA) P(mW)
----------------------------------------------------------------
Total estimated power consumption: 823
---
Vccint 1.50V: 253 379
Vccaux 2.50V: 167 418
Vcco25 2.50V: 11 27
---
Clocks: 2 3
Inputs: 1 1
Logic: 0 0
Outputs:
Vcco25 9 22
Signals: 0 1
---
Quiescent Vccint 1.50V: 250 375
Quiescent Vccaux 2.50V: 167 418
Quiescent Vcco25 2.50V: 2 5
Thermal summary:
----------------------------------------------------------------
Estimated junction temperature: 25C
Ambient temp: 25C
Case temp: 25C
Theta J-A: 0C/W
Article: 90913"JJ" <johnjakson@gmail.com> writes: > Hi Martin > <snip> > The latency of 20ns can be managed by MTA processor design, but the > ability to issue every 2.5ns (3.3ns in FPGA with 6 clocks latency) is > the charm. 40ns every 40ns just isn't the same. Lots of issue rate > means lots of slower PEs can share it. > Yes, I can see that would be different - I'll go and read up on RLDRAM now :-) > If conventional SDRAM can overlap 2 banks during the RAS time, that > would be news to me. > No, I don't think it can :-( Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 90914
On 25 Oct 2005 01:58:51 -0700, ALuPin@web.de wrote: >Hi, > >we have a "Video Monitor On-Screen Display" device from >Motorola Semiconductors. (MC141581P2) >The problem is that this device has been discontinued. >Instead of looking for a new device we are thinking about >implementing our own OSD device in a FPGA. > >Where do you think could arise problems when using a FPGA ? > >I think the main drawback is that FPGAs are not able >to generate stable clocks out off a internal PLL when the input >clock of the PLL changes dynamically. Is that correct ? >Or do such PLLs exist in FPGAs ? > > >Thank you for your opinion. > >Rgds >André We use FPGA to generate OSD. The only special requirement is to use an external good quality VCO.Article: 90915
Ah, before I investigate the system ACE are you sure it can be hacked to work for PLDs? http://www.xilinx.com/isp/systemace/faq001_system-ace_1_1.pdf Page 2... I also read the uP ideas... But it seams like a lot of work on my own... http://www.xilinx.com/bvdocs/appnotes/xapp058.pdf I was hoping someone had commercialised this.. Hmm, anyways, thanks for your input Antti. Ben "Antti Lukats" <antti@openchip.org> wrote in message news:djkrvn$7lc$01$1@news.t-online.com... > "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> > schrieb im Newsbeitrag news:djkmeg$mdo$1@sunnews.cern.ch... >> I know this isn't exactly comp.arch.cpld... >> >> does anyone know of a COTS solution for programming a (Xilinx) CPLD > without >> using PC + Windows + Impact etc etc. (a stand alone chunk of hardware >> with > a >> way for me to give it a set of bit files and a Program button would be > nice) >> >> I want to load one bit-file into a device to run a test, then once the > test >> is finished load a second bit-file - but i'm investigating a stand alone >> solution not using a PC + Cable + Software etc etc. >> >> Any pointers are welcome. >> Thanks! >> Ben >> Benjamin TODD > > Hi Ben, > > as usually YES/NO. :) > > 1) if you badly want then you can use SystemACE to program PLDs in the way > you described. its not very reasonable but its sure is possible. > > 2) there is no direct COTS solution I think. you can use any small MCU to > re-configure the PLDs solutions for that exist. > > reloading an PLD with test conf each time at power up isnt very nice thing > todo in generic. sure it depend on the PLD in use. > > I think with machXO you have an option to load the flash or the PLD (what > is > actually ram based) > > antti > > > > > > > > > > > > > > > >Article: 90916
Hi Zara, what kind of OSD have you implemented ? Are there general papers you can recommend ? Rgds Andr=E9Article: 90917
On 25 Oct 2005 02:56:35 -0700, ALuPin@web.de wrote: >Hi Zara, > >what kind of OSD have you implemented ? > >Are there general papers you can recommend ? > >Rgds >André Our OSD works on SDI digital video. You may find in xilinx website a lot of applications on SDI processing. Maintining enough mental distance, almost all of them are applicable to lots of video designs (not only OSD). regards ZaraArticle: 90918
Hi, That's very weird that you're getting 0 logic power. You should contact the hotline. Brendan (Xilinx) "Pasacco" <pasacco@gmail.com> wrote in message news:1130231038.657928.252630@g47g2000cwa.googlegroups.com... > dear all > > I am trying to measuring power consumpsion with VCD and NCD > information, in Xpower 6.3.03i, Appication version G.35, Virtex II pro. > And following report appeared. There seems to be something incorrect. > Especially logic power is '0'. Does anyone have this experience? > Thankyou again. > > > ------------------------------------------------------ > WARNING:Power:410 - No thermal characteristics available for this > device / package combination. > WARNING:Power:163 - PowerVcd_Dump: Declaration of variable > 'counter_tb.u_counter.en1' ignored, identifier code '!' is already in > use by 'counter_tb.t_en'! > WARNING:Power:164 - PowerVcd_Dump: Subsequent redeclarations of this or > other identifier codes will be ignored without comment. > WARNING:PowerEstimator:127 - Power estimate is considered inaccurate. > To see details, generate an advanced report with the "-v -a" switch. > WARNING:Power:762 - Only 87% of the design signals have been set. > WARNING:Power:763 - Only 87% of the design signals toggle. > > Power summary: I(mA) P(mW) > ---------------------------------------------------------------- > Total estimated power consumption: 823 > --- > Vccint 1.50V: 253 379 > Vccaux 2.50V: 167 418 > Vcco25 2.50V: 11 27 > --- > Clocks: 2 3 > Inputs: 1 1 > Logic: 0 0 > Outputs: > Vcco25 9 22 > Signals: 0 1 > --- > Quiescent Vccint 1.50V: 250 375 > Quiescent Vccaux 2.50V: 167 418 > Quiescent Vcco25 2.50V: 2 5 > > Thermal summary: > ---------------------------------------------------------------- > Estimated junction temperature: 25C > Ambient temp: 25C > Case temp: 25C > Theta J-A: 0C/W >Article: 90919
"Zara" <nospam.yozara@terra.es> wrote in message news:8l2sl1hagkl4hp6o8n44jhtlnae3pqhut4@4ax.com... > Our OSD works on SDI digital video. I can imagine wanting to sync to an ordinary video camera as used in security applications. I guess that would be slightly harder. A long time ago I saw an article where a 6845 was used as part of a PLL to sync video frame addresses with a video signal. The circuit compared the SYNC signals from both sources to decide whether to ramp the clock up or down. I have the circuit somewhere on my PC, if anybody wants it.Article: 90920
>> The element we're missing is the middle level documentation. To me this is >> a detailed block diagram with enough verbiage or whatever to describe the >> flow of the design and how the major functions work together. This level of >> documentation is not being captured in our designs and it becomes tough for >> another developer to pick up a design and fix anything but the most minor >> items. > > I use regression testing, code comments and > source control to cover these problems. Does this really cover the problem the OP is outlining Mike? If one of your designs is handed to another engineer with the details of a bug that your testbenches don't pick up, it's going to be really hard for the new engineer to know where to look without some top level hierarchical description of the design. One idea I had was a system where a top level hierarchy could be drawn. Each block could represent sub levels of the hierarchy/design modules etc, data paths would be shown here. If a block represents a design module it could be drawn with a bold (?) outline to represent that, and clicking it (or hyperlinks in the block) would open up source code, testbenches, scanned design notes/timing diagrams for that particular module. If a block represents a level of hierarchy then it could be clicked down through to the next level. It's the best way I can think if of collating all the design documentation for a design in a manner that makes it easier to see what's doing what in the overall scheme of things. Nial.Article: 90921
"rk" <stellare@nospamplease.comcast.net> wrote in message news:Xns96FA113D829FFrk@216.196.97.136... > http://klabs.org/history/ech/agc_schematics/ And the guy built one in his basement! Took him four years. http://klabs.org/history/build_agc/index.htm I'm reminded of Wallace and Gromit's Grand Day Out. Personally I'd like to convert the design to VHDL so I can have one running in a single FPGA. The 3-input NOR gates are simple, but a glance at the circuits shows many other types of circuits involving small pulse transformers etc. Many of the gates are used to make asynchronous cross-coupled SR latches and I suspect those may not suit the generally synchronous nature of FPGA chips. It may be better to devise functional block equivalents rather than trying to copy the low-level design. Oh well, if someone has more time than I do... :-)Article: 90922
I don't want to suppress warnings in case I do something questionable but I would like to address these warnings. Like what did I do that created them in the first place? I noticed on the FPGA editor that there are four DCMs that I did not instantiate. There seems to be something automatically being assigned. Brad SmallridgeArticle: 90923
"Brad Smallridge" <bradsmallridge@dslextreme.com> schrieb im Newsbeitrag news:11lsdpff8e8ml69@corp.supernews.com... > I don't want to suppress warnings in case I do something questionable but I > would like to address these warnings. Like what did I do that created them > in the first place? I noticed on the FPGA editor that there are four DCMs > that I did not instantiate. There seems to be something automatically being > assigned. > > Brad Smallridge > > those 4 DCMs are V4 NBTI 'issue' workaround. it is explained in some xilinx docs... anttiArticle: 90924
Hi all, I need a 16 words deep FIFO. I'm using the Xilinx FIFO Generator Core. I chosen an asynchronous FIFO, but I found an odd behaviour. The FIFO stores only 15 words then the Full Flag goes high. Is it normal? Why isn't it storing 16 words? I tried to monitor the number of words in the FIFO so I added the RD_DATA_COUNT and WR_DATA_COUNT outputs, they should 4 bits wide but instead they are 2 bits wide, so the count arrives at 3 and then it stops. Where is my error? I'm starting thinking tha in order to have 16 words I have to implement a 32 words FIFO.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z