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Thanks Peter. If you need master-slave ISERDES to get 7 bits, are there any layout issues, pin assignment issues that would cause problems or crowding? I only need 16 ISERDES total. BradArticle: 90926
You "chose an asynchronous FIFO" design. Why? Is your design synchronous, with the same clock for read and write? If so, use the synchronous design, it is much simpler and easier to understand. What is the max clock rate? Which Virtex or Spartan family? Peter AlfkeArticle: 90927
dear Before opening case, i would try fixing warnings. Warnings 410,163,164 are very weird, since i am using Xpower 6.3.03i, xc2vp30-7ff896..and the logic is simple counter... Any suggestions will be nice...ThankyouArticle: 90928
Peter Alfke wrote: > You "chose an asynchronous FIFO" design. Why? I chose the asynchronous one because I need two different clocks for reading and writing. Clock for write is 128 MHz. clock for read is 32 MHz. > Which Virtex or Spartan family? VirtexII, VP50.Article: 90929
Nial Stewart wrote:
> If a block represents a design module it could be drawn with a bold (?)
> outline to represent that, and clicking it (or hyperlinks in the block)
> would open up source code, testbenches, scanned design notes/timing
> diagrams for that particular module.
>
> If a block represents a level of hierarchy then it could be clicked down
> through to the next level.
I agree, but a good editor can do this. See:
http://opensource.ethz.ch/emacs/vhdl-mode.gif
-- Mike Treseler
Article: 90930This is not an answer to your query but rather a question to you: How did you include the generated FIFO from Core Generator in your project? (I am assuming you're using ISE) Did you have to compile the cores seperately? Or did ISE take care of it?Article: 90931
I started with vhdl and then saw communication industry shift to verilog. Now I use verilog all the time. I find that there are more resources dealing with verilog than vhdl. You mentioned you are trying to start with altera devices, I notice that the newer design examples and documentation on altera's website also uses verilog. >From a marketability standpoint - I see more job/contractor postings that require verilog expertise than vhdl. >From language standpoint - I think both vhdl and verilog have made strides towards ease of use with their latest standards. but you'll have more fun with verilog once you master it. Finally, to add to what others have said regarding thinking hardware - do not choose verilog because it will let you write software like code. For the best quality hardware it is imperative that you think hardware when you are writing code... or should I say describing hardware. -sanjayArticle: 90932
In addition, I like to always use binary notation after an arithmetic operator. In past, I have seen different simulators behave differently due to the way they may represent integers differently. I don't think it is so much of a problem here. But things can get tricky if you are addin negative nos or multiplying big nos. overflow = overflow + 1 can be written as overflow <= overflow + 1'b1 -sanjayArticle: 90933
"fpgabuilder" wrote: >>From a marketability standpoint - I see more job/contractor postings >that require verilog expertise than vhdl. Depends on location. For the USA as a whole, I just checked Monster.com and found the following posted jobs: 113 hits for "fpga and verilog" 148 hits for "fpga and vhdl" Looks to me like VHDL is still more popular. -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 90934
I stand corrected. Thanks for running that comparision. -sanjayArticle: 90935
If your 32 MHz clock is really derived from, and thus synchronous with, the 128 MHz, then I would treat this as a synchronous FIFO. Asynchronous means that you have no idea of, and no control over, the phase relationship between the two clocks. And asynchronous FIFO control is far trickier than synchronous, just because of the unknown and shifting phase relationships, and the associated possible decoding glitches and even metastability. Synchronism makes all this so much easier. Peter AlfkeArticle: 90936
Why does it not seem right that you as an author reserve at least a few rights when giving most of your rights on a paper away for free to a commercial publisher? I think it is ridiculous that publisher ever demanded exclusive rights without compensation. If you want to print conference proceedings you can do that with nonexclusive rights. And I am not the only one. A few years a ago a study was published that showed, that papers that are available online for free are cited twice as often as other papers. As a result more and more authors refused to give away exclusive rights. Universities made it their policy that the right to publish on the university homepage must stay with the university. http://www.nature.com/nature/focus/accessdebate/index.html Publishers that did not want to play that game risked to lose conference proceedings contracts. Most publishers now allow the author to keep the right to publish on the authors webserver. This is a minimalisitc compromise on the side of the authors. O'reilly goes a large step further: http://press.oreilly.com/pub/pr/1042 I suggest to every scientific author at least to try to retain the rights for his work. Once your paper is accepted by a conference committe, you get the copyright transferal from from the publisher with a few weeks delay. Just refuse to sign it and send them a note that you put the paper under a creative commons license. I doubt that the publisher is going to explain to the conference chair that they are not going to print your paper because they can not get exclusive rights. After all you are offering them a full set of rights for free. Kolja Sulimma Austin Lesea schrieb: > Kolja, > > Interesting. I knew I could distribute it internally, but fram what you > say, it appears I may also publicly post it on the Xilinx web site > (external world)? That doesn't seem right to me... > > Austin > > Kolja Sulimma wrote: > >> Austin Lesea wrote: >> >> >>> Since we wrote this, IEEE owns the copyrights, and we can no longer >>> distribute the paper. >> >> >> >> Not true. The IEEE copyright poolicy states that >> >> "Upon transferring copyright to IEEE, authors and/or their companies >> have the right to post their IEEE-copyrighted material on their own >> servers without >> permission, provided that the server displays a prominent notice >> alerting readers to their obligations with respect to copyrighted >> material and that the posted >> work includes an IEEE copyright notice." >> >> As Xilinx employees are authors and co-authors of quite a number of >> papers, a collection - maybe on the XUP homepage - would be nice. >> >> Kolja SulimmaArticle: 90937
Kryten wrote:
>"Zara" <nospam.yozara@terra.es> wrote in message
>news:8l2sl1hagkl4hp6o8n44jhtlnae3pqhut4@4ax.com...
>
>
>
>>Our OSD works on SDI digital video.
>>
>>
>
>I can imagine wanting to sync to an ordinary video camera as used in
>security applications. I guess that would be slightly harder.
>
>A long time ago I saw an article where a 6845 was used as part of a PLL to
>sync video frame addresses with a video signal. The circuit compared the
>SYNC signals from both sources to decide whether to ramp the clock up or
>down.
>
>I have the circuit somewhere on my PC, if anybody wants it.
>
>
>
>
>
A while back I did a video design that brought the image in on the
incoming video timing, transferred it to a slightly fast local clock for
the processing and then returned it to the incoming video timing at the
output. We did it this way to avoid using external PLLs. Just offering
it as an alternative approach.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 90938fpgabuilder wrote: -snip- > > Finally, to add to what others have said regarding thinking hardware - > do not choose verilog because it will let you write software like code. > For the best quality hardware it is imperative that you think hardware > when you are writing code... or should I say describing hardware. > Slightly off topic, but: For that matter if you're writing software for an embedded system you should be thinking about the assembly being generated _and_ the hardware consequences. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 90939
Hi,
I'm missing something here, I think. I used EDK create/import IP wizard
to create a custom IP that has one s/w accessible register. I want to
modify the data (shift, rotate, add, etc.) received from a terminal and
read it back. I didn't modify the slave read/write example code
generated. I wrote a program in C that uses custom IP library for
read/write, but I always read a 0. If I hardcode IP2Bus_Data, I could
read that data. I did a test that read/write LEDs before, and it worked
just fine. But it seems like I couldn't get it to work if I just modify
the Bus2IP_Data signal and read it back. I'm not familiar with VHDL.
Can anyone point out to me? Thanks!
Auto generated read/write that I use:
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_select is
when "1" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0 ) is
begin
case slv_reg_read_select is
when "1" => slv_ip2bus_data <= slv_reg0;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data;
IP2Bus_Ack <= slv_write_ack or slv_read_ack;
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
Article: 90940>> > A while back I did a video design that brought the image in on the > incoming video timing, transferred it to a slightly fast local clock for > the processing and then returned it to the incoming video timing at the > output. We did it this way to avoid using external PLLs. Just offering > it as an alternative approach. > My last design does OSD (and other things, of course) using this same approach. The fpga + sdram runs at the pixel clock doubled by DLL (Spartan2E), 54 Mhz. The stream is digitized, OSD with graphics is super-imposed on the stream, the played back. The sdram stores stills when needed. The DLL can lock to the sligthly jittering pixel clock (that's locked to line syncs). Made more than 2k pcs with no problems.Article: 90941
Does anyone here have any experience with running Linux on the V2Pro? Thanks, AustinArticle: 90942
Hi again, I forgot to mention my target is virtex-II pro fpga. Thanks.Article: 90943
"Austin Franklin" <aus3tin@darkr00m.com> schrieb im Newsbeitrag news:KIv7f.14466$xk2.151@fe06.lga... > Does anyone here have any experience with running Linux on the V2Pro? > > Thanks, > > Austin > I suppose quit a lot of people do. But what is what you need? AnttiArticle: 90944
On a sunny day (Tue, 25 Oct 2005 11:15:57 -0700) it happened Phil Hays <Spampostmaster@comcast.net> wrote in <patsl15a4mb135g980b8mqt1t66snnukgf@4ax.com>: >Depends on location. For the USA as a whole, I just checked >Monster.com and found the following posted jobs: > >113 hits for "fpga and verilog" >148 hits for "fpga and vhdl" > >Looks to me like VHDL is still more popular. Google: 'fpga vhdl sucks' 2460 hits 'fpga verilog sucks' 1340 hits ;-) _________________________________________ Usenet Zone Free Binaries Usenet Server More than 140,000 groups Unlimited download http://www.usenetzone.com to open accountArticle: 90945
Hi Gert, > Fine, thanks for reply. I am aware that VHDL is a matter of specifying. > If you can recommend documents or books, please don't hesitate. Noticing you're very probably Dutch, you could try Bert Molenkamp's VHDL book - it's a bit dated but will give you a very thorough understanding of the language and what which construct generates. There's a PDF version that can be found here: http://wwwhome.cs.utwente.nl/~molenkam/vhdl_boek/ Best regards, BenArticle: 90946
Hello Everyone, I am doing a project on Implementing 10/100 ethernet mac on a fpga using vhdl. I saw the link on fpga4fun.com, its implemented in verilog and also i am not sure why he included ipaddreses and udp header. i guess mac addresses of PC and fpga board should be sufficient. I have many questions on this. Infact i would like to speak with or chat with anyone who know something about this. I would really appreciate if you could give your messenger id or telephone number so that i can discuss about this for sometime. MY MAIN OBJECTIVE AND FEW QUESTIONS: I am implementing Ethernet MAC(ethernet packet transmit and receive modules) on fpga using vhdl and i am trying to transfer the data between the xilinx virtex 4 fpgaboard and the PC through the ethernet cable. There is a DP83847 Ethernet PHY chip on the fpga board. I need to test this chip, by sending and receiving ethernet frames between fpga and PC. I am attaching the xilinx virtex-4 fpga manual(page 17-ethernet) and the DP83847 ethernet data sheet for your reference. I am able to hardware reset the PHY on the fpga board. when i connect the fpga to PC through ethernet cable, i can see the link active on the PC. And also , by default whenever the PHY is being reset, its in full duplex mode. I understand that i need to write a small state machine, which creates an ethernet frame ie (preamble, destination address, source address, length/type, data, pad zero, crc) and send it 4 bits every clock cycle(txclock -MII interface) by making the transmit enable high. I didnt quite understand about implementing the analog part in the fpga, that you were saying in the end. 1)My ethernet frame consists of Preamble, destination address, source address, length/type, data, padded zeros, crc The destination and source address i am using the physical MAC address and not ip addresses, is it okay? 2)How do i view on my PC , what ethernet frames are being sent from the fpga board. Is there any software which can detect the ethernet frame's sent to the pc. If yes, Please suggest?( ethernet frame consists of only mac addresses and no ip addresses). thanks ashwinArticle: 90947
The problem with programming CPLDs and PROMs using SystemACE is that the programming algorithm for these devices is non-deterministic and require branch on condition flows to work reliably. SystemACE does not provide this capability. That is the reason that the uP flow detailed by XAPP058 is needed. As also indicated, an interesting question to ask is why do you want to configure your CPLD every time you power up? Is your design pattern changing all the time? Is this some sort of demo board? Benjamin Todd wrote: > I know this isn't exactly comp.arch.cpld... > > does anyone know of a COTS solution for programming a (Xilinx) CPLD without > using PC + Windows + Impact etc etc. (a stand alone chunk of hardware with a > way for me to give it a set of bit files and a Program button would be nice) > > I want to load one bit-file into a device to run a test, then once the test > is finished load a second bit-file - but i'm investigating a stand alone > solution not using a PC + Cable + Software etc etc. > > Any pointers are welcome. > Thanks! > Ben > Benjamin TODD > > ABCOIN > > CERN - European Organisation for Nuclear Research, > > Accelerator and Beam Controls - Infrastructure division. > > Building 864:1A01, Meyrin > > Geneva 23, Switzerland, CH-1211. > >Article: 90948
No problem, not even with ten bits parallel. Some of the configuration-oriented pins in the center do not have a SerDes. that's why i wrote "almost". You will not run into any problems in this regard. Peter AlfkeArticle: 90949
Gert Baars wrote: > Fine, thanks for reply. I am aware that VHDL is a matter of specifying. > If you can recommend documents or books, please don't hesitate. Take a look at part 2 of the VHDL FAQ at http://www.vhdl.org/comp.lang.vhdl/ Section 2.6 lists some recommended books, though there is not much in the way of description for many of them. I find Digital Systems Design with VHDL and Synthesis by Chang to have some good VHDL examples, while the Ashden book is also a staple on my bookshelf. If you want to look more at FPGA from a hardware point of view, then try The Design Warrior's Guide to FPGAs by Maxfield. Good Luck. David
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