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Thanks for the replies. I wasn't suggesting using the reverb method described above in real life, it was just something with fairly extreme parameters to use as an example when asking questions about fpgas. I've recently changed jobs from a computer science department to an engineering department, and am interested in learning about the new tools available to me in my new environment. We do have hardware and I believe software for programming FPGAs here, and was hoping to try some experiments. If I end up doing something "real" with FPGAs, then it would be in the audio/musical domain. And looking at past postings on this group that appears to be a fairly common application domain of interest. Cheers, Ross-cArticle: 92626
Frank wrote: ... > I don't know what you people are talking about. > Back to my question, how do I make a +-5V? If you don't know what we're referring to, you're better off buying what you need. Power supplies are cheap compares to your board. If you post your current requirements, we can suggest specific hardware. Using supplies with adjustable voltage but without knob locks is a fairly common way to smoke parts. Be careful. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 92627
Ray, OK. We will try to do better. I will look at how email push works now, and see if there is an opportunity here. Meantime, everyone stay tuned for FIFO16 news, as the story isn't done yet. For sync case, we know the delay 'fixes' the issue. For the async case, there is a whole lot of work going on RIGHT NOW to figure out what is the "problem" and what is the (simple) solution. Austin Ray Andraka wrote: > Austin Lesea wrote: > >> Ray, >> >> I hear you, and understand your concern. >> >> I also have been in the same situation you were in, and had the same >> feelings. >> > > Austin, > > I think you did the right thing with regards to NBTI. Yes, it > apparently is a non-issue, but before you knew it was a non-problem you > notified the customers and therefore we were aware of it being a > potential problem. It is much better, IMHO, to err on the side of > caution (ie, a false positive) rather than to under-report a real > problem. Yes, I got caught up in the NBTI thing too, and wound up > rewriting the Xilinx macro (long story), but in the end we took it out > even before Xilinx scaled back the severity because we never saw any > evidence that NBTI was affecting the design. > > My point with the synchronous FIFO application is that that is a real > problem that affects real designs unless it is designed around. I'm > pretty sure Xilinx understands that it is a problem, yet there is no > public pronouncement warning a designer to look out for it. The time is > already past for getting that caution added to the user manual. > > I'd like to be included on any internal email push list for issues > regarding the V4, as I'd rather find out about them from Xilinx than > have to discover them on my own after the design is done. >Article: 92628
Eric, Yes, he will have problems. Glitches on LUTs will be the least of his problems. Austin Eric Smith wrote: > I asked about the possibility of glitches on LUT outputs. Peter gave > a definitive response, and Symon wrote: > >>You got a good answer from Peter. However, my smarty pants response is to >>never put yourself in a position where you care what the answer is! You'd >>never clock a FF from the output of a LUT. Would you? ;-) > > > I fully agree; my designs are fully synchronous. > > The reason the whole question came up is that a friend is trying to > cram old TTL logic designs into an FPGA without redesigning them to > be synchronous, so he has latches, S-R flops, and other horrible stuff. > I was wondering whether an S-R flop implemented as two cross-coupled > gates using a LUT for each gate could even be guaranteed to function > correctly; if LUTs can have output glitches they would not. > > I'm still trying to convince my friend that his approach is likely to > cause him much grief. > > EricArticle: 92629
John, You bring up an interesting point. Yes, the squeaky wheel gets the grease (or in this case, the gorillas get the bananas). But, I had a strange thought: how many start-ups, consultants, etc. are there that need prototyping quantities (1 to 3 parts)? Does it make sense to have a program for smaller outfits (which are no less important to Xilinx, as CIS** was small once, too)? Is this the real case for web-based product availability? AustinArticle: 92630
Fred Marshall wrote:
> "Frank" <Francis.invalid@hotmail.com> wrote in message
> news:438fa5a4@news.starhub.net.sg...
>
>>I have a large board which asks for three power supplies, +3V, +3.3V and
>>+-5V.
>>First two can be easily satisfied with two HP power supplies (each has its
>>own
>>GND pin also). Regarding +-5V, can I replace with an HP power supply set
>>to
>>10V, -5V pin connect to HP's ground and +5V to power?
>
>
> You might with some caveats.
> First, the intended +-5v supply needs to be floating with respect to the
> other supplies.
> Then the 10v voltage difference can be reference wherever you want in theory
> and often in practice.
>
> The challenge is: now that you've floated the supply, how will you reference
> it to the ground or 0v point on the board?
>
> Think of the +-5v supply as a 10v battery. A battery "floats" with no
> problem.
> Unless you do more, the result looks like this:
>
>
> +------------------------------>+5v
> |
> |
> +----+ +--------------->+3.3v
> | 10v| +----+
> +----+ |3.3v| +----------+3v
> | +-+--++----+
> | | |3.3v|
> | | +-+--+
> | | |
> | | |
> | +-----+---------> 0v: the reference for +3.3v, +3v
> |
> |
> |
> +------------------------------>-5v
>
> With the 10v battery floating, there is no reference to the
> other batteries. Current flowing through the circuit board will cause
> the +/-5v terminals to go almost anywhere relative to 0v. Depending on
> what's on the board,
> the +5v terminal could end up at -6v and the =5v terminal at -15v (both
> relative to 0v of course).
>
>
>
> +------+----------------------->+5v
> | |
> | | +--------------->+3.3v
> +----+ | +----+
> | 10v| | |3.3v| +----------+3v
> +----+ ++-+ +-+--++----+
> | |R1| | |3.3v|
> | ++-+ | +-+--+
> | | | |
> | | | |
> | +-------+-----+---------> 0v: the reference for +3.3v, +3v
> | +--+
> | |R1|
> | ++-+
> | |
> +------+----------------------->-5v
>
> A resistor divider with current much higher than the +/-5v
> loads and connected to the 0v reference will refer the +/-5v
> to the rest of the batteries.
> It's not a very elegant or even practical solution but it makes the
> point to address your question.
You can make Fred's solution more practical by adding an operational
amplifier that can deliver the difference between +5 and -5 currents.
+------+-------------------------------------------->+5v
| |
| | +--------------->+3.3v
+----+ | +----+
| 10v| | |3.3v| +---------+3v
+----+ ++-+ +-+--+ +----+
| |R1| +----------+ | |3.0v|
| ++-+ | |\ | | +-+--+
| | +---|-\ | | |
| | | +---+----------+------+---------> 0v
| +--------|+/
| +--+ |/
| |R1|
| ++-+
| |
+------+----------------------->-5v
Is it worth it?
Jerry
--
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ
Article: 92631"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag news:dmptik$2ck5@xco-news.xilinx.com... > John, > > You bring up an interesting point. > > Yes, the squeaky wheel gets the grease (or in this case, the gorillas get > the bananas). > > But, I had a strange thought: how many start-ups, consultants, etc. are > there that need prototyping quantities (1 to 3 parts)? > > Does it make sense to have a program for smaller outfits (which are no > less important to Xilinx, as CIS** was small once, too)? > > Is this the real case for web-based product availability? > > Austin > Hi Austin, there are several companies to my knowledge waiting for 2 pieces of FX60 .. there are PCBs either manufactured or ready to go to production. so it is weird that those companies are unable to get the parts. its not required to the chips are available from web online, but customers working with leading edge technologies (V4 + PCIe 8 lane as example) and READY to test SHOULD get the silicon as EARLY as possible. AnttiArticle: 92632
Hi, I am writing a patent application for FPGA and have no prior experiences with patent writing. I found that in Xilinx patents, all lookup table equations are described in AND/OR/Multiplexer circuits in its claims. Describing a logic connection for a lookup table in claims is much more complex in English than presenting an equivalent logic equation. For example, a lookup table has the equation: Out <= (A*B) + (C*D); It is much more concise and simpler than describing the circuit in AND/OR gate circuits. Do you have experiences with and any advices on writing an equivalent logic equation in a patent claim field ? Any consequences? Thank you. WengArticle: 92633
Here's a cheap and quick, potentially noisy solution: 1. Buy two 5VDC "wall wort" power supplies. 2. connect the (-) from one to the (+) from the other. This is your common ground lead.. 3. The + lead will give you +5VDC 4. The - lead will give you -5VDC. Make sure the wall worts are rated to deliver enough current otherwise you'll get too much voltage drop for your app. Note that this supply is UNREGULATED, that is, increasing load will decrease your voltage. If you need a regulated supply, use 7-12VDC wall worts (to compensate for the voltage drop across the regulators), buy a 7805 positive and a 7905 negative 5V regulator, two 3300uF electrolytics and two 1uF ceramic caps to filter the output and a small PCB. There are tons of diagrams how to arrange things to get what you want. Google is your friend. Total cost of parts should be about $5 to build the regulator, plus some sort of enclosure if you require. If you happen to have two matching wall worts of >6VDC you can probably use them if you regulate, the regulator chips can accept up to ~35VDC. note that with larger input voltages you'll need to use heatsinks on the regulators to dissipate the extra power/heat. Dave "Frank" <Francis.invalid@hotmail.com> wrote in message news:438fcbcb@news.starhub.net.sg... > > "Jerry Avins" <jya@ieee.org> wrote in message > news:gpKdnbflleKAIhLeRVn-vg@rcn.net... > > Steve Underwood wrote: > > > Jerry Avins wrote: > > > > > >> Ryan Weihl wrote: > > >> > > >>> Michael R. Kesti wrote: > > >>> > > >>>> Frank wrote: > > >>>> > > >>>>> I have a large board which asks for three power supplies, +3V, > > >>>>> +3.3V and > > >>>>> +-5V. > > >>>> > > >>>> > > >>>> > > >>>> > > >>>> If I read you correctly, that's four supplies: +3V, +3.3V, +5V, and > > >>>> -5V. > > >>>> > > >>>>> First two can be easily satisfied with two HP power supplies (each > > >>>>> has its own > > >>>>> GND pin also). Regarding +-5V, can I replace with an HP power > > >>>>> supply set to > > >>>>> 10V, -5V pin connect to HP's ground and +5V to power? > > >>>> > > >>>> > > >>>> > > >>>> > > >>>> No. Doing so would provide zero volts to the board's -5V rail and > > >>>> +10V to > > >>>> its +5 rail. > > >>>> > > >>>> You need four supplies. > > >>>> > > >>> will an ATX supply not do? > > >>> rw > > >> > > >> > > >> > > >> Maybe not. Compound switchers need a load on the main supply in order > > >> to come up, and the auxiliary supplies aren't always well regulated. > > >> > > >> Jerry > > > > > > > > > They also make more noise than a neo-natal nursery. :-) > > > > If he knows what he's doing, ha can load the 10V supply with a beefy > > op-amp connected as a follower to a divider across the rails and ground > > its output. If something goes wrong, it can blow the board unless he > > uses Zener-cum-fuse protection. There are DC-DC power-supply bricks and > > chips that can probably supply all the -5 needed from a +5 supply. > > > > Jerry > > -- > > Engineering is the art of making what you want from things you can get. > > ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ > > I don't know what you people are talking about. > Back to my question, how do I make a +-5V? > >Article: 92634
I must admit that given our size we generally do better at getting the silicon than most. I remember showing our Broaddown2 product at a large event, in a very large hotel, in SF, in May last year and lots of people hadn't seen a real Spartan-3 at that stage which was quite funny given the audience. We do get a very unusually perspective because we have worked with every kind of company from one man bands to the largest. We have sat in some very high level presentations (representing customer) getting actively involved with customer delivery and pricing and we do see the difference between small guys and the large ones. The point being we have seen accounts/designs to Xilinx, or Altera, lost because a small number of pieces of silicon are not made available at the right time. Often if a customer brings us in early enough we can help them in a number of ways and generally avoid the problem but we can only do the near impossible at best. There is a problem for the small customer in that distributors are not very interested if they fail the 80:20 rule generally applied out there. Sometime little guys turn out big and we have already a few of those within our customer base. Anything that eases the acquiring of silicon is a win win situation and we have won accounts in past with our own strategic silicon stock that we carry. That is more than most distributors are doing now. The Xilinx website sales are useful we have already pointed one UK customer at that for something we didn't have nor the local distributor. I would say more devices please even if they are at book price. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Austin Lesea" <austin@xilinx.com> wrote in message news:dmptik$2ck5@xco-news.xilinx.com... > John, > > You bring up an interesting point. > > Yes, the squeaky wheel gets the grease (or in this case, the gorillas get > the bananas). > > But, I had a strange thought: how many start-ups, consultants, etc. are > there that need prototyping quantities (1 to 3 parts)? > > Does it make sense to have a program for smaller outfits (which are no > less important to Xilinx, as CIS** was small once, too)? > > Is this the real case for web-based product availability? > > Austin >Article: 92635
For most Xilinx families datasheets there is a page near the end of section that has an I/O count versus package table. There is also information in Xcell which you can download here http://www.xilinx.com/publications/xcellonline/index.htm . Look at the last few pages for shortform part data. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan3 Development Board. http://www.enterpoint.co.uk "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:11ov5j451ce316f@corp.supernews.com... > Hi Okashi, > > I found the tutorial at XESS.COM very useful when I was just starting out. > That was a year or so ago and things change. Seems like you are having > trouble > with pin IO counts, however, so you should go to the Xilinx site and look > for there > comparative data. Or just ask the group, we'll size it. > > Brad Smallridge > aivision.com > > "Okashii" <nordicelf@msn.com> wrote in message > news:438e3387$1@news.starhub.net.sg... >> Hi there, pardon me but I'm a newbie at fpga and stuff. I was using >> Xilinx ISE and vhdl to build some components and no matter what the size >> of component I keep getting "number of bonded iob" exceeded. Then after >> some observation I finally realized that its the size of bits of the >> ports of the top level component :P. May I know where I can find layman >> information on fpga online that explains what are "slices, slice >> flip-flops, LUT, IOB" and all these? >> Thanks in advance! >> > >Article: 92636
I am having trouble with the Xilinx ISERDES in Master/Slave configuration. I
can get data from the first output register but nothing from any of the
others. They are stuck low. It seems as if the data isn't clocking through
although the lock and the counter on the bit clock (cam1_clk7x) scope OK.
When I go into the FPGA layout editor all the signals connections seem to be
there. There is one small problem with the SHIFTIN signals of the master,
in that they appear to be unconnected, and I do get a DANGLING PIN warning
on these pins. These pins can not be connected to anything but another
ISERDES or OSERDES so I suppose connecting them to '0' is not allowed. I
tried to connect them to open as suggested by the V4 data manual but that
generated an early syntax error and abort.
Any help is much appreciated. Here is the code:
-- Company: Ai Vision
-- Engineer: Brad Smallridge
-- Create Date: 17:34:16 10/24/05
-- Design Name: LVDS
-- Module Name: top - Behavioral
-- Project Name:
-- Target Device: ML40x
-- Tool versions: 7.1.4
-- Description: Accepts LVDS Channel Link / Camera Link
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port(
sys_rst_in : in std_logic;
gpio_exp_hdr2 : in std_logic_vector( 9 downto 0); -- HDR2 diff
gpio : out std_logic_vector( 3 downto 0) ); -- LEDs
end top;
architecture Behavioral of top is
signal reset : std_logic;
signal reset2 : std_logic;
signal cam1_xclk : std_logic;
signal cam1_clk7xdiv2 : std_logic;
signal cam1_lock7xdiv2 : std_logic;
signal cam1_clk7x : std_logic;
signal cam1_lock7x : std_logic;
signal cam1_x0 : std_logic;
signal shift1 : std_logic;
signal shift2 : std_logic;
signal q : std_logic_vector(6 downto 0);
signal test_counter_3 : std_logic_vector( 9 downto 0);
component dcmfx2
port(
clkin_n_in : in std_logic;
clkin_p_in : in std_logic;
rst_in : in std_logic;
clkfx_out : out std_logic;
clkin_ibufgds_out : out std_logic;
clk0_out : out std_logic;
locked_out : out std_logic );
end component;
component dcm_140_280
port(
CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED_OUT : out std_logic );
end component;
begin
cam1_x0_ibufd_inst : IBUFDS
port map (
O => cam1_x0,
I => gpio_exp_hdr2(1),
IB => gpio_exp_hdr2(0) );
x0_iserdes_master : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- DDR SDR
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
NUM_CE => 1, -- clock enables 1,2
SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => q(0),
Q2 => q(1),
Q3 => q(2),
Q4 => q(3),
Q5 => q(4),
Q6 => q(5),
SHIFTOUT1 => shift1,
SHIFTOUT2 => shift2,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => cam1_clk7x,
CLKDIV => cam1_xclk,
D => cam1_x0,
DLYCE => '0',
DLYINC => '0',
DLYRST => '0',
OCLK => '0',
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => reset2 );
x0_iserdes_slave : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- "DDR" "SDR"
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
NUM_CE => 1, -- clock enables 1,2
SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => open,
Q2 => open,
Q3 => q(6),
Q4 => open,
Q5 => open,
Q6 => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => cam1_clk7x,
CLKDIV => cam1_xclk,
D => '0',
DLYCE => '0',
DLYINC => '0',
DLYRST => '0',
OCLK => '0',
REV => '0',
SHIFTIN1 => shift1,
SHIFTIN2 => shift2,
SR => reset2 );
cam1_dcmfx2 : dcmfx2
port map(
clkin_n_in => gpio_exp_hdr2(6), -- 40 MHz
clkin_p_in => gpio_exp_hdr2(7), -- Differential pair
rst_in => reset,
clkfx_out => cam1_clk7xdiv2, -- 140MHz
clkin_ibufgds_out => open,
clk0_out => cam1_xclk, -- 40 MHz
locked_out => cam1_lock7xdiv2 );
cam1_dcm_140_280: dcm_140_280
port map(
CLKIN_IN => cam1_clk7xdiv2, -- 140 MHz
RST_IN => reset2,
CLK0_OUT => open,
CLK2X_OUT => cam1_clk7x, -- 280 MHz
LOCKED_OUT => cam1_lock7x );
reset <= not sys_rst_in;
reset2 <= not cam1_lock7xdiv2;
led_test_counter_3_process:process(cam1_clk7x)
begin
if( cam1_clk7x'event and cam1_clk7x='1') then
if( reset='1' ) then
test_counter_3 <= (others=>'0');
else
test_counter_3 <= test_counter_3+1;
end if;
end if;
end process;
gpio(0) <= q(0); -- OK -- looks like image data
gpio(1) <= q(1) or q(2) or q(3) or q(4) or q(5) or q(6); -- stuck low
gpio(2) <= test_counter_3(9); -- OK
gpio(3) <= cam1_lock7x; -- OK
end Behavioral;
Article: 92637Yes - FROM, TO is correct. The constraints are still being applied incorrectly FROM my specified TO group, going to some arbitrary destination. Not sure what's up. Thanks, Dave. "Russ Panneton" <pannetron@hotmail.com> wrote in message news:dmnusn$2ck1@xco-news.xilinx.com... > Dave Roberts wrote: >> Dear all, >> >> I place a timing constraint on a pair of registers (from, to) either side >> of some logic. After I run the ISE 6.3 toolchain, I look at the actual >> delays for the constraint in Timing Analyzer. >> >> The constraint seems to have been applied from the source register which >> I specified as my destination, to a register or pad elsewhere in the >> design. The constraint is applied to logic other than specified. >> >> Any suggestions? >> >> Cheers, >> >> Dave. > > Can you check the PCF to see if the FROM TO still references the correct > register pair? > > RussArticle: 92638
Hmm. I assume you mean "acceptable" to the USPTO instead of legal. I suppose since Xilinx does hardware, then its claims would be in gates rather than an equation which could ambiguously be construed as hardware, software or mathematics. Concise and simple are not the focus of the claims section of the patent. The claims have to be narrowed so they don't intrude on other patents. If you want a simpler and easy to follow explanation using the equation notation, you can put it in the preferred embodiment section. Brad Smallridge aivision.com "Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1133542596.493746.45760@g43g2000cwa.googlegroups.com... > Hi, > I am writing a patent application for FPGA and have no prior > experiences with patent writing. > > I found that in Xilinx patents, all lookup table equations are > described in AND/OR/Multiplexer circuits in its claims. Describing a > logic connection for a lookup table in claims is much more complex in > English than presenting an equivalent logic equation. > > For example, a lookup table has the equation: > Out <= (A*B) + (C*D); > > It is much more concise and simpler than describing the circuit in > AND/OR gate circuits. > > Do you have experiences with and any advices on writing an equivalent > logic equation in a patent claim field ? > > Any consequences? > > Thank you. > > Weng >Article: 92639
Yeah, real variables are useful for making simulations more readable or for generating data for a testing, but they don't synthesize into real hardware. What are you trying to do? Brad Smallridge www.aivision.com "Simon" <oceanfrea@hotmail.com> wrote in message news:ee92804.-1@webx.sUN8CHnE... > Hi, if anyone could help me. I had declare real variable in vhdl and > everything seems to be working after running simulation using the Xilinx > ISE software. However, when i try synthesizing, it prompt error Real > operand is not supported in this context. Please if anyone could help. I > require floating variables to be declared in my code. Thanks.Article: 92640
Hi Brad, Thank you for your response. 1. Yes, the 'legal' should change to 'acceptable'. 2. I agree with your opinion: "If you want a simpler and easy to follow explanation using the equation notation, you can put it in the preferred embodiment section. " The question arises when the logic equation in LUT is described in the preferred embodiment section, but their correspondent logical circuits are not described in a provisional patent application. When I file for regular patent application later, claims would be invalid because the appropriate circuits are not described in provisional patent application. So I want to know if there is an approved patent with logical equation in its claims or if there is someone having experienced similar scenario, but was declined by USPTO. Thank you. WengArticle: 92641
John, Thank you, Austin John Adair wrote: > I must admit that given our size we generally do better at getting the > silicon than most. I remember showing our Broaddown2 product at a large > event, in a very large hotel, in SF, in May last year and lots of people > hadn't seen a real Spartan-3 at that stage which was quite funny given the > audience. > > We do get a very unusually perspective because we have worked with every > kind of company from one man bands to the largest. We have sat in some very > high level presentations (representing customer) getting actively involved > with customer delivery and pricing and we do see the difference between > small guys and the large ones. The point being we have seen accounts/designs > to Xilinx, or Altera, lost because a small number of pieces of silicon are > not made available at the right time. Often if a customer brings us in early > enough we can help them in a number of ways and generally avoid the problem > but we can only do the near impossible at best. > > There is a problem for the small customer in that distributors are not very > interested if they fail the 80:20 rule generally applied out there. Sometime > little guys turn out big and we have already a few of those within our > customer base. Anything that eases the acquiring of silicon is a win win > situation and we have won accounts in past with our own strategic silicon > stock that we carry. That is more than most distributors are doing now. The > Xilinx website sales are useful we have already pointed one UK customer at > that for something we didn't have nor the local distributor. I would say > more devices please even if they are at book price. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > > "Austin Lesea" <austin@xilinx.com> wrote in message > news:dmptik$2ck5@xco-news.xilinx.com... > >>John, >> >>You bring up an interesting point. >> >>Yes, the squeaky wheel gets the grease (or in this case, the gorillas get >>the bananas). >> >>But, I had a strange thought: how many start-ups, consultants, etc. are >>there that need prototyping quantities (1 to 3 parts)? >> >>Does it make sense to have a program for smaller outfits (which are no >>less important to Xilinx, as CIS** was small once, too)? >> >>Is this the real case for web-based product availability? >> >>Austin >> > > >Article: 92642
Austin Lesea wrote: > Ray, > > > For sync case, we know the delay 'fixes' the issue. > > For the async case, there is a whole lot of work going on RIGHT NOW to > figure out what is the "problem" and what is the (simple) solution. > > Austin, The synchronous case is a subset of the async case. If the sync case were simply a case of an indeterminant delay of the flaq output, then it wouldn't be a problem, however since the synchronous case can screw up the flags if you have two flag events in a row, the same holds true for the async case when the clock edges happen to be close enough together. The async case is actually more problematic, because you can't just add a delay to one of the clocks to "fix" it. It is also more insidious, since it may work fine until one day when your async clocks happen to have the edges align just as the fifo is going empty or full. Obviously, I can't tell Xilinx what to do here, and they can easily tell me to pound sand (yes, I am sticking my neck out here). I think Xilinx owes its current V4 customers the courtesy of a notification that a potential problem has surfaced with the FIFO16s, as they are a key feature in the FPGA architecture.Article: 92643
Hi Simon, He could well have a legitimate reason for reverse-engineering the core. Perhaps he wants to see if anyone is infringing his own patent? Although, from his post, I guess not. Also, I believe it's lawful to reverse-engineer something which is protected by trade secrets rather than a patent. That is, unless you stole the thing you're reverse-engineering. Still, as you say, best not to advertise it whatever the reasons. Cheers, Syms. p...s... I think there's something wrong with your full stop key... In a lot of your posts it keeps coming out in duplicate or triplicate... ;;;---))) "Simon Peacock" <simon$actrix.co.nz> wrote in message news:439019ae$1@news2.actrix.gen.nz... > For starters.. you shouldn't mention "reverse-engineer" and "Xilinx core > generator" in here.. this is a monitored group by both Altera and > Xilinx... > both will not appreciate it. > (not to mention those of us who make our living from the IP business) > > SimonArticle: 92644
<previous replies were snipped> Frank wrote: > I don't know what you people are talking about. > Back to my question, how do I make a +-5V? We need answers to these basic questions: 1)You need -5 volts, +5 volts, +3.3 volts, and +3.0 volts - correct? (can you use just +3.3 volts instead of both +3.0volts _and_ +3.3volts?) 2)How much current do you need for each voltage? 3)What voltages and currents do your 2 HP power supplies produce? Assuming that the HP's can produce negative voltage (with respect to the HP's GND), then set one HP for -5 volts and set the other one for +5 volts. Then use Low-DropOut (LDO) voltage regulators to produce the +3.0 volts and +3.3 volts. Dave PollumArticle: 92645
In article <438fcbcb@news.starhub.net.sg>, "Frank" <Francis.invalid@hotmail.com> wrote: > I don't know what you people are talking about. > Back to my question, how do I make a +-5V? Swing and a miss -- |\/| /| |2 |< mehaase(at)gmail(dot)comArticle: 92646
Dave Pollum wrote: > <previous replies were snipped> > > Frank wrote: > >>I don't know what you people are talking about. >>Back to my question, how do I make a +-5V? > > > We need answers to these basic questions: > 1)You need -5 volts, +5 volts, +3.3 volts, and +3.0 volts - correct? > (can you use just +3.3 volts instead of both +3.0volts _and_ > +3.3volts?) > 2)How much current do you need for each voltage? > 3)What voltages and currents do your 2 HP power supplies produce? > > Assuming that the HP's can produce negative voltage (with respect to > the HP's GND), then set one HP for -5 volts and set the other one for > +5 volts. Then use Low-DropOut (LDO) voltage regulators to produce the > +3.0 volts and +3.3 volts. If those hp supplies are like mine, either the positive or negative terminals may be grounded by a link. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 92647
On 2005-12-02, Dave <dspear99ca@yahoo.delete.com> wrote:
> Here's a cheap and quick, potentially noisy solution:
>
> 1. Buy two 5VDC "wall wort" power supplies.
> 2. connect the (-) from one to the (+) from the other. This is your common
> ground lead..
> 3. The + lead will give you +5VDC
> 4. The - lead will give you -5VDC.
>
> Make sure the wall worts are rated to deliver enough current otherwise
> you'll get too much voltage drop for your app. Note that this supply is
> UNREGULATED, that is, increasing load will decrease your voltage.
Only if you buy unregulated wall warts. You can get regulated
5V wall-warts and cable-lumps. They usually cost more of course.
--
Grant Edwards grante Yow! There's enough money
at here to buy 5000 cans of
visi.com Noodle-Roni!
Article: 92648Ray, I never said the async case was bulletproof. In fact, I said the "jury was still out." Well, the jury is walking back in... They are sitting down... I am intentionally hiding anything, but rather because the solution for the FIFO usage is not fully tested. I am told that the good news is that the sync case is 100% fixed by the ~1ns delay or 180 degree clock phase (whichever is easier to do). The async case solution is also easy (I am told). Austin Ray Andraka wrote: > Austin Lesea wrote: > >> Ray, >> >> >> For sync case, we know the delay 'fixes' the issue. >> >> For the async case, there is a whole lot of work going on RIGHT NOW to >> figure out what is the "problem" and what is the (simple) solution. >> >> > > Austin, > The synchronous case is a subset of the async case. If the sync case > were simply a case of an indeterminant delay of the flaq output, then it > wouldn't be a problem, however since the synchronous case can screw up > the flags if you have two flag events in a row, the same holds true for > the async case when the clock edges happen to be close enough together. > The async case is actually more problematic, because you can't just add > a delay to one of the clocks to "fix" it. It is also more insidious, > since it may work fine until one day when your async clocks happen to > have the edges align just as the fifo is going empty or full. > > Obviously, I can't tell Xilinx what to do here, and they can easily tell > me to pound sand (yes, I am sticking my neck out here). I think Xilinx > owes its current V4 customers the courtesy of a notification that a > potential problem has surfaced with the FIFO16s, as they are a key > feature in the FPGA architecture.Article: 92649
Simon wrote: > Hi, if anyone could help me. I had declare real variable in vhdl and everything seems to be working after running simulation using the Xilinx ISE software. However, when i try synthesizing, it prompt error Real operand is not supported in this context. Please if anyone could help. I require floating variables to be declared in my code. Thanks. I suppose you should RTFM. Carefully. On page 313 of the "XST User Guide" (for version 7.1i) we read, "Note: Functions and procedures in the math_real package, as well as the real type, are for calculations only. They are not supported for synthesis in XST." One problem is that starting on page 285 of that same guide, we read "XST accepts the following VDHL basic types" and on the next page, under the heading "The following types are VHDL defined types," we see REAL listed. This implies that one can use REALs for synthesis. David Bishop has developed a synthesizable REAL package. -a
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