Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
My apologies for not responding to this: my computer crashed big-time, & is only now on the air again. I see several others took up the thread: I trust you got satisfactory advice from them. Emtech wrote: > Hi David > Th > is is for an RGB LED demo display application. > > 1. There will be mixing of colours done at say 3ms intervals for each colour > to stay ithin the 10ms and take avantage of persistance of vision. > 2. Bits accuracy in the duty cycle is not very important since the PWM is > only for brightness control. > 3. The outputs must at least be synchronized to the colour mixing intervals, > i.e. 3ms intervals. In other words, the PWM will further divide the 3ms > intervals to control brightness. > 4. These will only be used in an RGB LED display application hence the only > real importance is the 10ms refresh limit. > > Thank you for your input. > Peter. > > "David Brooks" <davebXXX@iinet.net.au> wrote in message > news:435d7280$0$8621$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > >>Can you further tell us: >>1. What pulse repetition frequency you want >>2. How many bits accuracy in the duty cycle >>3. Must the outputs be synchronised? >>4. Are they to drive model-control servos? (Those often respond not to the >>average energy in the signal, but to the actual width. You can have a very >>long interval between pulses, & still have them work). >> >>Emtech wrote: >> >>>I have an application where I need to implement 24 or up to 32 PWM >>>outputs (8-bit) and >>>am considering using a small CPLD to handle the PWMs instead of doing it >>>all in software. >>>This does add a CPLD to the design, but frees the micro do to other >>>things. >>> >>>Any recommendations on the CPLD & CPLD size without completing the VHDL >>>first? >>> > >Article: 91451
As a licensed user of the Xilinx PCI32 core, where does one get a more comprehensive PCI testbench (stimulus generator) than what comes with the Xilinx PING example. Thanks AnthonyArticle: 91452
How could I implement a bus in my Spartan3 to let it communicate thorough a 16bit wide, 100MHz bus with a Blackfin DSP? Thanks, MarcoArticle: 91453
Anthony Ellis wrote: > As a licensed user of the Xilinx PCI32 core, where does one get a more > comprehensive PCI testbench (stimulus generator) than what comes with > the Xilinx PING example. There are few different options. If you have time just write our own pci transactor models. It's not such a big task if you have the standard. PCI standard is quite well written, but be aware that the state machines in the end may not be the best way to implement the transactor. Add few more states and everything is easier. My transactor (slave+master) is about 1000 lines of Vera code, and took few weeks to write and verify. Of course you can buy ready made test solutions. For example Synopsys Designware Verification IP for PCI. (http://www.synopsys.com/cgi-bin/designware/ipdir.cgi?c=pcimaster_fx&c=pcimonitor_fx&c=pcislave_fx) There are also othe vendors that do such models, just use google. --KimArticle: 91454
hi, I'm using a PPC405 on a Virtex2 pro. I try to allocate memory with malloc() function. It compiles without any problem but malloc returns NULL => no memory is allocated. I set the heap size at 0x0800 in docm. I set need_xil_malloc to false since xil_malloc seems to be used only for MicroBlaze. What's wrong ? Thanks for answer. Tibo ISE 7.1 / EDK 7.1 / SDK with no kernelArticle: 91455
nezhate schrieb: > Hi all, > Can anyone tell me why this occurs : "when synthetizing we get a good > results (time/area) by using an adder contained in the fpga circuit and > when we use an adder that can be manually designed, we get a less > performances (time/area) " ? > Thanks. > Hi, It's quite simple: Imagine in vhdl you write a behavioral statement like y <= a+b; then the synthesis tool knows exactly how to build the best adder for your target architecture. (the same applies for schematic macro symbols) The programmers of the tool have provided all neccessary information about the chips special abilities (e.g. extra carry chains) and how to use these. If you write lots of code to describe the adder architecture, without regards to the FPGAs structure (e.g you insist on creating a ripple adder) then the tool just has to follow your will, and creates exactly what you have designed. It may happen that you are trying to create exactly the same structure as used by the FPGA but the synthesis tool does not recognize it and creates the carry structure anew from general logic elements (eg. LUTs). This of course wastes lots of speed and area. Well, shit happens.. :-) have a nice synthesis EilertArticle: 91456
Antti Lukats wrote:
>AGREE 100%
>
>SRL16 is way useful but I do not see it nearly possible that they will be
>used the best
>way with regular synthesis. so the customer should be at least aware of what
>is needed
>to get the SRL16 being used (automatically) or then use them directly.
>
>Antti
>
>
>
Current synthesis pretty much only instantiates the SRL16 as a fixed
length shift register, and then only if the designer didn't put resets
on the registers. There is supposedly a magic incantation in Synplicity
that will infer a dynamic shift, but for th elife of me I have not been
able to get it to infer that consistently, and the words to the
incantation seem to change with each revision of the software. I find
it to require less effort just to instantiate the SRL16, especially if
you are actually using the dynamic capability. Also, a common mistake
with inferred fixed length shift registers is the synthesis often does
not infer a flip-flop at the SRL16 outputs, which kills clock
performance. Synplify will put a flip-flop at the output of a delay,
but if you have a register deeper than 17 clocks, it strings together
SLR16's with no flip-flops between, which again kills the performance.
(This may have been fixed in later versions, I haven't checked).
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 91457Peter Alfke wrote: > Guys, let's make a deal: > I give you a bit more, more early, and more honest information than you > can read in the press releases. > You, in turn, stop molesting and attacking me whenever I write anything > about dates and avilability. > I am not in marketing, but I am reasonably honest, and I believe in > what I write (or I just don't write about it.) > Isn't that good enough? > Peter > Peter: Don't let grumbling bother you! I appreciate your help! -EliArticle: 91458
Hello: This is a question/comment for the Xilinx people here. Is there a technical (or Marketing) reason that there are not more FPGA's that have lots of logic and RAM resources in a very small package. FOr example an XC3S1500 in a VQ100 or VQ44? I have applications which I need very few I/O but need lots of logic. For example, a CPU that streams A/D data in serially and spits data back out serailly. Also, BRING BACK Ceramic PGA! I understand its an expensive package, but with the high cost of FPGAs, I would rather pay the money to have easier PCB and hand assembly. I love FPGAs work but hate working with BGA's. Its expensive to protoype with. It would nice to lots more logic and RAM in the QFP packages! -EliArticle: 91459
"Eli Hughes" <emh203@psu.edu> schrieb im Newsbeitrag news:dknncg$1ik2$1@f04n12.cac.psu.edu... > Hello: > > This is a question/comment for the Xilinx people here. Is there a > technical (or Marketing) reason that there are not more FPGA's that have > lots of logic and RAM resources in a very small package. FOr example > an XC3S1500 in a VQ100 or VQ44? I have applications which I need very > few I/O but need lots of logic. For example, a CPU that streams A/D > data in serially and spits data back out serailly. > > Also, BRING BACK Ceramic PGA! I understand its an expensive package, > but with the high cost of FPGAs, I would rather pay the money to have > easier PCB and hand assembly. I love FPGAs work but hate working with > BGA's. Its expensive to protoype with. It would nice to lots more > logic and RAM in the QFP packages! > > > -Eli possible the FPGA vendors see no interest in that. pitty. I would really welcome some FPGA in QFN40, with onchip USB and etherner PHY :) but the FPGAs in small packages are rather small. The best small is possible s3e-500 in CP132 8b8 mm for ceramic packages i bet the times are over forever. AnttiArticle: 91460
nezhate wrote: > Hi all, > Can anyone tell me why this occurs : "when synthetizing we get a good > results (time/area) by using an adder contained in the fpga circuit and > when we use an adder that can be manually designed, we get a less > performances (time/area) " ? > Thanks. The adder in the FPGA is a silicon-optimized solution that uses embedded carry chains with very low propagation delays to perform the function. This optimized silicon is used because this is a common FPGA design element that has too many levels of logic for a "manual design" to implement well with the delays between LUTs. The manual design also requires a carry chain set of LUTs to complement the result LUTs. Read up on the FPGA's implementation of carry chains and you'll find dedicated silicon to handle the speed and density.Article: 91461
yusufilker@gmail.com wrote: > Hi, > I take a look at xapp807-Minimal Footprint Tri-Mode Ethernet MAC > Processing Engine. > Performance test results are at Table 5 of the document. > > What i understand from the table TEMAC works at 90mbps.(max speed) > it is supposed to work at least 990mbps, isn't it? > Where is the bottleneck , TEMAC , ultracontroller, FIFOs ? > How can we improve performance? > > thanks, > > yusuf Hi , when you create a TCP/IP stack, the most timing consuming process is the CRC calculation of the IP payload(when is done in SW). The Xilinx Embedded MAC has been tested with the treck TCP/IP. (www.treck.com) and it seems with this HDL TCP/IP stack you can up to 700 mbps (don't remember exactly the bandwith achieved) The MAC itself gives you no limitation. For example in a full duplex mode the MAC just add "55 55 55 55 55 55 DA" at the beginning of the frame and add the 4 bytes CRC at the end. The most time consuming problem when you create a TCP/IP stack is the CRC calculation. The xapp807 also uses the uIP TCP/IP stack that gives you a lot of limits. for example (if I remember) to save memory the SW buffer for TX and RX is the same. Another limitation is: TCP uses a sequence number to check that the data transmitted are received (on the far end). uIP use a SW state machine that checks that the TCP packet has arrived before send the next one, this SW machine is quite simple, it does work but is very slow. So, the answer to your question is To increase the bandwith you need a TCP/IP stack in HDL that creates the TCP/IP stack for you. At moment I'm currently designing a TCP/IP stack in HDL, in my case the application is a VOIP application, to do testing RFC2544 type at a 1Gbps. good luck, FrancescoArticle: 91462
BGA packages are FAR easier to deal with in automated reflow for a number of reasons. BGAs are also the smallest footprint/connection technology around, which is important to a lot of people. Another thread was noting that to get high levels of logic usually entails getting a lot of pins as well. I understand the desire for non-BGA versions (There's been a number of times I wished for it), but the commercial market probably won't sustain it in very high pin count packages. Cheers PeteSArticle: 91463
Hi all. I'm using a Virtex2 fpga which uses a lot of BRAMs. The design modifies the content of these BRAMs during elaboration. Is it possible to dynamically readback the BRAMs contents in a text file using JTAG? I've read the Xilinx documentation (impact) but I can't find a simple and fast solution. Can anybody help me? Thanks.Article: 91464
Hello Everyone, I am working on designing a digital modulator that will implement QAM on FPGA. The FPGA will be programmed in VHDL to modulate an input signal(maybefrom a function generator) A D/A converter will convert the digital signal to an analog one that canbe transmitted. Anyway, what I need now is algorithm and/or VHDL code that will carry out the QAM on FPGA. Any help is greatly appreciated AnthonyArticle: 91465
<giohdl@netscape.net> schrieb im Newsbeitrag news:1131375704.818715.280200@g43g2000cwa.googlegroups.com... > Hi all. > I'm using a Virtex2 fpga which uses a lot of BRAMs. > The design modifies the content of these BRAMs during elaboration. > Is it possible to dynamically readback the BRAMs contents in a text > file using JTAG? > I've read the Xilinx documentation (impact) but I can't find a simple > and fast solution. > Can anybody help me? > Thanks. > yes. you can help yourself by implementing the readback yourself. its doable just read the documentation - the location of the bram bits can be obtained from .LL file there is no tool yet available for this purpose. I have done some research with Spartan 3 readback, but nothing yet to be released maybe some day... anttiArticle: 91466
my project leader wants me to fit the elements of Fast Fourier Transfer including Memory to VirtexII pro board.. to start with he has asked me to map kernel element of FFT and try to Map it on VIRTEX Pro Board........How will i start from the scratch. I am new in FFT... any help will be highly appreciated thanks in advance AjArticle: 91467
Hi Adam, Thank you for your confirmatory information. WengArticle: 91468
I believe the Xilinx CoreGen tool already has a fixed-point parameterizible FFT core. Do you need floating-point for some reason? StephenArticle: 91469
>for ceramic packages i bet the times are over forever. What are military/space people using these days? (I thought that was the reason for ceramic packages in the old days.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 91470
Tibo wrote: > I'm using a PPC405 on a Virtex2 pro. I try to allocate memory > with malloc() function. It compiles without any problem but malloc > returns NULL => no memory is allocated. I set the heap size at 0x0800 in > docm. I set need_xil_malloc to false since xil_malloc seems to be used > only for MicroBlaze. > > ISE 7.1 / EDK 7.1 / SDK with no kernel Are you using a custom linker script? The STACK_SIZE and HEAP_SIZE variables are only used by the linker script. If you add --verbose to the -Wl linker options (Applications/Compiler Options/Advanced) the linker script will be output when you compile. This is also a good way to get the default linker script to read and modify. If your memory space is contiguous, (ie. it just has a start address, followed by text, followed by data, followed by bss) you should probably just be using the default linker script. If you need to use a custom linker script you need to read the default linker script to see what it does with HEAP_SIZE, and modify your custom linker script. Alan Nishioka alan@nishioka.comArticle: 91471
How much memory are you trying to allocate? 0x800 is only 2KB. Instead of using heap that small it might be better to allocate static data structures anyway. - Peter Tibo wrote: > hi, > > I'm using a PPC405 on a Virtex2 pro. I try to allocate memory > with malloc() function. It compiles without any problem but malloc > returns NULL => no memory is allocated. I set the heap size at 0x0800 in > docm. I set need_xil_malloc to false since xil_malloc seems to be used > only for MicroBlaze. > > What's wrong ? > > Thanks for answer. > > Tibo > > ISE 7.1 / EDK 7.1 / SDK with no kernelArticle: 91472
OK, here's an example from a few months back. It's a functional block
that can carry out either an FFT, an IFFT or a complex multiply. The
ensemble makes a pulse compressor. The tool has changed a little since
then, so I wouldn't write it quite like this again. For example, there
was a problem with the % operator back then. Plus, now that I know a
little better what I'm doing, I'd work my index variables differently.
I'd also make it all one loop, so as to better exploit the pipelining.
I maybe add about 100log2(SIZE) cycles by not having it as one loop. I
seem to remember this compiled to around 16000 slices of an X2CV6000,
and I could clock it at 120MHz (slightly more than ISE said, but you
can get away with these sort of things in the lab).
#define FFT_FORWARD -1
#define FFT_BACKWARD 1
#define CMPLX_MULT 2
#define SIZE 4096
#define 2xSIZE 8192
void PC4096Opt(IEEE754 realA_result[SIZE],
IEEE754 imagA_result[SIZE],
IEEE754 realB[SIZE],
IEEE754 imagB[SIZE],
IEEE754 Root_u1[2xSIZE],
IEEE754 Root_u2[2xSIZE],
int shuffle[SIZE],
int nn,
int m,
char mode,
IEEE754 scale){
int toggle;
float c1,c2,scaleLocal,t1,t2,u1,u2,xi1,xi,xIn,yi1,yi,yIn,
xA[SIZE],
yA[SIZE],
xB[SIZE],
yB[SIZE];
int w,z;
int i,j,i1,l,l1,l2,count,index,offset,shuff;
if ( (mode == FFT_FORWARD) || (mode == FFT_BACKWARD) ){
if (mode == FFT_FORWARD) offset = 0;
else offset = nn;
scaleLocal = (float) scale;
for (i = 0; i < nn; i++)
{
shuff = shuffle[i];
xIn = (float)realA_result[shuff];
xA[i] = xIn;
yIn = (float)imagA_result[shuff];
yA[i] = yIn;
}
// Compute the FFT
c1 = -1.0;
c2 = 0.0;
l2 = 1;
count = offset;
toggle = 0;
for (l=0;l<m;l++) {
l1 = l2;
l2 <<= 1;
for (j=0;j<(nn>>1);j++) {
// Pipelined Inner Loop
index = count + (j>>((m-l)-1));
u1 = (float) Root_u1[index];
u2 = (float) Root_u2[index];
w = l2*j;
z = w / (nn-1);
i = w - (nn-1) * z;
// Really, should be: i = (l2*j) % (nn-1)
i1 = i + l1;
if (toggle == 0)
{
xi1 = xA[i1];
xi = xA[i];
yi1 = yA[i1];
yi = yA[i];
t1 = u1 * xi1 - u2 * yi1;
t2 = u1 * yi1 + u2 * xi1;
xB[i1] = xi - t1;
yB[i1] = yi - t2;
xB[i] = xi + t1;
yB[i] = yi + t2;
}
else
{
xi1 = xB[i1];
xi = xB[i];
yi1 = yB[i1];
yi = yB[i];
t1 = u1 * xi1 - u2 * yi1;
t2 = u1 * yi1 + u2 * xi1;
xA[i1] = xi - t1;
yA[i1] = yi - t2;
xA[i] = xi + t1;
yA[i] = yi + t2;
}
}
count = (l2 - 1) + offset;
toggle = toggle ^ 1;
}
// Scaling for forward transform
for (i=0;i<nn;i++) {
if (toggle == 0)
{
realA_result[i] = (IEEE754) ( scaleLocal * xA[i]);
imagA_result[i] = (IEEE754) ( scaleLocal * yA[i]);
}
else
{
realA_result[i] = (IEEE754) ( scaleLocal * xB[i]);
imagA_result[i] = (IEEE754) ( scaleLocal * yB[i]);
}
}
}
else if (mode==CMPLX_MULT){
for(i=0; i<nn; i++)
{
xA[i] = (float) realA_result[i];
yA[i] = (float) imagA_result[i];
xB[i] = (float) realB[i];
yB[i] = (float) imagB[i];
}
for(i=0; i<nn; i++)
{
realA_result[i] = (IEEE754) ( (xA[i]*xB[i]) - (yA[i]*yB[i]) );
imagA_result[i] = (IEEE754) ( (yA[i]*xB[i]) + (xA[i]*yB[i]) );
}
}
}
Article: 91473XAPP807 is not targeted towards high-speed communication. It is intended to be used in control type applications, i.e. in environments where you want to control or monitor a system from within the FPGA by using the smallest amount of FPGA resources possible. The whole web server uses one embedded PowerPC, two Virtex-4 FIFOs, 1 Tri-mode Ethernet MAC, 20 LUTs and 20 FFs. There are two limiting factors in this setup. 1. The data path is only 8 bits wide which matches the data port of the TEMAC. However, with that the PPC needs to read every single byte out of the receive FIFO and send every single byte to the transmit FIFO. By changing the design and adding a little bit more logic the data path can be widened to 32 bits reducing the read/write overhead by a factor four. 2. The FIFOs are kept small. There is one 2KB FIFO each for receive and transmit. The software is written as a single control loop, i.e. one Ethernet Frame at a time. With that, there is receive FIFO overflow at higher transfer rates. Again, with some additional resources the FIFO depth can be enlarged and performance improved. The design has intentionally be kept small and simple but still versatile. While it connects to 10/100/1000 Mpbs networks to fulfill its purpose of monitoring and control through a web server it does not mean it can sustain data rates at these link speeds. If you are looking for high-speed data transfer over TCP/IP check out XAPP535 and XAPP536. - Peter yusufilker@gmail.com wrote: > Hi, > I take a look at xapp807-Minimal Footprint Tri-Mode Ethernet MAC > Processing Engine. > Performance test results are at Table 5 of the document. > > What i understand from the table TEMAC works at 90mbps.(max speed) > it is supposed to work at least 990mbps, isn't it? > Where is the bottleneck , TEMAC , ultracontroller, FIFOs ? > How can we improve performance? > > thanks, > > yusuf >Article: 91474
Is it part of EDIF 2 0 0? A later version? I searched the 2 0 0 BNF on the EDIF website and didn't find it. Thanks!
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z