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thanks for the information, just planning on making a pcb with a spartan3 on it (my first own pcb) ... kind regards, Y "Austin Lesea" <austin@xilinx.com> wrote in message news:cnig6f$qn43@cliff.xsj.xilinx.com... > All, > > A separate power supply for Vccaux which powers the DCM delay lines, IO > predrivers, and some bias circuits is a good idea to reduce system jitter. > > Switching regulators are just fine to use in this application. As long > as there is no more than a 10 mV droop in a 1 ms period (that would be a > really slow switcher -- 1 KHz????). Variations of hundreds of mV at a > fast rate are smoothed out by the DCM's filtering (typical of a > switcher). It is a sudden droop followed by a slow recovery that > affects the DCM, as it can not track fast enough to correct for the push > out in delay of the delay lines. This primarily affects the falling > edge of the clock coming out, and the Clock 2X output, and Clock DV > output (which all use falling edges to synthesize their signals). > > Austin > (who was on the DCM design team for V2, V2P, S3, and V4, and did the > subsequent verification and characterization) > > Sylvain Munaut wrote: > > Hello, > > > > > > I'm wondering if there is any advantage on using a separate regulator for > > the Vccaux. > > > > I already have 2.5V generated on the board by a switching regulator for > > the multiple DDR chips and for some Vccio of the spartan 3. Now, with the > > new TI regulator that has 3 regulators in a chip, I can have a separate LDO > > to power just the Vccaux portion. Is it useful to have it separate ? > > > > > > Thanks, > > > > SylvainArticle: 75951
ksy <helloone@kornet.net> wrote: : Hello All, : Is it possible to use spartan3 for 5V PCI interface? : I seems that there is no problem to use for 3.3V PCI interface. Learn about level-limiting busswitches, like the SN74CBTD3861. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 75952
Hi all, I'm new to FPGA and CPLD. Had just started learning VHDL, I'm keen to implement my design on real Xilinx FPGA. Buying a professional development board is really a costly affair, so I'm interested to build my own FPGA board for learning purpose! Can anybody provide please provide me some help, where should I start or suggest some pointer? All I know about FPGA board is; FPGA board is similar to microcontroller board, and you have to download the bits into it. And you have download cable for this purpose, whose schematic is available at Xilinx's site. And finally which FPGA should I select? It should be SRAM, so I can reprogram it again and again, and should be cheap though. Thanks in advanceArticle: 75953
> I'm new to FPGA and CPLD. Had just started learning VHDL, I'm keen to > implement my design on real Xilinx FPGA. Buying a professional > development board is really a costly affair, so I'm interested to > build my own FPGA board for learning purpose! > > Can anybody provide please provide me some help, where should I start > or suggest some pointer? > > All I know about FPGA board is; FPGA board is similar to > microcontroller board, and you have to download the bits into it. And > you have download cable for this purpose, whose schematic is available > at Xilinx's site. > You can get started with an FPGA board that is under GPL: http://www.opencores.org/projects.cgi/web/acxbrd/overview Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 75954
"Jack// ani" <nospam4u_jack@yahoo.com> wrote in message news:86040da6.0411200551.6609a567@posting.google.com... > Hi all, > > I'm new to FPGA and CPLD. Had just started learning VHDL, I'm keen to > implement my design on real Xilinx FPGA. Buying a professional > development board is really a costly affair, so I'm interested to > build my own FPGA board for learning purpose! http://xilinx.openchip.org/proto/ easy! 2M Gates FPGA platform for $49, cant go lower than that! :) > Can anybody provide please provide me some help, where should I start > or suggest some pointer? there are some DIY FPGA boards with all manufacturing files (gerber) but doing a single proto is more costly than buying a board. > All I know about FPGA board is; FPGA board is similar to > microcontroller board, and you have to download the bits into it. And > you have download cable for this purpose, whose schematic is available > at Xilinx's site. Yes and No. Microcontrollers usually need to be programmed with object code for some the microcontroller. FPGA needs to be programmed to be anything, this can be single wire or and gate or microcontroller. once you have some microcontroller in the FPGA you can program the controller with proper object code. in many cases 4 wires to LPT port is sufficent to program an FPGA > And finally which FPGA should I select? It should be SRAM, so I can > reprogram it again and again, and should be cheap though. http://www.xilinx.com/store/electronica2004 there is special offer for 2 boards for $99 if you need more than that, the wait for the Xilinx S3-1500 low cost to be announced, it has more goodies, if you really want todo it yourself, try ebay shopping to get some FPGA for very cheap, attach power supply and jtag header, but the time/effort spent doesnt actually justify that in most cases. > Thanks in advance Antti http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&rd=1&item=3854143050Article: 75955
Crimson_M wrote:
> Does anyone have any experience using Xilinx System Generator? I'm
> curious as to how it's designs stack up against custom RTL for FPGAs.
> Any metrics would be especially helpful. I am debating using this tool
> for some digital receiver processing, so it would be creating complex
> FIR filters, amplitude and phase computation, differentiator, etc.
> from my Matlab code.
The mathworks part for simulation and hdl code generation
is available by itself.
http://www.mathworks.com/products/filterhdl/description1.html
I saw an impressive demo but have not used it.
Don't know if System Generator includes it all.
-- Mike Treseler
Article: 75956"bassos" <bassos@bassos.it> wrote: >you know nucleus RTOS? Yes. >how much money? It depends. The vendor was of no help with that? >i wold like load on microblaze softprocessor....you that what you say? The MicroBlaze is supported. Enjoy. -- Dan HenryArticle: 75957
Hi Austin Obviously there is more margin if you're not pushing the transceiver so hard, and being in the IC business I always take "real-soon-now" with a large pinch of salt. But in the timescales we're looking at it seems that there will be solutions from both the biggest FPGA vendors, which always helps when talking to customers who might exclusively use one or the other...:-) Cheers Ian Austin Lesea wrote: > Ian, > > There is a definite advantage to using a transceiver designed to work at > 10 Gbs at 6.25 Gbs -- there is a lot of margin! > > Using a 6.25 Gbs transceiver at 6.25 Gbs means that every one of them > has to be just perfect, and pass the production BER test. We are in > production. At 10 Gbs. > > And, you can see (and get delivery of) the Pro-X transceivers (today at > the many RocketLab(tm) demo sites we have around the world). > > No "will", "more details under NDA", or any of that. Just product, > working, on the shelf, shipping NOW. > > Austin > > Ian Dedic wrote: > >> Thanks Dave -- it sounds like all our views agree here (see other >> mails in thread) that 5-6Gb/s as a next step avoids the issues which >> become difficult at 10-12Gb/s. Also given the number of channels >> available (from Altera and Xilinx) this will meet our requirement (up >> to about 100Gb/s total throughput). >> >> IanArticle: 75958
"Jack// ani" <nospam4u_jack@yahoo.com> wrote in message news:86040da6.0411200551.6609a567@posting.google.com... > Hi all, > > I'm new to FPGA and CPLD. Had just started learning VHDL, I'm keen to > implement my design on real Xilinx FPGA. Buying a professional > development board is really a costly affair, so I'm interested to > build my own FPGA board for learning purpose! > > Can anybody provide please provide me some help, where should I start > or suggest some pointer? > > All I know about FPGA board is; FPGA board is similar to > microcontroller board, and you have to download the bits into it. And > you have download cable for this purpose, whose schematic is available > at Xilinx's site. > > And finally which FPGA should I select? It should be SRAM, so I can > reprogram it again and again, and should be cheap though. Xilinx has a $99 kit that is ideal for your purposes. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_heller http://www.kasamba.com/viewExpert.asp?conMemID=105725&Catid=1111&banID=2100Article: 75959
Thanks for all your suggestions! I'm using EDK 6.2i. so I have to modify the linker script manually. Best, Yongjie On Fri, 19 Nov 2004 09:56:53 -0800 Amit Kasat <Amit.Kasat@Xlnx.com> wrote: > Yongjie, > What EDK release are you using. The latest EDK 6.3 has a graphical > linker script generation tool that allows you specify where to put > various sections of your program into internal or external memories > present in your system. > > Amit. > > Yongjie Liu wrote: > > >Hi, > > > >I would like to run my program (too big) from external memory. I don't > >know how to configure my project in Xilinx Platform Studio to complie it > >correctly. What parameter should I modify or is there any configureation > >file I should creat? > > > >Any suggestion or help is greatly appreiciated! > > > >Thanks > >Yongjie > > > > -- Mega <mega_bits@hotmail.com>Article: 75960
Hi,
I'm trying to read files (i.e. JPEG file) from the compactflash card on
the vertex II multimedia board. I know I have to use the sysace
controller and its library. I use the following code to conplie:
#include "xparameters.h"
#include "xutil.h"
#include "sysace_stdio.h"
char *Filename = "winter.jpg";
int main (void) {
FILE *fp;
DWORD X_image, Y_image;
BYTE *our_image_buffer;
printf("starting....\r\n");
if ((fp = fopen(Filename, "r")) == NULL) {
printf("\r\nCan't open file: %s \r\n", Filename);
return 0;
}
return 0;
}
Here is my MHS for the sysace driver:
BEGIN opb_sysace
PARAMETER INSTANCE = system_ace_compactflash
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x81000000
PARAMETER C_HIGHADDR = 0x81FFFFFF
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT SysACE_MPA = MPA
PORT SysACE_CLK = sysace_clk
PORT SysACE_MPD = MPD
END
I can complie the above code but the program freezes when I download
bitstream to the borad and run it through XMD debugger. Would you please
take a look at my code to see if it's correct? I have no experience
using the sysace driver to read files. Also, let me know the right
configuration for the port connection of sysace core and the right way
using C to read file.
Thanks a lot.
Yongjie
Article: 75961On 20 Nov 2004 05:51:34 -0800, nospam4u_jack@yahoo.com (Jack// ani) wrote: >Hi all, > >I'm new to FPGA and CPLD. Had just started learning VHDL, I'm keen to >implement my design on real Xilinx FPGA. Buying a professional >development board is really a costly affair, so I'm interested to >build my own FPGA board for learning purpose! > >Can anybody provide please provide me some help, where should I start >or suggest some pointer? Here's a pointer: http://www.fpga-faq.com/FPGA_Boards.shtml Given that you are just getting started, I think you would be best off buying your first board, rather than getting distracted on building a board (which given your cost sensitivity, is going to be more expensive that buying one of the low cost boards). Most of the cheap boards use chips that are supported by the free software from the FPGA vendors. I would recommend you look at something with a Xilinx Spartan-2 or Spartan-3 chip. Philip =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COMArticle: 75962
"Yongjie Liu" <mega_bits@hotmail.com> wrote in message news:20041120104948.691F.MEGA_BITS@hotmail.com... > Hi, > > I'm trying to read files (i.e. JPEG file) from the compactflash card on > the vertex II multimedia board. I know I have to use the sysace > controller and its library. I use the following code to conplie: [snip] > Here is my MHS for the sysace driver: > > BEGIN opb_sysace > PARAMETER INSTANCE = system_ace_compactflash > PARAMETER HW_VER = 1.00.b > PARAMETER C_BASEADDR = 0x81000000 > PARAMETER C_HIGHADDR = 0x81FFFFFF > BUS_INTERFACE SOPB = mb_opb > PORT OPB_Clk = sys_clk_s > PORT SysACE_MPA = MPA > PORT SysACE_CLK = sysace_clk > PORT SysACE_MPD = MPD > END connecting MPA and MPD is not enough, you have no connection to WEN and CEN as example, so its natural that everything freezes!! try some known good SYSACE example program first to verify that sysace works, AFTER that is OK move on trying out fat file system on sysace. AnttiArticle: 75963
Swamy, Check the size of the software code to make sure that it will fit in the BRAM space you have allocated. Shalin- swamy wrote: > I am getting the following error message while building a simple > system consisting of bram, ppc, uart, plb bus, opb bus, plb2opb > bridge. I am trying to use hardware simulation to verify my design. > Any help or pointers is greatly appreciated. > > thanks > swamy > > Initializing Memory... > Checking ELFs associated with PPC405 instance ppc405_0 for overlap... > > > Analyzing file hello/executable.elf... > ERROR:MDT - Elf file hello/executable.elf does not reside completely > within BRAM > > memory of processor ppc405_0. > ERROR:MDT - Uncheck the `Mark for BRAM Initialization` setting on the > software > application generating this ELF. > INFO:MDT - This ELF file should be downloaded using a debugger, a > bootloader or > an ACE file. > make: *** [implementation/download.bit] Error 1 > Done.Article: 75964
vadim wrote:
> Is it possible to create a parametarizable Megafunction of my own
> designs
> in Quartus ? I would like to be able to add my own designs into
> MegWizard Manager that can be instatiated within *.BDF files as
> graphic entities with
> configurable properties (similar to the LPM_XXX functions).
Step one is to learn vhdl or verilog.
Once you have working synthesis code it is
easy to make a quartus graphic symbol for it.
It is also easy to add generic options in the code.
However, if the top ports change, you have to
remake the symbol.
-- Mike Treseler
Article: 75965
I am doing some test with the Spartan III multipliers. I have tried
the following simple code:
entity mac_ex is
generic (width: integer := 18) ;
port ( a,b : in std_logic_vector (width-1 downto 0);
final_res: out std_logic_vector((width*2)-1 downto
0));
end mac_ex;
architecture behave of mac_ex is
begin
final_res <= a * b;
end;
The map report states that the above code will be implemented in 3
(three) 18x18 multipliers when 'width' is equal to 18. Does any of you
have an explanation for needing 3 18x18 multipliers?.
Note: when 'width' is equal to 17, just one 18x18 multiplier is
needed. I am using the WebPack 6.2.03 version
thanks,
cris
Article: 75966Hi Antti, Thanks for your help! Do you have examples for sysace? I find everywhere on xilinx website but got nothing useful. If you know the place I could find it, please let me knwo. Also, I will try to connect WEN and CEN. Best, Yongjie On Sat, 20 Nov 2004 19:50:55 +0100 "Antti Lukats" <antti@case2000.com> wrote: > "Yongjie Liu" <mega_bits@hotmail.com> wrote in message > news:20041120104948.691F.MEGA_BITS@hotmail.com... > > Hi, > > > > I'm trying to read files (i.e. JPEG file) from the compactflash card on > > the vertex II multimedia board. I know I have to use the sysace > > controller and its library. I use the following code to conplie: > [snip] > > > Here is my MHS for the sysace driver: > > > > BEGIN opb_sysace > > PARAMETER INSTANCE = system_ace_compactflash > > PARAMETER HW_VER = 1.00.b > > PARAMETER C_BASEADDR = 0x81000000 > > PARAMETER C_HIGHADDR = 0x81FFFFFF > > BUS_INTERFACE SOPB = mb_opb > > PORT OPB_Clk = sys_clk_s > > PORT SysACE_MPA = MPA > > PORT SysACE_CLK = sysace_clk > > PORT SysACE_MPD = MPD > > END > > connecting MPA and MPD is not enough, you have no connection to WEN and CEN > as example, so its natural that everything freezes!! > > try some known good SYSACE example program first to verify that sysace > works, AFTER that is OK move on trying out fat file system on sysace. > > Antti > -- Mega <mega_bits@hotmail.com>Article: 75967
cristian wrote: > I am doing some test with the Spartan III multipliers. I have tried > the following simple code: > > entity mac_ex is > generic (width: integer := 18) ; > port ( a,b : in std_logic_vector (width-1 downto 0); > final_res: out std_logic_vector((width*2)-1 downto > 0)); > > end mac_ex; > > architecture behave of mac_ex is > begin > > final_res <= a * b; > > end; > > The map report states that the above code will be implemented in 3 > (three) 18x18 multipliers when 'width' is equal to 18. Does any of you > have an explanation for needing 3 18x18 multipliers?. > > Note: when 'width' is equal to 17, just one 18x18 multiplier is > needed. I am using the WebPack 6.2.03 version Probably because it considers it a unsigned multiplication. The 18x18 are only for signed numbers. SylvainArticle: 75968
I found the appnote for microblaze (and src), but I can't find the anything for ppc. The xilprofile directory in edk does not compile for ppc platform. Has anyone tried profiler in the ppc? Any trick? If I just compile with -pg, I have undefine reference to the _mcount(). Since xmd does collect profile info from ppc hw, there should be some code for xilprofile for ppc platform, right? Thanks -TonyArticle: 75969
hello all, it is not a question concerning FPGA but I could get the answer here: from old devices that went to trash I get two EPM7032VLC44-15 and I would like to reuse them to build my own very low cost first protoboard for developping wih VHDL. It sounds like ALtera CPLD but I do not find the meaning of VLC, is it a low voltage version (3.3V)? Is it a REprogrammable device? Thanks by avance for your help.Article: 75970
Got a strange problem here. When I power up, the platform PROM starts up the Spartan 3 OK and a Cypress FX2 (USB2). However when I shoot another program down through the JTAG cable, there is a slight dip in the FX2 reset pin, which I connected to a Spartan IO, from about 3.3V to 2.2V. This slight dip in voltage seems to hose the FX2 chip and its oscillator will not come back on. I thought that the IOs during the programming cycle of the Spartan 3s were high impedance and I shouldn't see such a dip. In retrospect, I should have wired the Cypress FX2 Reset pin to an RC network like the data sheet says. But instead I wanted to be able to start the FX2 after things were stable with the Spartan 3. Another issue is why the FX2 won't recover, even if I cycle the reset pin, but that question I will direct to the Cypress folks. Any help here would be appreciated. Thanks in advance, b r a d @ a i v i s i o n . c o mArticle: 75971
What's the deal with 18 by 18 multipliers? Sheesh, is there anything more useful they could have dropped into those silicon ares?Article: 75972
On 20 Nov 2004 13:08:48 -0800, cas7406@yahoo.com (cristian) wrote: >I am doing some test with the Spartan III multipliers. I have tried >the following simple code: > >entity mac_ex is > generic (width: integer := 18) ; > port ( a,b : in std_logic_vector (width-1 downto 0); > final_res: out std_logic_vector((width*2)-1 downto >0)); > >end mac_ex; > >architecture behave of mac_ex is >begin > >final_res <= a * b; > >end; > >The map report states that the above code will be implemented in 3 >(three) 18x18 multipliers when 'width' is equal to 18. Does any of you >have an explanation for needing 3 18x18 multipliers?. > >Note: when 'width' is equal to 17, just one 18x18 multiplier is >needed. I am using the WebPack 6.2.03 version > >thanks, > >cris The 18-by-18 multiplier is two's-complement. You can use it for unsigned multiplication by setting the MSB of the multiplier and multiplicand inputs to 0. This works as long as the unsigned numbers are 17 bits or less. Beyond that, it's going to cost extra. Bob Perlman Cambrian Design WorksArticle: 75973
Only block ram can be initialized during an fpga download. If you are trying to run from external ram or cache, you have to download manually with a debugger or boot loader (and uncheck Mark BRAM for initialization, to continue implementation). If you think you are running entirely from block ram, this probably means your linker script is bad (and is linking your program into memory that is not block ram). Alan Nishioka alann@accom.com swamydp@yahoo.com (swamy) wrote in message news:<f43b3388.0411191512.70f321d9@posting.google.com>... > I am getting the following error message while building a simple > system consisting of bram, ppc, uart, plb bus, opb bus, plb2opb > bridge. I am trying to use hardware simulation to verify my design. > Any help or pointers is greatly appreciated. > > thanks > swamy > > Initializing Memory... > Checking ELFs associated with PPC405 instance ppc405_0 for overlap... > > > Analyzing file hello/executable.elf... > ERROR:MDT - Elf file hello/executable.elf does not reside completely > within BRAM > > memory of processor ppc405_0. > ERROR:MDT - Uncheck the `Mark for BRAM Initialization` setting on the > software > application generating this ELF. > INFO:MDT - This ELF file should be downloaded using a debugger, a > bootloader or > an ACE file. > make: *** [implementation/download.bit] Error 1 > Done.Article: 75974
"Fab" <moi@chezmoi.fr> wrote in message news:419fe5b9$0$32312$636a15ce@news.free.fr... > hello all, > > it is not a question concerning FPGA but I could get the answer here: > > from old devices that went to trash I get two EPM7032VLC44-15 and I would > like to reuse them to build my own very low cost first protoboard for > developping wih VHDL. > > It sounds like ALtera CPLD but I do not find the meaning of VLC, is it a > low voltage version (3.3V)? > > Is it a REprogrammable device? It's an obsolete CPLD, you should be able to find data for it on the Altera web site. However, it doesn't seem to be supported by the current Altera development software. You's be better off buying some more up-to-date devices from the MAX 7000 family. They aren't expensive. Leon
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z