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I would not even consider using a high-speed I/O part unless I see it working for real on a board. And with some characterization data to back it up. That's because engineers have been burned too many times for claims of serial I/O greatness only to be left without working silicon when it comes times for the rubber to hit the road. Who cares about seeing info under NDA? 6.25 Gbps and above I/O is too critical to count on some powerpoint presentation that claims great I/O performance. You can get a Xilinx V2 Pro X today and verify for yourself if it meets your needs in the lab. Real silicon operating at 10 Gbps on a real board. Case closed with no decision for me unless I can see a Stratix II running on a real board. With Xilinx you don't even need to have all the great equipment yourself. You can go to a rocket lab and see for yourself. Also, I would much prefer to run a 10 Gbps device at 6.25 than a 6.25 Gbps device at 6.25 Gbps. I'll take all the extra margin any day. Ian & Hilda Dedic <news.nospam@dedics.co.uk> wrote in message news:<3099tbF2te2tsU1@uni-berlin.de>... > Hi Austin > > Obviously there is more margin if you're not pushing the transceiver so > hard, and being in the IC business I always take "real-soon-now" with a > large pinch of salt. > > But in the timescales we're looking at it seems that there will be > solutions from both the biggest FPGA vendors, which always helps when > talking to customers who might exclusively use one or the other...:-) > > Cheers > > Ian > > Austin Lesea wrote: > > > Ian, > > > > There is a definite advantage to using a transceiver designed to work at > > 10 Gbs at 6.25 Gbs -- there is a lot of margin! > > > > Using a 6.25 Gbs transceiver at 6.25 Gbs means that every one of them > > has to be just perfect, and pass the production BER test. We are in > > production. At 10 Gbs. > > > > And, you can see (and get delivery of) the Pro-X transceivers (today at > > the many RocketLab(tm) demo sites we have around the world). > > > > No "will", "more details under NDA", or any of that. Just product, > > working, on the shelf, shipping NOW. > > > > Austin > > > > Ian Dedic wrote: > > > >> Thanks Dave -- it sounds like all our views agree here (see other > >> mails in thread) that 5-6Gb/s as a next step avoids the issues which > >> become difficult at 10-12Gb/s. Also given the number of channels > >> available (from Altera and Xilinx) this will meet our requirement (up > >> to about 100Gb/s total throughput). > >> > >> IanArticle: 76026
javaguy11111@gmail.com (DB) wrote in news:85472d99.0411220559.531d4b6b@posting.google.com: > I have seen a few low cost($100-$200) fpga boards with 400k Spartan > 3's, but nothing with 1million gates yet. I would think with the > supposedly low price of the Spartan 3 that such boards would have made > an appearance by now. Does anyone know if such a board exists yet. We have a $199 1M-gate Spartan3 board at http://www.xess.com/prod035.php3. -- ---------------------------------------------------------------- Dr. Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 76027
"Chris Stratton" <cs_posting@hotmail.com> wrote in message news:ae2ff5ca.0411221453.1b082f07@posting.google.com... > "Bob" <nimby1_notspamm_@earthlink.net> wrote in message news:<Gwcod.8180$pK6.1111@newsread2.news.atl.earthlink.net>... > > Just use the series resistor to limit the 8051->S3 high-level current. > > > > In the S3->8051 direction, you don't need anything since LVTTL (3.3V supply) > > has exactly the same logic thresholds as TTL (5V supply). > > That should work with most logic familiers - if he has to talk to 5v > devices that really need a higher input voltage, he should be able to > use widely available 74-whatever-xx DIP package buffers or inverters > in a 3.3v volt-compatible logic family as stand-in level translators. > > Of course, why not simply move the "8051" into the FPGA?? > > Chris It looks like his 8051 is not (LV)TTL compatible. He will need some sort of translation. You are right, though. If I were he, I would stuff that uP into the FPGA. I looked at opencores.org http://www.opencores.org/browse.cgi/by_category but didn't see any 8051's. Maybe he can some other processor core. BobArticle: 76028
Hamish Moffatt wrote:
> Err.. That's functionally correct, but how does it help to get Synplify
> to use the reset inputs for synchronous reset?
It doesn't.
My point was to demonstrate a way to
integrate an external asynchronous reset
with your existing code in a vendor portable way.
Is this a question of a design not fitting
or unease about wasting gates?
-- Mike Treseler
Article: 76029Hello, I installed EDK 6.3 on a Win XP Pro machine (after un-installing 6.2.2). When I attempt to execute any of the executables in bin/nt, like xps.exe, xmd.exe, etc, Windows reports: "The procedure entry point fc_auth_data could not be located in the dynamic link library libSecurity.dll". How do I fix this error? ISE 6.3 (SP1) has already been installed and functions correctly. The dll file, libSecurity.dll, is located in the bin directory in the ISE installation. Thank you, NNArticle: 76030
On 20 Nov 2004, T Lee wrote: > I found the appnote for microblaze (and src), but I can't > find the anything for ppc. > > The xilprofile directory in edk does not compile for ppc platform. > > Has anyone tried profiler in the ppc? Any trick? > > If I just compile with -pg, I have undefine reference to the _mcount(). > Since xmd does collect profile info from ppc hw, there should be > some code for xilprofile for ppc platform, right? > > > > > Thanks > > -Tony > Hi Tony, I have pasted a link to an application note that describes how to profile the ppc 405 in hardware (Click on xapp 545). If the link doesn't work for whatever reason, you can google "xapp545". Good luck. http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1209874&iLanguageID=1&showDesc=false nnArticle: 76031
nospam4u_jack@yahoo.com (Jack// ani) wrote in message news:<86040da6.0411220039.ceb09f3@posting.google.com>... > "Leon Heller" <leon_heller@hotmail.com> wrote in message news:<419f7a75$0$2292$cc9e4d1f@news-text.dial.pipex.com>... Hey Leon where you, I need your help!! I have one more query According to my text book, if your design needs large numbers of flip-flops you should so for a FPGA instead of CPLD, but you can use CPLD for lesser flip-flops demanding design. So I want to know about their relative figures, also can I design 4bit counters, ripple counter, ring counter, Johnson counter etc, on his CPLD? Thanks againArticle: 76032
Hello guys, I have a ISA-card with a xilinx xc3030 on it that i understand is something you know what it is.. http://hem.bredband.net/b222911/thecard.jpg I looked in all my drawers and found this one that was given to me a couple of years ago, does anyone know what it is, and what can be done with it? If sellable, what is reasonable to ask for this card? Thanks in advance! :) //LarsArticle: 76033
Hi Lars, last winter I also found two boards with XC3000s on them. What I did with them was to de-populate them and make them into key-holders. Now they are hanging on the wall in my flat and do a proper job. Appart from that, if you want to do any FPGA-things: those things are ancient.... Cheers, Martin Lars Helgeson wrote: > Hello guys, I have a ISA-card with a xilinx xc3030 on it that i > understand is something you know what it is.. > > http://hem.bredband.net/b222911/thecard.jpg > > I looked in all my drawers and found this one that was given to me a > couple of years ago, does anyone know what it is, and what can be done > with it? > > If sellable, what is reasonable to ask for this card? > > Thanks in advance! :) > > //LarsArticle: 76034
Bob <nimby1_notspamm_@earthlink.net> wrote: : It looks like his 8051 is not (LV)TTL compatible. He will need some sort of : translation. : You are right, though. If I were he, I would stuff that uP into the FPGA. I : looked at opencores.org To interface 3.3V CMOS (which is also real TLL levels) to 5 Volt CMOS, use some (X)CT Logic, like 74ACT Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 76035
Hello, are You shure that switching to a 3V3 compatible CPU is not possible??? What other chips are on board??? Are these the real bottlenecks??? My comment: I think replacing a 1,50$ 8051 CPU with an "almost compatible" 8051 soft CPU that would need 20$ of FPGA ressources (and generate lots of trouble and engineering costs) is not preferable for real world designs. Such designs do not help in establishing FPGA´s, they just keep them having the smell of "complex playground and too expensive engineering". For accademic research it may be great to build a bridge out of nuts and bolts only and ignore the existence of steel girders - big fun, but in daily work I often hear: "an FPGA ???, no let´s use a ´XYZ´ CPU (stylish with lots of power (potency) and MHz)" - and that makes selling FPGA designs hard work... with best regards, Peter Seng "Lawrence Kiss" <lkiss80@127.0.0.1:7501> schrieb im Newsbeitrag news:41a1aa5e_1@127.0.0.1... > > I am taking an embedded systems course. We had to buy a parts kit that was > available only from the prof. The semester is coming to a close within 2 > weeks, and everyone is trying to finish their final (open ended) projects. > No time to convert everything that I have been doing all semester to 3.3. > Thanks for the suggestion though. > > "Peter Seng" <NOSPAM@seng.de> wrote: > > > >"Lawrence Kiss" <lkiss80@hotmail.com> schrieb im Newsbeitrag > >news:41a15113$1_1@127.0.0.1... > >> I would like to integrate an 8051 microcontroller to a spartan 3 > >development > >> board. For input port I know I need to add a series resistor. However > >for > >> the output ports, I have read posts and app notes about using the > >> quickswitch product. The only problem is the package that they come in. > >I > >> have been wire wrapping most of my pins thus far and have not found any > >> level shifting solutions that comes in a DIP package (that can be wire > >> wrapped). So here is my question: instead of using the level shifter, > >can > >> I just directly connect my Spartan 3 output port to an input port on my > >8051 > >> and have a pull-up resistor to 5V on the same net? My idea is that for > >low > >> outputs I would just output a low logic level, but for a high output, > I > >> would create the VHDL code to output a high impedance (Z)... Does anyone > >> think this will work, or am I just crazy? > >> > >> Thanks for any suggestions! > >> > >> Larry > >> > >> > >> > >> Posted Via Usenet.com Premium Usenet Newsgroup Services > >> ---------------------------------------------------------- > >> ** SPEED ** RETENTION ** COMPLETION ** ANONYMITY ** > >> ---------------------------------------------------------- > >> http://www.usenet.com > > > > > > > >Why not running the 8051 at 3V3 ??? > >There are lot of 3V3 compatible 8051 MCU´s / CPU´s .... > > > > > >with best regards, > > > >Peter Seng > > > > > >############################# > >SENG digitale Systeme GmbH > >Im Bruckwasen 35 > >D 73037 Goeppingen > >Germany > >tel +7161-75245 > >fax +7161-72965 > >eMail p.seng@seng.de > >net http://www.seng.de > >############################# > > > > > > > > ----== Posted via Newsfeed.Com - Unlimited-Uncensored-Secure Usenet News==---- > http://www.newsfeed.com The #1 Newsgroup Service in the World! >100,000 Newsgroups > ---= 19 East/West-Coast Specialized Servers - Total Privacy via Encryption =---Article: 76036
Peter Seng <NOSPAM@seng.de> wrote: : Hello, : are You shure that switching to a 3V3 compatible CPU is not possible??? : What other chips are on board??? Are these the real bottlenecks??? : My comment: I think replacing a 1,50$ 8051 CPU with an "almost compatible" : 8051 soft CPU that would need 20$ of FPGA ressources (and generate lots of : trouble and engineering costs) is not preferable for real world designs. : Such designs do not help in establishing FPGA?s, they just keep them having : the smell of "complex playground and too expensive engineering". : For accademic research it may be great to build a bridge out of nuts and : bolts only and ignore the existence of steel girders - big fun, but in daily : work I often hear: "an FPGA ???, no let?s use a ?XYZ? CPU (stylish with lots : of power (potency) and MHz)" - and that makes selling FPGA designs hard : work... If you talk about Spartan 3, 20 $ is often the cost of the whole chip, to a soft core inside can't eat up more than those 20 $. Also if the soft core spares you some pins and so your design can live with a TQFP208 agains a FBGA256, this can ease up (engineering) board design and prototyping costs a lot. But otherwise having know working parts on the board is also a good thing! Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 76037
Hello, I'm a student and I am working on my Bachelor Lecture. Our tool is Quartus II, so I have a question. How can I trace a signal of a design, which doesn't "exist" after the Compilation (Post-Compilation)? Unfortunately I didn't find the answer neither on www.altera.com nor in altera documentations. I am very grateful, if somebody can help me. Thanks EmrahArticle: 76038
larshson@home.se (Lars Helgeson) wrote in message news:<ccdfa921.0411222359.56c98182@posting.google.com>... > Hello guys, I have a ISA-card with a xilinx xc3030 on it that i > understand is something you know what it is.. > > http://hem.bredband.net/b222911/thecard.jpg > > I looked in all my drawers and found this one that was given to me a > couple of years ago, does anyone know what it is, and what can be done > with it? > > If sellable, what is reasonable to ask for this card? > > Thanks in advance! :) > > //Lars Type "cio-das801/802" into google, second hit.. http://www.measurementcomputing.com/PDFmanuals/cio-das80x.pdf -LasseArticle: 76039
Do you have SP2 for Wxp installed? Did you uninstalled everything xilinx 6.2 and edk 6.2 with all service packs?Article: 76040
Muthu wrote: > Hi, > How to be part of NASA as a VLSI Design engineer? > > Regards, > Muthu You must be a US citizen first.Article: 76041
larshson@home.se (Lars Helgeson) wrote in message news:<ccdfa921.0411222359.56c98182@posting.google.com>... > Hello guys, I have a ISA-card with a xilinx xc3030 on it that i > understand is something you know what it is.. > > http://hem.bredband.net/b222911/thecard.jpg Did you try google on the obvious part number (DAS-801) ??? http://www.engberg.dk/cbi/cio_das801.htmArticle: 76042
"emrah" <emrah25@gmx.at> wrote in message news:2668dc9b.0411230312.1c6f75a4@posting.google.com... > Hello, > > I'm a student and I am working on my Bachelor Lecture. Our tool is > Quartus II, so I have a question. How can I trace a signal of a > design, which doesn't "exist" after the Compilation > (Post-Compilation)? Unfortunately I > didn't find the answer neither on www.altera.com nor in altera > documentations. > I am very grateful, if somebody can help me. > Thanks > > Emrah There may be a better way but I just made a "dummy" output port and assigned the signal in question to that dummy port. This was only for the simulation stage and I am aware that it could alter the routing for post-fit simulations. In my case, I was only using about 10% of the chip for that particular experiment so I wasn't very worried and so I did not make any comparisons of the fit/placement charts with and without my "dummy" output. Rob YoungArticle: 76043
On 23 Nov 2004 00:26:29 +0000 (GMT), Thomas Womack <twomack@chiark.greenend.org.uk> wrote: >In article <9e825b8b.0411220805.3b0ab84e@posting.google.com>, >cristian <cas7406@yahoo.com> wrote: >>Thanks for your feedbacks. > >>However the following combinations >>are implemented in 3 18x18 multipliers when the operands are 18 bits >>wide. > >I assume synthesis tools are smarter than I am about these things, but >I'd have thought an 18x18 unsigned multiplier was a 17x17 unsigned >multiplier, 35 AND gates, some wire and a three-input 35-bit-wide >adder: > >(2^17a + b) (2^17c + d) = 2^34*a*c + 2^17*(ad+bc) + bd > >where a and c can only take on the value 0 and 1, so you can multiply >by them using an AND gate. You can supply the missing intelligence yourself. Wrap the following up as an entity, and the ugliness of the architecture doesn't matter. You can make your own multiplier, and break it down into 3 separate multiplications yourself, 17x17, 17x1** and 18x1, onto 3 intermediate signals, and sum them yourself. Just a couple of lines of VHDL (e.g. in a clocked process) The tools will still infer three multiplication blocks. HOWEVER by attaching attributes to the internal signals: attribute mult_style: string; attribute mult_style of big_one:signal is "block"; attribute mult_style of little_one:signal is "lut"; you have fine control of multiplier block or gate usage for any multiplier size you care for. Works in Webpack XST, I haven't tried in other tools... Making this a parameterisable n*m multiplier with n,n\m generics is left as an exercise for the reader... ** Yes, use a 17x1 multiplier! The tools are certainly pretty smart about packing multiplication into LUTs when they are told to. I don't know about a n*1 mult, but I couldn't match its performance on a n*2 mult with anything simple. >Does the synthesis do something different if you instantiate N+1 18x18 >unsigned multipliers on a chip with 3N hardware multipliers? No, but the mapper tells you it won't fit! - BrianArticle: 76044
On Mon, 22 Nov 2004 15:23:17 -0800, "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote: >What are the procedures for adding signals to the simulation? I have been >going to the SIGNALS pane, and clicking on add to wave signals in design. >Then, since that seems to give me everything, I start deleting most of them. Select the ones you want in "Signals" before clicking "Add". - BrianArticle: 76045
(my response follows the quoted text) Lars Helgeson wrote: > Hello guys, I have a ISA-card with a xilinx xc3030 on it that i > understand is something you know what it is.. > > http://hem.bredband.net/b222911/thecard.jpg > > I looked in all my drawers and found this one that was given to me a > couple of years ago, does anyone know what it is, and what can be done > with it? > > If sellable, what is reasonable to ask for this card? > > Thanks in advance! :) > > //Lars ---------------------------------------------- A Xilinx XC3030 is an FPGA providing up to 2,000 equivalent logic gates, or 100 configurable logic blocks to be more exact. The XC3000 series FPGAs were never supported by Xilinx ISE development software, so the legacy stuff you can find on their website won't help you. You need Foundation, not ISE Foundation. As an I/O card, it might be worth a little to someone who can find a use for it. As a development card, it isn't worth anything. As a museum piece... wait a while... maybe a long while :-) Dwayne Surdu-MillerArticle: 76046
"salman sheikh" <sheikh@pop500.gsfc.nasa.gov> wrote in message news:cnvg9c$nuh$1@skates.gsfc.nasa.gov... > Muthu wrote: > > Hi, > > How to be part of NASA as a VLSI Design engineer? > > > > Regards, > > Muthu > You must be a US citizen first. Like Verner von Braun. ;-)Article: 76047
Martin Kellermann <Martin.Kellermann@nospam.xilinx.com> wrote in message news:<41A2F1BD.6030103@nospam.xilinx.com>... > Hi Lars, > > last winter I also found two boards with XC3000s on them. What I did > with them was to de-populate them and make them into key-holders. > > Now they are hanging on the wall in my flat and do a proper job. Appart > from that, if you want to do any FPGA-things: those things are ancient.... > > Cheers, > > Martin > > > > Lars Helgeson wrote: > > Hello guys, I have a ISA-card with a xilinx xc3030 on it that i > > understand is something you know what it is.. > > > > http://hem.bredband.net/b222911/thecard.jpg > > > > I looked in all my drawers and found this one that was given to me a > > couple of years ago, does anyone know what it is, and what can be done > > with it? > > > > If sellable, what is reasonable to ask for this card? > > > > Thanks in advance! :) > > > > //Lars haha, I had a XC4010 as key-holder too, but i though it's not lead free so I dont want to keep it anymore. If sellable, what is reasonable to ask for this keyhold? :)Article: 76048
Brad Smallridge wrote: > What are the procedures for adding signals to the simulation? I have been > going to the SIGNALS pane, and clicking on add to wave signals in design. > Then, since that seems to give me everything, I start deleting most of them. > Seems inefficient. Also what does region mean in add signal in region? I > also tried to save dataset, but when I loaded the file back, nothing seemed > to happen. Is this all suppose to be done with the wavedo files? > > b r a d @ a i v i s i o n . c o m > > I think the easiest way is from the command line: add wave -hex top/module1/submodule/signal1 When you add all the signals you want, update your 'wave.do' file and then just execute 'do wave.do' before the start of the next simulation. -KevinArticle: 76049
i've used it a few times and every version of the software is a huge step forward ... because with the first versions you could have a simple flowchart but a huge footprint after synthesis or it made code that at first didn't synthetize but after adding the right option/modifications ran perfectly ... but for the stuff i used it (audio/video processing) it was really impressive, kinda like it ... it had its limitations but i you should try the demo (http://www.xilinx.com/dsp/eval_software.htm), haven't used it in a few months and there have been new releases so i think if those got as much increase in usebility as those i witnessed than you should try it out ... greetz "Crimson_M" <crimson_m@hotmail.com> wrote in message news:9ba2ff64.0411190745.3747dfd5@posting.google.com... > Does anyone have any experience using Xilinx System Generator? I'm > curious as to how it's designs stack up against custom RTL for FPGAs. > Any metrics would be especially helpful. I am debating using this tool > for some digital receiver processing, so it would be creating complex > FIR filters, amplitude and phase computation, differentiator, etc. > from my Matlab code. > > Thanks, > Brandon
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