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Paul Johnson wrote: > On 9 Feb 2006 15:58:10 -0800, "rickman" <spamgoeshere4@yahoo.com> > wrote: > > >You have ignored the real issue. The issue is not whether the async > >design can run faster under typical conditions; we all know it can. > >The issue is how do you make use of that faster speed? The system > >design has to work in the worst case conditions, so you can only use > >the available performance under worse case conditions. > > I think there's an issue here with the definition of "worst-case > conditions". It's not just process/voltage/temperature corners, and > tool would have to build in a safety margin even if it was. But, when > you're designing a static timing analyser, you also have to take into > account random localised on-die variations, and you have to build in > more safety margin just in case. The end result is that when doing > synchronous design your tool gives you a conservative estimate, and > you're stuck with it. If you've got a bad process async design and a > bad-process sync design sitting next to each other in a hot room with > low voltages, then the async design should presumably run faster. "Local" variations can also affect the async processor. That is why the delta between the data and control path delays must be larger than zero. In the end all these effects must be accounted for whether at the chip level or at the system level. > >You can do the same thing with a clocked design. Measure the > >temperature and run the clock faster when the temperature is cooler. > > You can't do that because, I think, you can't get the tools to give > you a graph of max frequency vs. temperature for worst-case process > and voltage. You just get the corner cases. With an async design it > doesn't matter - it just runs as fast as it can. Brings to mind the > gingerbread man. I don't need tools, silicon speed vs. temp and voltage is a well known quantity. Besides, there are little or no tools commercially available for doing async design. I assumed we were not talking about the practicality with today's tools, but were extrapolating to a "perfect" world. But the real issue is what do you do with the excess speed of the async design at room temp, etc? Your design has to meet specific goals over all variables of temp, voltage and process. Ok, FPGA identified one application where it might be acceptable to not meet your timing goals as the box warms up. Personally I don't believe that, since even Cisco designs using requirements and I seriously doubt there is room for uncontrolled variables limiting the performance of their equipment. "Yes, our product will operate at XXX packets per second (as long as you keep it very cool and the voltage regulator is at the high end of its spec and the chip is at the fast end of its spec)." Do they spec equipment that way? Doesn't this make sense? What do you do with the extra MIPs you get *sometimes*.Article: 96776
Hi Zara. Thanks for the answers... >4) What does a bus-split / decoupled address terms stand for ? I don't know. Or at least, I don't recognize the concept under those terms. But I am not native english speaver, it may just be a limited knowledeg of the language. thoses terms are used in the plb bus description regarding the ability to read/write in the same cycle. Regards, Mordehay.Article: 96777
In a project I use the Altera EPM3256ATC144-10. Now I have the necessity to make some changes to the project, but I don't have enough macrocells in the actual devices. Alteras doesn't have a pin-to-pin compatible EPLD with the EPM3256ATC144-10 but with more macrocelles (about +40%). What of you knows a devices that could resolve my problem? Unfortunately I cannot modify the PCB, but I could replace the Altera EPLD with any other CPLD. ThanksArticle: 96778
Hy motty, the way to know what exactly the processor does during the simulation is to use the "mb-objdump" tool as Paul mentioned above. the PC (program counter) register is located under the microblaze0 instance and is called "PC_EXE[31:0]" find it and put it to your sim waves. use the mb-objdump tool to relate the PC values to the actual code (c + assembler). another tip is to compile using the -g option (debug) . I hope it helps, Mordehay.Article: 96779
Unfortunately, I can't think of many options for you, exccept to modify the PCB. The package you picked, 144pin flat pack suppoprts your device and the smaller one. There is one more larger device in the Max3000 family, but it is also in a larger package. If you try to switch to an alternate device, another brand, etc you will also be in a position of having to rework the PCB, so if you are going to have to do that you might as well stay with a device that you know. Your other options, may be optimizations or elimimating some of the logic in the device and moving it into firmware, etc, but trying to gain 40% on a fairly large device is not going to be an easy task.Article: 96780
I downloaded the Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d from Xilinx site. These are the free starter products. In the past I used ISE and ModelSim older versions and all worked. I am not sure what I should do to make these work. I just want simple VHDL and to use Schematics. I dont see any way to tell ISE not to do dual language? Any advice appretiated! "Hans" <hans64@ht-lab.com> wrote in message news:e6YGf.23547$Fy4.22367@newsfe4-win.ntli.net... > Looks like you are using both vlog (verilog) and vcom (vhdl) compiler, > check that you have a dual language license, > > Hans. > www.ht-lab.com > > "mBird" <no@email.com> wrote in message > news:11uo5ck9o574tfa@corp.supernews.com... >>I just downloaded Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d >> I make a simple project, using schematic (one and gate) an dthen make a >> test bench waveform. I then do Simulate Behaviural Model but no matter >> what I do I always get # Error loading design with no other indication of >> erors. In the previous version of ISE and ModelSim it all worked so I am >> not sure what is error? >> Any help greatly appretiared! >> >> The results of from ModelSim: >> # Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl >> # do m.fdo >> # ** Warning: (vlib-34) Library already exists at "work". >> # Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 2005 >> # -- Compiling module FD_MXILINX_matt_sch >> # -- Compiling module matt_sch >> # >> # Top level modules: >> # matt_sch >> # Model Technology ModelSim XE III vcom 6.0d Compiler 2005.04 Apr 26 2005 >> # -- Loading package standard >> # -- Loading package textio >> # -- Loading package std_logic_1164 >> # -- Loading package std_logic_textio >> # -- Loading package std_logic_arith >> # -- Loading package std_logic_unsigned >> # -- Compiling entity m >> # -- Compiling architecture testbench_arch of m >> # Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 2005 >> # -- Compiling module glbl >> # >> # Top level modules: >> # glbl >> # vsim -L cpld_ver -L uni9000_ver -lib work -t 1ps m glbl >> # Loading C:\Modeltech_xe_starter\win32xoem/../std.standard >> # Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body) >> # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) >> # Loading >> C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) >> # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) >> # Loading >> C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) >> # Loading work.m(testbench_arch) >> # XE version supports only a single HDL >> # Error loading design >> # Error: Error loading design >> # Pausing macro execution >> # MACRO ./m.fdo PAUSED at line 8 >> >> >> >> > >Article: 96781
me_2003@walla.co.il wrote: > Hi Zara. > Thanks for the answers... > > >4) What does a bus-split / decoupled address terms stand for ? > > I don't know. Or at least, I don't recognize the concept under those > terms. But I am not native english speaver, it may just be a limited > knowledeg of the language. > > thoses terms are used in the plb bus description regarding the ability > to read/write in the same cycle. > Regards, Mordehay. The PLB bus is treated as three buses, the address bus, the read data bus and the write data bus. The PLB spec allows all three buses to be performing separate transactions at the same time. This is what is meant by the term split-bus. For example, starting from an idle state, a PLB master arbitrates for the address bus. Once granted the address bus, it sets up a transaction. Let us say it sets up a long burst write for this example. Once that transaction is acknowledged by a PLB slave, the PLB master releases the address bus, and starts putting data on the PLB write data bus. This is what is meant by decoupled address. The address bus is released as soon as the transaction is acknowledged, and can be used to set up more transactions. A second PLB master can then request the address bus. Once granted, it can set up another data transaction. Let us say it sets up a long burst read. Once a slave acknowledges the transaction, the PLB master relinquishes the address bus, and the PLB slave starts putting data on the read data bus. At this point in the example, there are two different data phase transactions going on at the same time, both a burst read, and a burst write. The address bus is free at this point to be used to set up the next transactions. For example, another read can be started which will allow the targeted PLB slave to start fetching the data. As soon as the first PLB slave that was performing a read finishes its transaction of the data bus, the second one can start placing its data on the bus. This is what is referred to as address pipelining in the PLB spec. If you have not already done so, download the IBM CoreConnect toolkit. It contains the specifications for the PLB, OPB, and DCR buses. It also has a simulation test bench with bus functional models and bus monitors. There are a few differences between the IBM spec, and how Xilinx has implemented the CoreConnect buses in EDK. Make sure to read the Xilinx documentation carefully, and take note of the differences. I got to the IBM CoreConnect toolkit through the Xilinx web site, but it has been long enough ago that I don't remember the link. Regards, John McCaskillArticle: 96782
You are referencing Verilog primitive libraries on the vsim line: vsim -L cpld_ver -L uni9000_ver -lib There must be an option in ISE to select the VHDL or Verilog? Are your schematics translated to Verilog? Hans www.ht-lab.com "mBird" <no@email.com> wrote in message news:11up72iddd8ao91@corp.supernews.com... >I downloaded the Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d from >Xilinx site. These are the free starter products. In the past I used ISE >and ModelSim older versions and all worked. I am not sure what I should do >to make these work. I just want simple VHDL and to use Schematics. I dont >see any way to tell ISE not to do dual language? Any advice appretiated! > > "Hans" <hans64@ht-lab.com> wrote in message > news:e6YGf.23547$Fy4.22367@newsfe4-win.ntli.net... >> Looks like you are using both vlog (verilog) and vcom (vhdl) compiler, >> check that you have a dual language license, >> >> Hans. >> www.ht-lab.com >> >> "mBird" <no@email.com> wrote in message >> news:11uo5ck9o574tfa@corp.supernews.com... >>>I just downloaded Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d >>> I make a simple project, using schematic (one and gate) an dthen make a >>> test bench waveform. I then do Simulate Behaviural Model but no matter >>> what I do I always get # Error loading design with no other indication >>> of erors. In the previous version of ISE and ModelSim it all worked so I >>> am not sure what is error? >>> Any help greatly appretiared! >>> >>> The results of from ModelSim: >>> # Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl >>> # do m.fdo >>> # ** Warning: (vlib-34) Library already exists at "work". >>> # Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 >>> 2005 >>> # -- Compiling module FD_MXILINX_matt_sch >>> # -- Compiling module matt_sch >>> # >>> # Top level modules: >>> # matt_sch >>> # Model Technology ModelSim XE III vcom 6.0d Compiler 2005.04 Apr 26 >>> 2005 >>> # -- Loading package standard >>> # -- Loading package textio >>> # -- Loading package std_logic_1164 >>> # -- Loading package std_logic_textio >>> # -- Loading package std_logic_arith >>> # -- Loading package std_logic_unsigned >>> # -- Compiling entity m >>> # -- Compiling architecture testbench_arch of m >>> # Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 >>> 2005 >>> # -- Compiling module glbl >>> # >>> # Top level modules: >>> # glbl >>> # vsim -L cpld_ver -L uni9000_ver -lib work -t 1ps m glbl >>> # Loading C:\Modeltech_xe_starter\win32xoem/../std.standard >>> # Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body) >>> # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) >>> # Loading >>> C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) >>> # Loading >>> C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) >>> # Loading >>> C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) >>> # Loading work.m(testbench_arch) >>> # XE version supports only a single HDL >>> # Error loading design >>> # Error: Error loading design >>> # Pausing macro execution >>> # MACRO ./m.fdo PAUSED at line 8 >>> >>> >>> >>> >> >> > >Article: 96783
The Xilinx App Note, xapp224, suggests that it's possible to do non-source-synchronous data recovery in a spartan-3 at up to 320 Mbps (320 MHz) -- has anyone ever managed to get this or higher serial speeds working in a spartan-3 PQ208 package? I'm trying to make this work with a 100-ohm differential LVDS link and I can't seem to get my design up past 150 Mbps. I'm totally willing to entertain the idea that I've got signal integrity problems, controlled impedance problems, etc. but I'm worried that the lead inductance on the PQ208 package might make this sort of IO impossible. Thanks, ...EricArticle: 96784
Hi John, Many many thanks for you taking the time to explain this issue - It realy helps me alot. I read the PLB spec (from both xilinx/ibm) but couldnt find any good decription of those terms. So thanks again and have a nice weekend.Article: 96785
Antti wrote: > I am ! happy and smiling, I got finally fully working MicroBlaze > uClinux image built fully from GPL sources on WinXP without the use of > any linux machine or linux emulation. > > here is short intro how todo this: > > http://help.xilant.com/UClinux:MicroBlaze:Win32Build > > I wish I could have time to add more detailed docu about the process > but I need to prepare some demos for the Embedded in Nurnberg what > starts next tuesday > > Antti > thanks Antti, Very nice and interesting job. Happy for you ! Laurent www.amontec.comArticle: 96786
Hi this problem arises when u r openning two instances of the model sim. try this out and see did u open the two instances of the modelsim. "XE version supports only a single HDL " this error is common when two windows of modelsim wre open Bye VipsArticle: 96787
Thanks all! Is there a way to dump the output of the mb-objdump to a file? It lists in the command console and it would be nice to have a hard-copy.Article: 96788
Do you know what caused the issues with compiling busybox and sh? Is it a build script issues, a cygwin issues, or a gcc issue? "11.now you get core dump whild building busybox and sh, those need to be pulled out and compiled out of tree and then injected back 12.the busybox and sh need to be in place in the build tree and the makefile adjusted to skip them durin main build" Antti wrote: > > I am ! happy and smiling, I got finally fully working MicroBlaze > uClinux image built fully from GPL sources on WinXP without the use of > any linux machine or linux emulation. > > here is short intro how todo this: > > http://help.xilant.com/UClinux:MicroBlaze:Win32Build > > I wish I could have time to add more detailed docu about the process > but I need to prepare some demos for the Embedded in Nurnberg what > starts next tuesday > > AnttiArticle: 96789
Use console redirection: mb-objdump -Sx executable.elf > executable.objdump motty wrote: > > Thanks all! Is there a way to dump the output of the mb-objdump to a > file? It lists in the command console and it would be nice to have a > hard-copy.Article: 96790
The project Synthesis Tool setting has only one setting: XST (VHDL/Verilog) I did get it to work by selecting ModelSim (PS/SE) Mixed instead of ModelSim XE as the project's simulator but I am puzzled as to how that could even work since I have ModelSim XE installed only? Thanks for your help and info! "Hans" <hans64@ht-lab.com> wrote in message news:rw1Hf.24458$Fy4.9903@newsfe4-win.ntli.net... > You are referencing Verilog primitive libraries on the vsim line: > > vsim -L cpld_ver -L uni9000_ver -lib > > There must be an option in ISE to select the VHDL or Verilog? Are your > schematics translated to Verilog? > > Hans > www.ht-lab.com > > > "mBird" <no@email.com> wrote in message > news:11up72iddd8ao91@corp.supernews.com... >>I downloaded the Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d from >>Xilinx site. These are the free starter products. In the past I used ISE >>and ModelSim older versions and all worked. I am not sure what I should do >>to make these work. I just want simple VHDL and to use Schematics. I dont >>see any way to tell ISE not to do dual language? Any advice appretiated! >> >> "Hans" <hans64@ht-lab.com> wrote in message >> news:e6YGf.23547$Fy4.22367@newsfe4-win.ntli.net... >>> Looks like you are using both vlog (verilog) and vcom (vhdl) compiler, >>> check that you have a dual language license, >>> >>> Hans. >>> www.ht-lab.com >>> >>> "mBird" <no@email.com> wrote in message >>> news:11uo5ck9o574tfa@corp.supernews.com... >>>>I just downloaded Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d >>>> I make a simple project, using schematic (one and gate) an dthen make a >>>> test bench waveform. I then do Simulate Behaviural Model but no matter >>>> what I do I always get # Error loading design with no other indication >>>> of erors. In the previous version of ISE and ModelSim it all worked so >>>> I am not sure what is error? >>>> Any help greatly appretiared! >>>> >>>> The results of from ModelSim: >>>> # Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl >>>> # do m.fdo >>>> # ** Warning: (vlib-34) Library already exists at "work". >>>> # Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 >>>> 2005 >>>> # -- Compiling module FD_MXILINX_matt_sch >>>> # -- Compiling module matt_sch >>>> # >>>> # Top level modules: >>>> # matt_sch >>>> # Model Technology ModelSim XE III vcom 6.0d Compiler 2005.04 Apr 26 >>>> 2005 >>>> # -- Loading package standard >>>> # -- Loading package textio >>>> # -- Loading package std_logic_1164 >>>> # -- Loading package std_logic_textio >>>> # -- Loading package std_logic_arith >>>> # -- Loading package std_logic_unsigned >>>> # -- Compiling entity m >>>> # -- Compiling architecture testbench_arch of m >>>> # Model Technology ModelSim XE III vlog 6.0d Compiler 2005.04 Apr 26 >>>> 2005 >>>> # -- Compiling module glbl >>>> # >>>> # Top level modules: >>>> # glbl >>>> # vsim -L cpld_ver -L uni9000_ver -lib work -t 1ps m glbl >>>> # Loading C:\Modeltech_xe_starter\win32xoem/../std.standard >>>> # Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body) >>>> # Loading >>>> C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) >>>> # Loading >>>> C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) >>>> # Loading >>>> C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) >>>> # Loading >>>> C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) >>>> # Loading work.m(testbench_arch) >>>> # XE version supports only a single HDL >>>> # Error loading design >>>> # Error: Error loading design >>>> # Pausing macro execution >>>> # MACRO ./m.fdo PAUSED at line 8 >>>> >>>> >>>> >>>> >>> >>> >> >> > >Article: 96791
Hi Paul I have found following issues 1) /user/mount/mount.c C compiler parse error !? 2) /user/sh and user/busybox both fail on final linking or elf2flt conversion when invoked from main build tree, so as a workaround I let the busybox to be compiled into .a and .o files inside the main build tree, then copy out the .a and .o and run link elf2flt in out of tree setup, then copy the busybox executable back into main tree both cause 'core dump' when in main tree, but sh also cause core dump in out of tree, during elf2flt so for sh I invoke the elf2flt again after out of tree build this is busybox when in main tree Exception: STATUS_ACCESS_VIOLATION at eip=610D9100 eax=0022F12C ebx=00000000 ecx=6115D8BC edx=00000000 esi=00000007 edi=0000000A ebp=0022E588 esp=0022E570 program=c:\mb_gnu_8_1\microblaze\bin\elf2flt.exe, pid 2884, thread main cs=001B ds=0023 es=0023 fs=003B gs=0000 ss=0023 Stack trace: Frame Function Args 0022E588 610D9100 (0022F12C, 00000000, 00000000, 0000000A) 0022E5A8 610D9288 (00000000, 00000000, 0000000A, 00000000) 0022E5C8 610D5040 (00000000, 6115D8BC, 0042B533, 00401B9F) 0022EEC8 00402399 (00000007, 6115D8BC, 00490090, 77DADB0D) 0022EF78 61005BC8 (0022EFD0, 0022EFC0, 00000005, 00000000) 0022FF88 61005EB3 (00000000, 00000000, 00000000, 00000000) End of stack trace ok, let ma attach the makefiles that I use for busybox/sh out of tree ----------------------------- ifndef ROOTDIR ROOTDIR=../uClinux-dist endif UCLINUX_BUILD_USER = 1 include $(ROOTDIR)/.config LIBCDIR = $(CONFIG_LIBCDIR) include $(ROOTDIR)/config.arch BB = busybox BB_OBJS += ./init/init.o ./init/init_shared.o BB_OBJS += ./networking/hostname.o BB_OBJS += ./util-linux/mount.o BB_OBJS += ./shell/hush.o BB_OBJS += ./coreutils/ls.o ./coreutils/mkdir.o ./coreutils/true.o ./coreutils/false.o ./coreutils/echo.o ./coreutils/chmod.o ./coreutils/test.o ## BB_OBJS += ./applets/busybox.o ./applets/applets.o LDLIBS += ./libbb/libbb.a LDLIBS += ./applets/applets.a ## LDLIBS += ./coreutils/coreutils.a ##LDLIBS += ./shell/shell.a all: $(BB) cp busybox.elf.bflt busybox $(BB): $(BB_OBJS) $(CC) $(LDFLAGS) -o $@ $(BB_OBJS) $(LDLIBS) clean: -rm -f $(BB) *.elf *.gdb *.o %.o: %.c $(CC) -c $(CFLAGS) -o $@ $< -------------------------- ifndef ROOTDIR ROOTDIR=../uClinux-dist endif UCLINUX_BUILD_USER = 1 include $(ROOTDIR)/.config LIBCDIR = $(CONFIG_LIBCDIR) include $(ROOTDIR)/config.arch CFLAGS += -DHAVE_MALLOC FLTFLAGS += -s 8192 SH = sh SH_OBJS += sh1.o sh2.o sh3.o sh4.o sh5.o sh6.o #LDLIBS += ./libbb/libbb.a all: $(SH) cp sh.elf.bflt sh $(SH): $(SH_OBJS) $(CC) $(LDFLAGS) -o $@ $(SH_OBJS) $(LDLIBS$(LDLIBS_$@)) clean: -rm -f $(TFT) *.elf *.gdb *.o %.o: %.c $(CC) -c $(CFLAGS) -o $@ $< ----------------------- the busybox makefile does produce flat exe from makefile the sh make file produces Exception: STATUS_ACCESS_VIOLATION at eip=610D9100 eax=0022F12C ebx=00000000 ecx=6115DE74 edx=00000000 esi=00000007 edi=0000000A ebp=0022E588 esp=0022E570 program=c:\mb_gnu_8_1\microblaze\bin\elf2flt.exe, pid 5172, thread main cs=001B ds=0023 es=0023 fs=003B gs=0000 ss=0023 Stack trace: Frame Function Args 0022E588 610D9100 (0022F12C, 00000000, 00000000, 0000000A) 0022E5A8 610D9288 (00000000, 00000000, 0000000A, 00000000) 0022E5C8 610D5040 (00000000, 6115DE74, 0042B533, 00401B9F) 0022EEC8 00402399 (00000007, 6115DE74, 00490090, 77DADB0D) 0022EF78 61005BC8 (0022EFD0, 0022EFC0, 00000002, 00000000) 0022FF88 61005EB3 (00000000, 00000000, 00000000, 00000000) End of stack trace so I convert it after make manually with bat file mb-elf2flt sh.elf copy sh.elf.bflt sh this sh is correct working exe ! I assume the issues are in the elf2flt mainly 3) all flat exes produced have .elf.bflt extension so I had to modify the makefiles to get proper exe names, dont know what is causing this or where would the proper fix to this issue belong too AnttiArticle: 96792
Hi -- Thanks for the idea. I am sure to have only one instance running. I did get it to work by selecting ModelSim (PS/SE) Mixed instead of ModelSim XE as the project's simulator but I am puzzled as to how that could even work since I have ModelSim XE installed only? Thanks for your help and info! "VIPS" <thevipulsinha@gmail.com> wrote in message news:1139583102.164399.197010@o13g2000cwo.googlegroups.com... > Hi > this problem arises when u r openning two instances of the model sim. > try this out and see did u open the two instances of the modelsim. > "XE version supports only a single HDL " this error is common when two > windows of modelsim wre open > > Bye > > Vips >Article: 96793
Thomas gave the answer to the problem. David second it. Why not just adding two flops at sel and add? This will solve the problem.Article: 96794
Sky wrote: > In a project I use the Altera EPM3256ATC144-10. > Now I have the necessity to make some changes to the project, but I don't > have enough macrocells in the actual devices. > Alteras doesn't have a pin-to-pin compatible EPLD with the EPM3256ATC144-10 > but with more macrocelles (about +40%). > What of you knows a devices that could resolve my problem? Unfortunately I > cannot modify the PCB, but I could replace the Altera EPLD with any other > CPLD. Depending on the required speed you may connect wires to the 144 pads... and connect then to an external box containing whatever. Yes, I'm aware the wires are very fine. Thus, I'd rather 1) do a new pcb 2) squeeze a reduced functionality in the existing part. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 96795
Paul Johnson wrote: > On 9 Feb 2006 15:58:10 -0800, "rickman" <spamgoeshere4@yahoo.com> > wrote: > > >You have ignored the real issue. The issue is not whether the async > >design can run faster under typical conditions; we all know it can. > >The issue is how do you make use of that faster speed? The system > >design has to work in the worst case conditions, so you can only use > >the available performance under worse case conditions. > > I think there's an issue here with the definition of "worst-case > conditions". It's not just process/voltage/temperature corners, and > tool would have to build in a safety margin even if it was. But, when > you're designing a static timing analyser, you also have to take into > account random localised on-die variations, and you have to build in > more safety margin just in case. The end result is that when doing > synchronous design your tool gives you a conservative estimate, and > you're stuck with it. If you've got a bad process async design and a > bad-process sync design sitting next to each other in a hot room with > low voltages, then the async design should presumably run faster. I had a chance to think about this further and I think the localized variables in path delays actually hurt the async device more than it does the sync device. The idea behind the sync clocked design is to deal with all the issues that make the logic delay time so variable. Instead of trying to match delays with the clocking, the entire issue is lumped into the clock domain. The clock period has to be larger than the worst case delay through the logic plus an additional margin for the skewing of the clock. Minimizing clock skew is the purpose of the clock tree. So this is typically very small and only needs to be added to the logic delay to get the minimum clock period. The async processor must match the clock delay with the logic delay and always keep the clock delay slightly larger. There are always variations in timing of similar components due to statistical factors. Even if it is out at the 3 sigma point, by having a million transitors on a die, you have to account for the few that are either fast or slow. The worst case would be a fast clock path and a slow logic path. This skewing must be considered at the logic and clock level. In the end you end up having to allow for the deviation in both directions which means it is doubled. So the async design likely must have larger margins added to the design of the handshake path and the result is it will have a slower maximum speed compared to a sync design.Article: 96796
That sounds like a wonderfull recipe for field failures if carried to production. I might say that it would be workable for a prototype, but I wouldn't go much farther than that. You indicated in your original post that you are not able to modify the PCB. Is there a real reason for this or is it just a case of where MGT doesn't WANT to modify the PCB? Quite frankly, often times I have found that far more enegy is spent attempting to take a short cut around something and failing than would have been spent to do it right the first time.Article: 96797
rickman wrote: > But the real issue is what do you do with the excess speed of the async > design at room temp, etc? Your design has to meet specific goals over > all variables of temp, voltage and process. You are too focused on the MHz - forget the MHz for a moment, and look at the pJ and uV/m. Many, many designers would be very happy to get those gains, and still be in the same MHz ballpark. The High end CPU you mentioned, quotes 15,000 gated clock elements. At that count, it has to asympotpe to async performance anyway, and it becomes a semantics exercise what you call a device with that many gated/local/granular clocks... -jgArticle: 96798
Isaac Bosompem wrote: > Hi guys, I've been reading through the Spartan3 architecture embedded > multipliers app note and I can't seem to find out how long (in terms of > clock cycles) the sync multipliers in the Spartan3 will take. Can I > safely assume that after I have asserted the inputs to the module, I > will get the output back in the following clock cycle? > > Thanks, > > Isaac No asumption is safe, IHMO, run a simple simulation to verify it, sometimes that's quicker than digging in the docs jungle.Article: 96799
Super! Thanks alot! Now I can make some good progress....
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