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MM wrote: > I have an OPB_GPIO module configured as all outputs. It is a part of an EDK > system which is instantiated as a module in a top-level ISE project. I am > using d_outs from the GPIO module. When I tried inserting some logic between > these outputs and the top level pins I got the following error: > > ERROR:NgdBuild:809 - output pad net 'gpio_leds<4>' has an illegal load: > pin I2 on block _n00141 with type LUT3 > > So, does that mean that I can't drive any internal logic with GPIO outputs? GPIO outputs can drive internal logic. Sometimes it's easier than building an IPIF interface. I'm going to take a guess and say that you connected your internal logic input to the IOB instead of to the GPIO. Post the code if you want someone to figure it out. --- Joe Samson Pixel VelocityArticle: 97126
eziggurat@gmail.com wrote: > Has anybody interface a WIFI compact flash with a FPGA? Could provide > any tips or information in how you did it. > > Regards > > Paul Lee Perhaps maybe you can pick up the datasheet of the chip used in your WiFi compact flash board and take a peek at it? It is most likely a simple memory mapped hardware interface (or ATA like interface given its a CF standard).Article: 97127
For those looking at smaller FPGA and USB, this new device has both Host and Peripheral modes, and has a 26MHz SPI link. Interface is via 32 registers, includes 15KV ESD USB drivers. Opens up FPGA access USB Flash drives as storage, and USB keyboards etc... -jgArticle: 97128
Shyam, HardCopy II uses two layers of metal customization, plus three via layers as well, for a total of 5 masks. The layers altered are in the middle of the metal stack (actually metal layers 5 and 6). With HardCopy Stratix we used a similar arrangement but on a 130nm rather than 90nm process of course. The turnaround time we are quoting for both HardCopy Stratix and HardCopy II is approximately the same (to a limited extent it is design dependent, and this can affect what you get quoted). By Q4 of this year, the turnaround time of HardCopy II will be lower than HC Stratix. This is for two reasons. Firstly the flow for HC II has been designed with increased automation in mind, and we are ramping this up as we do more designs. Secondly, the logic fabric of HC II allows for much higher performance in comparison with the initial FPGA than HC-Stratix did. This gives us more margin in meeting timing and means it's much easier to get timing closure when doing final routing of the HC II device. This is going to translate into shorter conversion times. Hope this helps. Paul. Shyam wrote: > Hi, > > I have a few questions regarding user masks in Altera's HardCopy and > HardCopy II structured ASICs. The HardCopy handbook suggests that the > "top two metal layers" are utilized for user customization while the > HardCopy II handbook just suggests that "two metal layers" are utilized > for the same; in case of HardCopy II nowhere is it suggested that the > "top two metal layers" are utilized for customization. Having said that > I have the following questions: > > 1. Which are the user mask layers in HardCopy and HardCopy II? > > 2. How many user mask layers are being used exactly? Just two > corresponding to two metal layers or perhaps four including via layers? > > 3. Is the turnaround time for HardCopy II greater than that of HardCopy > perhaps because user customization has not been deferred to the highest > mask layers and a lower mask layer needs to be used? > > Thanks very much.Article: 97129
I have a schematic of a 4bit adder in my CAD program. It has the
ability to create a "VHDL schematic netlist". I've been trying to find
a software package that I can use to simulate this schematic. It says
"It can be used in conjunction with PLD software from Altera and
Xilinx.
Could someone recomend to me the program from Altera or Xilinx?
Hopefully there is a free version?
I don't need to simulate my schematic as if it were TTL logic, I just
want to make sure it works. I will be expanding it to 32bits and there
will be a lot of places for errors!!!
I've atached the VHDL and EDIF files.
Thanks!
LIBRARY IEEE
USE IEEE.std_logic_1164.all
ENTITY MULTIPLY IS PORT
(
); END MULTIPLY;
ARCHITECTURE STRUCTURE OF MULTIPLY IS
-- COMPONENTS
COMPONENT TTL__74LS04 PORT
(
I_A : IN std_logic;
O_A : OUT std_logic;
I_B : IN std_logic;
O_B : OUT std_logic;
I_C : IN std_logic;
O_C : OUT std_logic;
GND : IN std_logic;
O_D : OUT std_logic;
I_D : IN std_logic;
O_E : OUT std_logic;
I_E : IN std_logic;
O_F : OUT std_logic;
I_F : IN std_logic;
VCC : IN std_logic
); END COMPONENT;
COMPONENT TTL__74LS02 PORT
(
O_A : OUT std_logic;
I0_A : IN std_logic;
I1_A : IN std_logic;
O_B : OUT std_logic;
I0_B : IN std_logic;
I1_B : IN std_logic;
GND : IN std_logic;
I0_C : IN std_logic;
I1_C : IN std_logic;
O_C : OUT std_logic;
I0_D : IN std_logic;
I1_D : IN std_logic;
O_D : OUT std_logic;
VCC : IN std_logic
); END COMPONENT;
COMPONENT TTL__74LS00 PORT
(
I0_A : IN std_logic;
I1_A : IN std_logic;
O_A : OUT std_logic;
I0_B : IN std_logic;
I1_B : IN std_logic;
O_B : OUT std_logic;
GND : IN std_logic;
O_C : OUT std_logic;
I0_C : IN std_logic;
I1_C : IN std_logic;
O_D : OUT std_logic;
I0_D : IN std_logic;
I1_D : IN std_logic;
VCC : IN std_logic
); END COMPONENT;
COMPONENT TTL__74LS08 PORT
(
I0_A : IN std_logic;
I1_A : IN std_logic;
O_A : OUT std_logic;
I0_B : IN std_logic;
I1_B : IN std_logic;
O_B : OUT std_logic;
GND : IN std_logic;
O_C : OUT std_logic;
I0_C : IN std_logic;
I1_C : IN std_logic;
O_D : OUT std_logic;
I0_D : IN std_logic;
I1_D : IN std_logic;
VCC : IN std_logic
); END COMPONENT;
COMPONENT TTL__74LS11 PORT
(
I0_A : IN std_logic;
I1_A : IN std_logic;
I0_B : IN std_logic;
I1_B : IN std_logic;
I2_B : IN std_logic;
O_B : OUT std_logic;
GND : IN std_logic;
O_C : OUT std_logic;
I0_C : IN std_logic;
I1_C : IN std_logic;
I2_C : IN std_logic;
O_A : OUT std_logic;
I2_A : IN std_logic;
VCC : IN std_logic
); END COMPONENT;
COMPONENT TTL__74LS21 PORT
(
I0_A : IN std_logic;
I1_A : IN std_logic;
I2_A : IN std_logic;
I3_A : IN std_logic;
O_A : OUT std_logic;
GND : IN std_logic;
O_B : OUT std_logic;
I0_B : IN std_logic;
I1_B : IN std_logic;
I2_B : IN std_logic;
I3_B : IN std_logic;
VCC : IN std_logic
); END COMPONENT;
COMPONENT TTL__7425 PORT
(
I0_A : IN std_logic;
I1_A : IN std_logic;
G_A : IN std_logic;
I2_A : IN std_logic;
I3_A : IN std_logic;
O_A : OUT std_logic;
GND : IN std_logic;
O_B : OUT std_logic;
I0_B : IN std_logic;
I1_B : IN std_logic;
G_B : IN std_logic;
I2_B : IN std_logic;
I3_B : IN std_logic;
VCC : IN std_logic
); END COMPONENT;
COMPONENT TTL__74LS27 PORT
(
I0_A : IN std_logic;
I1_A : IN std_logic;
I0_B : IN std_logic;
I1_B : IN std_logic;
I2_B : IN std_logic;
O_B : OUT std_logic;
GND : IN std_logic;
O_C : OUT std_logic;
I0_C : IN std_logic;
I1_C : IN std_logic;
I2_C : IN std_logic;
O_A : OUT std_logic;
I2_A : IN std_logic;
VCC : IN std_logic
); END COMPONENT;
COMPONENT TTL__74LS86 PORT
(
I0_A : IN std_logic;
I1_A : IN std_logic;
O_A : OUT std_logic;
I0_B : IN std_logic;
I1_B : IN std_logic;
O_B : OUT std_logic;
GND : IN std_logic;
O_C : OUT std_logic;
I0_C : IN std_logic;
I1_C : IN std_logic;
O_D : OUT std_logic;
I0_D : IN std_logic;
I1_D : IN std_logic;
VCC : IN std_logic
); END COMPONENT;
-- SIGNALS
SIGNAL A0_1 : std_logic;
SIGNAL A0_NAND_B0_1 : std_logic;
SIGNAL A0_NOR_B0_1 : std_logic;
SIGNAL A1_1 : std_logic;
SIGNAL A1_NAND_B1_1 : std_logic;
SIGNAL A1_NOR_B1_1 : std_logic;
SIGNAL A2_1 : std_logic;
SIGNAL A2_NAND_B2_1 : std_logic;
SIGNAL A2_NOR_B2_1 : std_logic;
SIGNAL A3_1 : std_logic;
SIGNAL A3_NAND_B3_1 : std_logic;
SIGNAL A3_NOR_B3_1 : std_logic;
SIGNAL B0_1 : std_logic;
SIGNAL B1_1 : std_logic;
SIGNAL B2_1 : std_logic;
SIGNAL B3_1 : std_logic;
SIGNAL \C\\A\\R\\R\\Y\\_\\I\\N\\_1\ : std_logic;
SIGNAL CARRY_IN_1 : std_logic;
SIGNAL GND : std_logic;
SIGNAL S0_1 : std_logic;
SIGNAL S1_1 : std_logic;
SIGNAL S2_1 : std_logic;
SIGNAL S3_1 : std_logic;
SIGNAL VCC : std_logic;
SIGNAL NET10_1 : std_logic;
SIGNAL NET11_1 : std_logic;
SIGNAL NET12_1 : std_logic;
SIGNAL NET13_1 : std_logic;
SIGNAL NET14_1 : std_logic;
SIGNAL NET15_1 : std_logic;
SIGNAL NET16_1 : std_logic;
SIGNAL NET17_1 : std_logic;
SIGNAL NET18_1 : std_logic;
SIGNAL NET1_1 : std_logic;
SIGNAL NET2_1 : std_logic;
SIGNAL NET3_1 : std_logic;
SIGNAL NET4_1 : std_logic;
SIGNAL NET5_1 : std_logic;
SIGNAL NET6_1 : std_logic;
SIGNAL NET7_1 : std_logic;
SIGNAL NET8_1 : std_logic;
SIGNAL NET9_1 : std_logic;
-- GATE INSTANCES
BEGIN
U1 : TTL__74LS04 PORT MAP
(
I_A => CARRY_IN_1,
O_A => \C\\A\\R\\R\\Y\\_\\I\\N\\_1\,
I_B => A3_NOR_B3_1,
O_B => NET15_1,
I_C => A2_NOR_B2_1,
O_C => NET12_1,
GND => GND,
O_D => NET10_1,
I_D => A1_NOR_B1_1,
O_E => NET9_1,
I_E => A0_NOR_B0_1,
O_F => NET1_1,
I_F => \C\\A\\R\\R\\Y\\_\\I\\N\\_1\,
VCC => VCC
);
U2 : TTL__74LS02 PORT MAP
(
O_A => A0_NOR_B0_1,
I0_A => A0_1,
I1_A => B0_1,
O_B => A1_NOR_B1_1,
I0_B => A1_1,
I1_B => B1_1,
GND => GND,
I0_C => A2_1,
I1_C => B2_1,
O_C => A2_NOR_B2_1,
I0_D => A3_1,
I1_D => B3_1,
O_D => A3_NOR_B3_1,
VCC => VCC
);
U3 : TTL__74LS00 PORT MAP
(
I0_A => A0_1,
I1_A => B0_1,
O_A => A0_NAND_B0_1,
I0_B => A1_1,
I1_B => B1_1,
O_B => A1_NAND_B1_1,
GND => GND,
O_C => A2_NAND_B2_1,
I0_C => A2_1,
I1_C => B2_1,
O_D => A3_NAND_B3_1,
I0_D => A3_1,
I1_D => B3_1,
VCC => VCC
);
U4 : TTL__74LS08 PORT MAP
(
I0_A => A1_NOR_B1_1,
I1_A => A2_NAND_B2_1,
O_A => NET18_1,
I0_B => NET15_1,
I1_B => A3_NAND_B3_1,
O_B => NET3_1,
GND => GND,
O_C => NET14_1,
I0_C => A0_NOR_B0_1,
I1_C => A0_NAND_B0_1,
O_D => NET5_1,
I0_D => NET12_1,
I1_D => A2_NAND_B2_1,
VCC => VCC
);
U5 : TTL__74LS11 PORT MAP
(
I0_A => A0_NOR_B0_1,
I1_A => A1_NAND_B1_1,
I0_B => \C\\A\\R\\R\\Y\\_\\I\\N\\_1\,
I1_B => A0_NAND_B0_1,
I2_B => A1_NAND_B1_1,
O_B => NET13_1,
GND => GND,
O_C => OPEN,
I0_C => OPEN,
I1_C => OPEN,
I2_C => OPEN,
O_A => NET17_1,
I2_A => A2_NAND_B2_1,
VCC => VCC
);
U6 : TTL__74LS21 PORT MAP
(
I0_A => \C\\A\\R\\R\\Y\\_\\I\\N\\_1\,
I1_A => A0_NAND_B0_1,
I2_A => A1_NAND_B1_1,
I3_A => A2_NAND_B2_1,
O_A => NET16_1,
GND => GND,
O_B => OPEN,
I0_B => OPEN,
I1_B => OPEN,
I2_B => OPEN,
I3_B => OPEN,
VCC => VCC
);
U7 : TTL__7425 PORT MAP
(
I0_A => A2_NOR_B2_1,
I1_A => NET18_1,
G_A => OPEN,
I2_A => NET17_1,
I3_A => NET16_1,
O_A => NET2_1,
GND => GND,
O_B => OPEN,
I0_B => OPEN,
I1_B => OPEN,
G_B => OPEN,
I2_B => OPEN,
I3_B => OPEN,
VCC => VCC
);
U8 : TTL__74LS27 PORT MAP
(
I0_A => A1_NOR_B1_1,
I1_A => NET14_1,
I0_B => OPEN,
I1_B => OPEN,
I2_B => OPEN,
O_B => OPEN,
GND => GND,
O_C => OPEN,
I0_C => OPEN,
I1_C => OPEN,
I2_C => OPEN,
O_A => NET4_1,
I2_A => NET13_1,
VCC => VCC
);
U9 : TTL__74LS08 PORT MAP
(
I0_A => \C\\A\\R\\R\\Y\\_\\I\\N\\_1\,
I1_A => A0_NAND_B0_1,
O_A => NET11_1,
I0_B => NET10_1,
I1_B => A1_NAND_B1_1,
O_B => NET7_1,
GND => GND,
O_C => NET8_1,
I0_C => NET9_1,
I1_C => A0_NAND_B0_1,
O_D => OPEN,
I0_D => OPEN,
I1_D => OPEN,
VCC => VCC
);
U10 : TTL__74LS02 PORT MAP
(
O_A => NET6_1,
I0_A => A0_NOR_B0_1,
I1_A => NET11_1,
O_B => OPEN,
I0_B => OPEN,
I1_B => OPEN,
GND => GND,
I0_C => OPEN,
I1_C => OPEN,
O_C => OPEN,
I0_D => OPEN,
I1_D => OPEN,
O_D => OPEN,
VCC => VCC
);
U11 : TTL__74LS86 PORT MAP
(
I0_A => NET1_1,
I1_A => NET8_1,
O_A => S0_1,
I0_B => NET7_1,
I1_B => NET6_1,
O_B => S1_1,
GND => GND,
O_C => S2_1,
I0_C => NET5_1,
I1_C => NET4_1,
O_D => S3_1,
I0_D => NET3_1,
I1_D => NET2_1,
VCC => VCC
);
END STRUCTURE;
And here is the EDIF:
(edif MULTIPLY
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2006 02 16 17 37 48)
(program "SchEdit.exe")
(comment "Original data from Qcad/Schematics"))
(comment "MULTIPLY")
(comment "Thursday, February 16, 2006")
(comment "1")
(comment "1")
(comment "Microcad")
(comment "1-416-783-8886")
(comment "")
(comment "")
(comment ""))
(external QCAD_LIB
(edifLevel 0)
(technology
(numberDefinition
(scale 1 1 (unit distance))))
(cell &74LS04
(cellType generic)
(comment "From QCAD library TTL")
(view NetlistView
(viewType netlist)
(interface
(port I_A (direction INPUT))
(port O_A (direction OUTPUT))
(port I_B (direction INPUT))
(port O_B (direction OUTPUT))
(port I_C (direction INPUT))
(port O_C (direction OUTPUT))
(port GND (direction INPUT))
(port O_D (direction OUTPUT))
(port I_D (direction INPUT))
(port O_E (direction OUTPUT))
(port I_E (direction INPUT))
(port O_F (direction OUTPUT))
(port I_F (direction INPUT))
(port VCC (direction INPUT)))))
(cell &74LS02
(cellType generic)
(comment "From QCAD library TTL")
(view NetlistView
(viewType netlist)
(interface
(port O_A (direction OUTPUT))
(port I0_A (direction INPUT))
(port I1_A (direction INPUT))
(port O_B (direction OUTPUT))
(port I0_B (direction INPUT))
(port I1_B (direction INPUT))
(port GND (direction INPUT))
(port I0_C (direction INPUT))
(port I1_C (direction INPUT))
(port O_C (direction OUTPUT))
(port I0_D (direction INPUT))
(port I1_D (direction INPUT))
(port O_D (direction OUTPUT))
(port VCC (direction INPUT)))))
(cell &74LS00
(cellType generic)
(comment "From QCAD library TTL")
(view NetlistView
(viewType netlist)
(interface
(port I0_A (direction INPUT))
(port I1_A (direction INPUT))
(port O_A (direction OUTPUT))
(port I0_B (direction INPUT))
(port I1_B (direction INPUT))
(port O_B (direction OUTPUT))
(port GND (direction INPUT))
(port O_C (direction OUTPUT))
(port I0_C (direction INPUT))
(port I1_C (direction INPUT))
(port O_D (direction OUTPUT))
(port I0_D (direction INPUT))
(port I1_D (direction INPUT))
(port VCC (direction INPUT)))))
(cell &74LS08
(cellType generic)
(comment "From QCAD library TTL")
(view NetlistView
(viewType netlist)
(interface
(port I0_A (direction INPUT))
(port I1_A (direction INPUT))
(port O_A (direction OUTPUT))
(port I0_B (direction INPUT))
(port I1_B (direction INPUT))
(port O_B (direction OUTPUT))
(port GND (direction INPUT))
(port O_C (direction OUTPUT))
(port I0_C (direction INPUT))
(port I1_C (direction INPUT))
(port O_D (direction OUTPUT))
(port I0_D (direction INPUT))
(port I1_D (direction INPUT))
(port VCC (direction INPUT)))))
(cell &74LS11
(cellType generic)
(comment "From QCAD library TTL")
(view NetlistView
(viewType netlist)
(interface
(port I0_A (direction INPUT))
(port I1_A (direction INPUT))
(port I0_B (direction INPUT))
(port I1_B (direction INPUT))
(port I2_B (direction INPUT))
(port O_B (direction OUTPUT))
(port GND (direction INPUT))
(port O_C (direction OUTPUT))
(port I0_C (direction INPUT))
(port I1_C (direction INPUT))
(port I2_C (direction INPUT))
(port O_A (direction OUTPUT))
(port I2_A (direction INPUT))
(port VCC (direction INPUT)))))
(cell &74LS21
(cellType generic)
(comment "From QCAD library TTL")
(view NetlistView
(viewType netlist)
(interface
(port I0_A (direction INPUT))
(port I1_A (direction INPUT))
(port I2_A (direction INPUT))
(port I3_A (direction INPUT))
(port O_A (direction OUTPUT))
(port GND (direction INPUT))
(port O_B (direction OUTPUT))
(port I0_B (direction INPUT))
(port I1_B (direction INPUT))
(port I2_B (direction INPUT))
(port I3_B (direction INPUT))
(port VCC (direction INPUT)))))
(cell &7425
(cellType generic)
(comment "From QCAD library TTL")
(view NetlistView
(viewType netlist)
(interface
(port I0_A (direction INPUT))
(port I1_A (direction INPUT))
(port G_A (direction INPUT))
(port I2_A (direction INPUT))
(port I3_A (direction INPUT))
(port O_A (direction OUTPUT))
(port GND (direction INPUT))
(port O_B (direction OUTPUT))
(port I0_B (direction INPUT))
(port I1_B (direction INPUT))
(port G_B (direction INPUT))
(port I2_B (direction INPUT))
(port I3_B (direction INPUT))
(port VCC (direction INPUT)))))
(cell &74LS27
(cellType generic)
(comment "From QCAD library TTL")
(view NetlistView
(viewType netlist)
(interface
(port I0_A (direction INPUT))
(port I1_A (direction INPUT))
(port I0_B (direction INPUT))
(port I1_B (direction INPUT))
(port I2_B (direction INPUT))
(port O_B (direction OUTPUT))
(port GND (direction INPUT))
(port O_C (direction OUTPUT))
(port I0_C (direction INPUT))
(port I1_C (direction INPUT))
(port I2_C (direction INPUT))
(port O_A (direction OUTPUT))
(port I2_A (direction INPUT))
(port VCC (direction INPUT)))))
(cell &74LS86
(cellType generic)
(comment "From QCAD library TTL")
(view NetlistView
(viewType netlist)
(interface
(port I0_A (direction INPUT))
(port I1_A (direction INPUT))
(port O_A (direction OUTPUT))
(port I0_B (direction INPUT))
(port I1_B (direction INPUT))
(port O_B (direction OUTPUT))
(port GND (direction INPUT))
(port O_C (direction OUTPUT))
(port I0_C (direction INPUT))
(port I1_C (direction INPUT))
(port O_D (direction OUTPUT))
(port I0_D (direction INPUT))
(port I1_D (direction INPUT))
(port VCC (direction INPUT))))))
(library MAIN_LIB
(edifLevel 0)
(technology
(numberDefinition
(scale 1 1 (unit distance))))
(cell MULTIPLY
(cellType generic)
(view NetlistView
(viewType netlist)
(interface)
(contents
(instance U1
(viewRef NetlistView
(cellRef &74LS04
(libraryRef QCAD_LIB))))
(instance U2
(viewRef NetlistView
(cellRef &74LS02
(libraryRef QCAD_LIB))))
(instance U3
(viewRef NetlistView
(cellRef &74LS00
(libraryRef QCAD_LIB))))
(instance U4
(viewRef NetlistView
(cellRef &74LS08
(libraryRef QCAD_LIB))))
(instance U5
(viewRef NetlistView
(cellRef &74LS11
(libraryRef QCAD_LIB))))
(instance U6
(viewRef NetlistView
(cellRef &74LS21
(libraryRef QCAD_LIB))))
(instance U7
(viewRef NetlistView
(cellRef &7425
(libraryRef QCAD_LIB))))
(instance U8
(viewRef NetlistView
(cellRef &74LS27
(libraryRef QCAD_LIB))))
(instance U9
(viewRef NetlistView
(cellRef &74LS08
(libraryRef QCAD_LIB))))
(instance U10
(viewRef NetlistView
(cellRef &74LS02
(libraryRef QCAD_LIB))))
(instance U11
(viewRef NetlistView
(cellRef &74LS86
(libraryRef QCAD_LIB))))
(net A0_1
(joined
(portRef I0_A (instanceRef U2))
(portRef I0_A (instanceRef U3))))
(net A0_NAND_B0_1
(joined
(portRef O_A (instanceRef U3))
(portRef I1_C (instanceRef U4))
(portRef I1_B (instanceRef U5))
(portRef I1_A (instanceRef U6))
(portRef I1_C (instanceRef U9))
(portRef I1_A (instanceRef U9))))
(net A0_NOR_B0_1
(joined
(portRef I_E (instanceRef U1))
(portRef O_A (instanceRef U2))
(portRef I0_C (instanceRef U4))
(portRef I0_A (instanceRef U5))
(portRef I0_A (instanceRef U10))))
(net A1_1
(joined
(portRef I0_B (instanceRef U2))
(portRef I0_B (instanceRef U3))))
(net A1_NAND_B1_1
(joined
(portRef O_B (instanceRef U3))
(portRef I1_A (instanceRef U5))
(portRef I2_B (instanceRef U5))
(portRef I2_A (instanceRef U6))
(portRef I1_B (instanceRef U9))))
(net A1_NOR_B1_1
(joined
(portRef I_D (instanceRef U1))
(portRef O_B (instanceRef U2))
(portRef I0_A (instanceRef U4))
(portRef I0_A (instanceRef U8))))
(net A2_1
(joined
(portRef I0_C (instanceRef U2))
(portRef I0_C (instanceRef U3))))
(net A2_NAND_B2_1
(joined
(portRef O_C (instanceRef U3))
(portRef I1_D (instanceRef U4))
(portRef I1_A (instanceRef U4))
(portRef I2_A (instanceRef U5))
(portRef I3_A (instanceRef U6))))
(net A2_NOR_B2_1
(joined
(portRef I_C (instanceRef U1))
(portRef O_C (instanceRef U2))
(portRef I0_A (instanceRef U7))))
(net A3_1
(joined
(portRef I0_D (instanceRef U2))
(portRef I0_D (instanceRef U3))))
(net A3_NAND_B3_1
(joined
(portRef O_D (instanceRef U3))
(portRef I1_B (instanceRef U4))))
(net A3_NOR_B3_1
(joined
(portRef I_B (instanceRef U1))
(portRef O_D (instanceRef U2))))
(net B0_1
(joined
(portRef I1_A (instanceRef U2))
(portRef I1_A (instanceRef U3))))
(net B1_1
(joined
(portRef I1_B (instanceRef U2))
(portRef I1_B (instanceRef U3))))
(net B2_1
(joined
(portRef I1_C (instanceRef U2))
(portRef I1_C (instanceRef U3))))
(net B3_1
(joined
(portRef I1_D (instanceRef U2))
(portRef I1_D (instanceRef U3))))
(net CBARABARRBARRBARYBAR_BARIBARNBAR_1
(joined
(portRef I_F (instanceRef U1))
(portRef O_A (instanceRef U1))
(portRef I0_B (instanceRef U5))
(portRef I0_A (instanceRef U6))
(portRef I0_A (instanceRef U9))))
(net CARRY_IN_1
(joined
(portRef I_A (instanceRef U1))))
(net GND
(joined
(portRef GND (instanceRef U1))
(portRef GND (instanceRef U2))
(portRef GND (instanceRef U3))
(portRef GND (instanceRef U4))
(portRef GND (instanceRef U5))
(portRef GND (instanceRef U6))
(portRef GND (instanceRef U7))
(portRef GND (instanceRef U8))
(portRef GND (instanceRef U9))
(portRef GND (instanceRef U10))
(portRef GND (instanceRef U11))))
(net S0_1
(joined
(portRef O_A (instanceRef U11))))
(net S1_1
(joined
(portRef O_B (instanceRef U11))))
(net S2_1
(joined
(portRef O_C (instanceRef U11))))
(net S3_1
(joined
(portRef O_D (instanceRef U11))))
(net VCC
(joined
(portRef VCC (instanceRef U1))
(portRef VCC (instanceRef U2))
(portRef VCC (instanceRef U3))
(portRef VCC (instanceRef U4))
(portRef VCC (instanceRef U5))
(portRef VCC (instanceRef U6))
(portRef VCC (instanceRef U7))
(portRef VCC (instanceRef U8))
(portRef VCC (instanceRef U9))
(portRef VCC (instanceRef U10))
(portRef VCC (instanceRef U11))))
(net NET10_1
(joined
(portRef O_D (instanceRef U1))
(portRef I0_B (instanceRef U9))))
(net NET11_1
(joined
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(portRef I1_A (instanceRef U10))))
(net NET12_1
(joined
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(portRef I0_D (instanceRef U4))))
(net NET13_1
(joined
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(portRef I2_A (instanceRef U8))))
(net NET14_1
(joined
(portRef O_C (instanceRef U4))
(portRef I1_A (instanceRef U8))))
(net NET15_1
(joined
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(portRef I0_B (instanceRef U4))))
(net NET16_1
(joined
(portRef O_A (instanceRef U6))
(portRef I3_A (instanceRef U7))))
(net NET17_1
(joined
(portRef O_A (instanceRef U5))
(portRef I2_A (instanceRef U7))))
(net NET18_1
(joined
(portRef O_A (instanceRef U4))
(portRef I1_A (instanceRef U7))))
(net NET1_1
(joined
(portRef O_F (instanceRef U1))
(portRef I0_A (instanceRef U11))))
(net NET2_1
(joined
(portRef O_A (instanceRef U7))
(portRef I1_D (instanceRef U11))))
(net NET3_1
(joined
(portRef O_B (instanceRef U4))
(portRef I0_D (instanceRef U11))))
(net NET4_1
(joined
(portRef O_A (instanceRef U8))
(portRef I1_C (instanceRef U11))))
(net NET5_1
(joined
(portRef O_D (instanceRef U4))
(portRef I0_C (instanceRef U11))))
(net NET6_1
(joined
(portRef O_A (instanceRef U10))
(portRef I1_B (instanceRef U11))))
(net NET7_1
(joined
(portRef O_B (instanceRef U9))
(portRef I0_B (instanceRef U11))))
(net NET8_1
(joined
(portRef O_C (instanceRef U9))
(portRef I1_A (instanceRef U11))))
(net NET9_1
(joined
(portRef O_E (instanceRef U1))
(portRef I0_C (instanceRef U9))))))))
(design MULTIPLY
(cellRef MULTIPLY
(libraryRef MAIN_LIB))))
Article: 97130hi, thanks a lot for the information. i'll try the books you've suggested. any comments on the book "Advanced Digital Design with the Verilog" is very much appreciated. thank you CMOSArticle: 97131
Paul Hollingworth wrote: <snip> > Secondly, the logic fabric of HC II allows for much > higher performance in comparison with the initial FPGA than HC-Stratix > did. This gives us more margin in meeting timing and means it's much > easier to get timing closure when doing final routing of the HC II > device. This is going to translate into shorter conversion times. Carefull, if customers hear that, you know what they are going to ask a) Can we please have the faster speed, sir ? b) Since this is such a doddle, the NRE costs will plumet too, right ? Only the unreasonable ones would expect both at the same time.. :) -jgArticle: 97132
Thanks a lot Paul. Sure helps. But gives rise to a couple more technical questions in my mind that I hope you'll be able to clarify. My understanding is that HardCopy II makes use of fine-grained architecture blocks known as HCells. Precharacterized HCell macros form a library of various Stratix II ALM and DSP block configurations. If my understanding is correct,looks like two kinds of customizations would be required in HardCopy II: one, customization within each HCell macro and two, customization to route together all HCell macros/memory blocks. Here are my questions: 1. Are the fine-grained structures within a HCell macro interconnected using layers like via4/metal5/via5/metal6/via6? Does this potentially give rise to any electrical reliability issues because perhaps a lot of vias (via4 on via3 on via2 on via1) need to be stacked to form even local connections (say between fine-grained structures like NAND gates, inverters, transistors etc.)? 2. Is the MultiTrack routing architecture of Stratix II (R4/R24/C4/C16 etc.) preserved in HardCopy II? Is the global routing (between HCell macros/memory blocks) carried out using customer metal layers 5 and 6? 3. Can using only two metal layers for both local routing (within HCell macros) and global routing (between HCell macros/memory blocks) routing cause problems during migration because of congestion issues? Can the migration be unsuccessful for certain designs? I understand that in raising the above questions I am making certain assumptions regarding HarCopy II implementation which may not be correct and I apologize for that. Any clarification would be very helpful. Thanks again.Article: 97133
Hi, You should be able to use Altera's Quartus II for carrying out this simulation. There is a free web edition of Quartus II at http://www.altera.com/products/software/products/quartus2web/sof-quarwebmain.html I do know that Quartus II accepts edif as input. But you would have to specify how the gates in your edif map to Quartus II logic functions. For that I think you'll need to create a library mapping file (.lmf). Install Quartus II and then look for instructions on how to do this in 'Help-Index'. For some CAD tools there are already existing .lmf files that specify the mapping to Quartus II logic functions but I don't know if one exists corresponding to the CAD tool that generated your edif. Of course you can also try creating a schematic for your adder design using the Quartus II schematic editor itself and perhaps that may be easier than trying to use your edif file. Good luck!Article: 97134
I think the ultimate thing to do would be making my CAD design directly responsible for the input, so that I can not only vaidate the design but the connections in my schematic. Creating a PCB that doesn't work is one thing, soldering around a hundred gates to it is another! :) Thanks. I'm downloading it right now, but for some reason the connection reset at 166MB. :(Article: 97135
I will hope what Xilinx is not worse than Altera. :-) Why do I ask this question? Last time I see (at many sites) advertisement "FREE LICENSE ..." and next by very very small letters "... for 6 months".Article: 97136
Hi all.
I have to import a text file in my handel-C source code.
The content of the file .txt is an integer.
To import the text file, without using chanin and extern keywords, I thought
to create a file in C
language as follows:
---
/* c_file.c */
#include <stdio.h>
unsigned int test()
{
unsigned int x;
FILE *fp;
fp=fopen("test.txt","r");
x=getc(fp);
fclose(fp);
return x;
}
---
and my handel-C source code is:
---
set clock=external "P182";
#include "c_file.c"
void main(void)
{
chanout output; // only for debug
unsigned 16 y;
y=test();
output ! y;
}
---
In Debug mode, when i build the project, i see this error:
stdio.h Ln 275, Col 35-42: Syntax error before '_filbuf'
stdio.h Ln 275, Col 35-42: Syntax error
The compiling process of the only c_file.c is right
Anyone can help me, please??????????
Thanks a lot!
Article: 97137Do you use any special software tools for reading the .bit file and flash image? "Gabor" <gabor@alacron.com> wrote in message news:1140108297.431410.245210@z14g2000cwz.googlegroups.com... > > mughat wrote: >> I have a problem width my CPLD-SPI_flash configuration system. >> >> I have made a configuration interface for my Spartan 3 FPGA involving a >> CPLD >> (CoolRunner 2) and SPI flash (M25P32). >> >> My FPGA is set up to serial master configuration mode. The FPGA is >> generating the clock for the CPLD and the CPLD transfers the data from >> the >> SPI flash to the DIN pin on the FPGA. I use the application notes and >> source >> code xapp800 from Xilinx. >> >> I monitor the CPLD and it steps through states (1-4): >> 1 STATE_RESET >> 2 LOAD_READ_OPCODE >> 3 LOAD_READ_ADDRESS >> 4 READ_DATA >> 5 WAIT_STATE >> >> The CPLD stays in state 4 where it waits for the FPGA to indicate >> configuration done by pulling the DONE pin high. >> >> The hardware seams to work. I can see the data on the DIN pin of the FPGA >> but the FPGA never indicates configuration done by pulling the DONE pin >> high. >> >> I think the problem may be the process of converting the .bit file to a >> format that can be written to the serial flash. >> >> Anyone that have any suggestions on how to find the problem? > > The first thing I always check is the bit order within bytes. Make > sure the SPI isn't swapping your bits, or try swapping bits when you > create the SPI flash image. > >> >> Andreas Beier >> Computer Systems Engineer >Article: 97138
Hi there
I am using a Micron verilog behavioaral mdoel for SDRAM MT48LC16M16A2
which is rated for CL=2 and I want to adapt the timings to verify a
Mobile RAM which provides timings (tCK3, tAC3 etc.) for CL=3. How can I
do it safely?
Thanks in advance to who'll reply
task set_<my mem>_timing;
begin
// Special timing for -75, CAS Latency = 3, tAC = 7.4ns!
tAC = 7.4;
tCK2 = 7.5; // tCK for CL=2
tHZ = 5.4;
tOH = 3.0;
tOH2 = 1.8; // Just enough...
tMRD = 2.0; // 2 Clk Cycles
tRAS = 45.0;
tRC = 65.0;
tRCD = 20.0;
tRFC = 66.0;
tRP = 20.0;
tRRD = 15.0;
tWRa = 7.0; // A2 Version - Auto precharge mode (1 Clk + 7
ns)
tWRp = 14.0; // A2 Version - Manual precharge mode (14 ns)
end
endtask
Article: 97139Good day to all, Does anyone know of any peculiarities concerning the measurement of the standby current of a DDR RAM? I was thinking of measuring the standby current like I do for a regular IC module; setting all data inputs to ground/vdd and placing a small resistor in the path to ground. In this manner, the resistor's voltage drop can be used to extrapolate the standby current. Perphaps, amplifying the resistor's voltage drop can increase the measurement accuracy... Given that I know relatively little about DDRs (I will research them after I post this post), I was wondering if this typical standby current measurement setup will be apllicable for DDRs. After all, DDRs operate in standby with clocks in the 100's of MHz and standby currents in the order of 10's of mA. Any help will be appreciated. The DDR (to be tested) in question is unknown for the moment. Regards, RogerArticle: 97140
Hello,
I'm trying to pack something into two SLICEs and the tools don't get it
... I get map error. And it should be possible to do what I want since I
can "draw" it in the FPGA editor.
(I'm using ISE7.1 sp4 and I target spartan 3)
What I'm trying to pack a a dualport distributedram (RAM16X1D) and a 5:1
mux in two slicesM, one above the other.
On the first slice (top one) is the classic RAM16x1D stuff. On this same
slice, I want to place a F5Mux between the two output of the DRAM,
commanded by BX (actually, BX will be forced to 1, I just want the
second output of the distributed ram on the F5 output pin).
On the second slice (bottom one), I get a 4:1 mux done with the two LUTs
+ the F5 on the slice. And on the same slice, I want to use the FX mux
to mux between either the output of the F5 of this slice, or the F5 out
pin of the slice above.
The VHDL code I write as test is givent at the end of the post and also
available there : http://pastebin.com/559361
The error I get :
---
ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=reg,
RLOC=X0Y1)
which require the combination of the following symbols into a single
SLICEM
component:
RAMDP symbol "memcell_I" (Output Signal = dob_i)
MUXF5 symbol "f5_I" (Output Signal = fxb)
The function generator memcell_I is unable to be placed in the G position
because the output signal doesn't match other symbols' use of the G
signal.
The signal dob_i already uses G. Please correct the design constraints
accordingly.
----
Any idea how to make the tool understand ???
Sylvain
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity reg_cell is
port (
di : in std_logic;
we : in std_logic;
doa : out std_logic;
dob : out std_logic;
addr_a : in std_logic_vector(3 downto 0);
addr_b : in std_logic_vector(3 downto 0);
imm : in std_logic_vector(3 downto 0);
sel_imm : in std_logic_vector(1 downto 0);
sel_ad : in std_logic;
sel_op : in std_logic;
clk : in std_logic
);
end reg_cell;
architecture rtl of reg_cell is
signal doa_i : std_logic;
signal dob_i : std_logic;
signal fxa : std_logic;
signal fxb : std_logic;
attribute U_SET : string;
attribute RLOC : string;
attribute U_SET of memcell_I : label is "reg";
attribute U_SET of f5_I : label is "reg";
attribute U_SET of f6_I : label is "reg";
attribute RLOC of f6_I : label is "X0Y0";
attribute RLOC of f5_I : label is "X0Y1";
attribute RLOC of memcell_I : label is "X0Y1";
begin
with sel_imm select
fxa <= imm(0) when "00",
imm(1) when "01",
imm(2) when "10",
imm(3) when "11",
'-' when others;
doa <= doa_i;
memcell_I: RAM16X1D
port map (
DPO => dob_i,
SPO => doa_i,
A0 => addr_a(0),
A1 => addr_a(1),
A2 => addr_a(2),
A3 => addr_a(3),
D => di,
DPRA0 => addr_b(0),
DPRA1 => addr_b(1),
DPRA2 => addr_b(2),
DPRA3 => addr_b(3),
WCLK => clk,
WE => we
);
f5_i: MUXF5
port map (
O => fxb,
I0 => dob_i,
I1 => doa_i,
S => sel_ad
);
f6_i: MUXF6
port map (
O => dob,
I0 => fxb,
I1 => fxa,
S => sel_op
);
end rtl;
Article: 97141Hello I have to make an connection to a FPGA-borad. http://www.celoxica.com/products/rc300/default.asp This board only supports ethernet communication with the mac-layer. Now I have to build an app that can send data(in my case images) to the board. My question is now how can i send data using the mac-layer only from a c++ programm. I do not think that we are using(or is possible to use) a router/switch between the pc and the board, we will use an pachted-ethernet-cable. thanksArticle: 97142
"Sylvain Munaut" <com.246tNt@tnt> wrote in message news:43f5c215$0$19097$ba620e4c@news.skynet.be... > Hello, > > I'm trying to pack something into two SLICEs and the tools don't get it > ... I get map error. And it should be possible to do what I want since I > can "draw" it in the FPGA editor. > (I'm using ISE7.1 sp4 and I target spartan 3) > > What I'm trying to pack a a dualport distributedram (RAM16X1D) and a 5:1 > mux in two slicesM, one above the other. > Hi Sylvain, Does it help to use the floorplanner after translate? So, remove your RLOCs from the code. Run Translate. Run the floorplanner. Place the parts on the floorplan. Export a UCF file? Just a thought. Good luck, Syms.Article: 97143
Symon wrote: > "Sylvain Munaut" <com.246tNt@tnt> wrote in message > news:43f5c215$0$19097$ba620e4c@news.skynet.be... > >>Hello, >> >>I'm trying to pack something into two SLICEs and the tools don't get it >>... I get map error. And it should be possible to do what I want since I >>can "draw" it in the FPGA editor. >>(I'm using ISE7.1 sp4 and I target spartan 3) >> >>What I'm trying to pack a a dualport distributedram (RAM16X1D) and a 5:1 >>mux in two slicesM, one above the other. >> > > Hi Sylvain, > Does it help to use the floorplanner after translate? > > So, remove your RLOCs from the code. Run Translate. Run the floorplanner. > Place the parts on the floorplan. Export a UCF file? > Just a thought. > Good luck, Syms. > > Nope, the floorplanner don't let me put the memcell in the same couple of slice as the F6 mux contruct. I'm investigating how to create a hardmacro now, see if that would work. SylvainArticle: 97144
ada wrote: [snip] > > I am just a bit confused - among all nets in original UCF file I have > CLK_DDR_FB_IN and CLK_DDR_FB_OUT. In my design I am using only > CLK_DDR_FB_IN for giving my feedback signal to DDR. Should I use both? I > do not see any reason for it. Usually the reason for a feadback net is to match board-level delays, so you can automatically adjust your clock phase. Look at the board schematic and see how these nets are hooked up. Maybe you need to drive CLK_DDR_FB_OUT to the DIMM. Which board are you you're using? A quick look at the Avnet site turned up a lot of boards with FG456 package Virtex-II parts, and some with Virtex-II Pro in the FF1152 package. > > Best, > AdaArticle: 97145
I don't usually use the .bit file directly. I use Impact to generate a PROM file in HEX format (or use promgen if you prefer a command line interface). This is a very simple format with just the bitstream and no header. Then I use a simple C program to turn this back into binary for storage in flash. Impact or promgen gives you the choice of swapped or not swapped bits when generating the .hex file. Then if your embedded firmware gets the bit order wrong, you can just re-build the .hex file using the opposite swap mode rather than changing the firmware. A note of warning. Impact 8.1i sp1 (and maybe sp2?) GUI always sets the swap bits mode when generating .hex files, so you need to run promgen from the command line to generate unswapped .hex files. mughat wrote: > Do you use any special software tools for reading the .bit file and flash > image? > > "Gabor" <gabor@alacron.com> wrote in message > news:1140108297.431410.245210@z14g2000cwz.googlegroups.com... > > > > mughat wrote: > >> I have a problem width my CPLD-SPI_flash configuration system. > >> > >> I have made a configuration interface for my Spartan 3 FPGA involving a > >> CPLD > >> (CoolRunner 2) and SPI flash (M25P32). > >> > >> My FPGA is set up to serial master configuration mode. The FPGA is > >> generating the clock for the CPLD and the CPLD transfers the data from > >> the > >> SPI flash to the DIN pin on the FPGA. I use the application notes and > >> source > >> code xapp800 from Xilinx. > >> > >> I monitor the CPLD and it steps through states (1-4): > >> 1 STATE_RESET > >> 2 LOAD_READ_OPCODE > >> 3 LOAD_READ_ADDRESS > >> 4 READ_DATA > >> 5 WAIT_STATE > >> > >> The CPLD stays in state 4 where it waits for the FPGA to indicate > >> configuration done by pulling the DONE pin high. > >> > >> The hardware seams to work. I can see the data on the DIN pin of the FPGA > >> but the FPGA never indicates configuration done by pulling the DONE pin > >> high. > >> > >> I think the problem may be the process of converting the .bit file to a > >> format that can be written to the serial flash. > >> > >> Anyone that have any suggestions on how to find the problem? > > > > The first thing I always check is the bit order within bytes. Make > > sure the SPI isn't swapping your bits, or try swapping bits when you > > create the SPI flash image. > > > >> > >> Andreas Beier > >> Computer Systems Engineer > >Article: 97146
I am not certain I entirely understand what you are asking, but it sounds like you have bits and pieces of various concepts and I think you need to research the components of your system a bit more. You will need to start, by examing the protocol (language) that the device you need to communicate with undestands. Once you have a clear understanding of it, which in this case sounds like the MAC layer in a typical ethernet protocol, you can begin to look at what you will need to connect to it. I suspect you are looking for a form of magic bullet, such as conenct through a router and you will all of a sudden have needed commands at your figertips. Unfortunately, it probably doesn't exist. As far as accessing this with a C++ program, being C++ isn't enough. It will depend on what platform you are using, what tools and libraries you have available, what "level" you are writing you code for (driver, application, etc).Article: 97147
"Roggey" <Roggey@gmail.com> writes: |> I have to make an connection to a FPGA-borad. |> |> http://www.celoxica.com/products/rc300/default.asp |> |> This board only supports ethernet communication with the mac-layer. Now |> I have to build an app that can send data(in my case images) to the |> board. |> |> My question is now how can i send data using the mac-layer only from a |> c++ programm. How to sent UDP packets or establish a TCP connection from C++ depends entirely on your operating system. Under Unix/Linux, you may want to start on the "man 2 socket" manual page and related tutorials. On MacOS, it's probably the same. On the FPGA side: If you have a way to upload a microcontroller into the FPGA, or it has already a built-in processor, and you have a C compiler for it, you can install either a bare-boned TCP/IP stack such as http://savannah.nongnu.org/projects/lwip/ which also supports ARP and DHCP, or even a full embedded operating system such as Linux or Windows CE. Thats the most flexible and luxurious approach. If you want to avoid using a processor, then you can probably forget about using TCP. But decoding UDP packets in hardware may still be very feasible. If your Ethernet it is a point-to-point link, you may want to try sending out UDP packets to IP broadcast addresses. This should be translated into MAC broadcasts and therefore bypasss the entire address-resolution protocol (ARP) mechanism in which your FPGA will not participate. On the decoding end, you will have to hope that the IP packets arrive unfragmented and with constant-length headers (i.e., no options), which is normally the case for UDP packets shorter than ~1.5 kB. Of course all this is a real hack and may fail as soon as anything else gets connected to the same network. But as long as you do not expect Ethernet to run will all the features with which it is used normally, it can be used almost as easily as any other type of serial port. Markus -- Markus Kuhn, Computer Laboratory, University of Cambridge http://www.cl.cam.ac.uk/~mgk25/ || CB3 0FD, Great BritainArticle: 97148
Without real oscilloscope your are lost. How can you see without osci if your DQS and DQ go tristate ? Rgds Andr=E9Article: 97149
What do you mean by last trail? Last mailing list post is Thu Feb 16 Last project created 17-Feb-2006 17:45:28 Guenter
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