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Messages from 94575

Article: 94575
Subject: Re: Attack of the clones
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 13 Jan 2006 14:40:12 -0800
Links: << >>  << T >>  << A >>
Grant,

A bit off your topic, but building any computing machine for your own 
use is perfectly legal.  Oh so it was the last time I checked.

Xerox PARC tried to buy a DEC 10, but DEC wouldn't sell them one.  So, 
Xerox got the schematics, put everyone to work, and built one.  Just 
one.  Used it for research.  Even made their own operating system for it.

Nothing DEC could do:  Xerox PARC did not derive any profit from it, did 
not use it to do any product (and they had the losses to prove it!).

I wonder if today Apple would even care if you went into business 
offering (old) Mac Clones?

As long as you are not using their IP, their patents (and not impacting 
their present business), they really have no reason to care.

An Altair clone?  Why?  So that you could use those old S100 interface 
pcbs?  Run CPM?

Austin


Article: 94576
Subject: Re: how do I minimize the logic in this function?
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 13 Jan 2006 14:42:11 -0800
Links: << >>  << T >>  << A >>
Brannon,

How about a BRAM?  Simple ROM look up table, 6 bits in, 8 bits out.

Austin

Brannon wrote:

> I have an async function with six bits in and eight bits out (listed
> below). I need to minimize the logic usage (in a Virtex2) for this
> function. It appears that most kmap tools will support six bits in but
> only one bit out. Anyone have a tool or method they would recommend to
> help with my problem?
> 
> I do it currently with two three bit subtracters (in LUTs, not
> CarryChain) and a 6bit x 16 element mux (using muxf prims) running as a
> lookup table. The output of one adder drives the mux S input. It just
> takes too much time and space.
> 
> In      Out
> 0       0
> 1       66
> 2       128
> 3       0
> 4       64
> 5       65
> 6       66
> 7       64
> 8       130
> 9       128
> 10      136
> 11      130
> 12      0
> 13      66
> 14      128
> 15      0
> 16      68
> 17      69
> 18      65
> 19      68
> 20      80
> 21      81
> 22      69
> 23      80
> 24      64
> 25      65
> 26      66
> 27      64
> 28      68
> 29      69
> 30      65
> 31      68
> 32      138
> 33      136
> 34      160
> 35      138
> 36      130
> 37      128
> 38      136
> 39      130
> 40      162
> 41      160
> 42      168
> 43      162
> 44      138
> 45      136
> 46      160
> 47      138
> 48      0
> 49      66
> 50      128
> 51      0
> 52      64
> 53      65
> 54      66
> 55      64
> 56      130
> 57      128
> 58      136
> 59      130
> 60      0
> 61      66
> 62      128
> 63      0
> 
> Thanks for your time.
> 

Article: 94577
Subject: what happens in SDR-SDRAM if i exceed tRAS(max)
From: "Subhasri krishnan" <subhasri.krishnan@gmail.com>
Date: 13 Jan 2006 14:54:31 -0800
Links: << >>  << T >>  << A >>
Hi all,
There is a situtation in my controller when tRAS(max) is exceeded. My
controller starts to read out from some row but I am not sure exactly
which one. Does anyone know what row will be opened under this
situation? 
Thanks
Subhasri.K


Article: 94578
Subject: Re: how do I minimize the logic in this function?
From: Alex Freed <alexf@mirrow.com>
Date: Fri, 13 Jan 2006 14:57:29 -0800
Links: << >>  << T >>  << A >>
That's what BRAMs are good for. Unless you are using all of them for
something else, it's a no-brainer.

Brannon wrote:
> I have an async function with six bits in and eight bits out (listed
> below). I need to minimize the logic usage (in a Virtex2) for this
> function. It appears that most kmap tools will support six bits in but
> only one bit out. Anyone have a tool or method they would recommend to
> help with my problem?
> 
> I do it currently with two three bit subtracters (in LUTs, not
> CarryChain) and a 6bit x 16 element mux (using muxf prims) running as a
> lookup table. The output of one adder drives the mux S input. It just
> takes too much time and space.
> 
> In      Out
> 0       0
> 1       66
> 2       128
> 3       0
> 4       64
> 5       65
> 6       66
> 7       64
> 8       130
> 9       128
> 10      136
> 11      130
> 12      0
> 13      66
> 14      128
> 15      0
> 16      68
> 17      69
> 18      65
> 19      68
> 20      80
> 21      81
> 22      69
> 23      80
> 24      64
> 25      65
> 26      66
> 27      64
> 28      68
> 29      69
> 30      65
> 31      68
> 32      138
> 33      136
> 34      160
> 35      138
> 36      130
> 37      128
> 38      136
> 39      130
> 40      162
> 41      160
> 42      168
> 43      162
> 44      138
> 45      136
> 46      160
> 47      138
> 48      0
> 49      66
> 50      128
> 51      0
> 52      64
> 53      65
> 54      66
> 55      64
> 56      130
> 57      128
> 58      136
> 59      130
> 60      0
> 61      66
> 62      128
> 63      0
> 
> Thanks for your time.
> 

Article: 94579
Subject: Re: How to create a delay BUF?
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Fri, 13 Jan 2006 17:03:09 -0600
Links: << >>  << T >>  << A >>


steven wrote:

>Ycan create small delays on signals by passing the signal through a LUT 
>configured to act as a buffer. Here it is in VHDL
>
>LUT_DELAY: LUT1
>generic map(
> INIT => X"10")
>
>port map(
>O => signal_in_delayed,
>I0 => signal_in);
>
>
>  
>
This is a very small delay, maybe about 1 ns on Spartan 2.  One way
I have used to make a much longer delay on a 95xx CPLD that had no
continuous clock was to pass the signal out an output pin and back into
a different input pin.  I put a resistor (about 1.5 K Ohm, in that case,
for about 20 nS of delay) between the two pins.  This, of course, eats
up two whole pins for one delay.  I needed to make something happen
a safe delay after an I/O strobe went away, and this did the trick.  Of
course, where a fast clock is available, there are much more reliable and
predictable ways to do this.

Jon


Article: 94580
Subject: Re: Attack of the clones
From: "logjam" <grant@cmosxray.com>
Date: 13 Jan 2006 15:03:47 -0800
Links: << >>  << T >>  << A >>
Well, all of the old mac websites were sent C&D letters threating them
if they didn't remove system software required to run a mac from 1984.

If you aren't a mac guy already, it would be pretty hard to get one of
those old machines running because of Apple's actions.

Altair clone, because, I don't know...its the Altair!  :)  I want to
make a computer "kit" and have it be useful at the same time.


Article: 94581
Subject: Re: FPGA Journal Article
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Fri, 13 Jan 2006 17:13:19 -0600
Links: << >>  << T >>  << A >>


Kevin Morris wrote:

>I'm writing a feature article for FPGA Journal (www.fpgajournal.com)
>about FPGAs and the re-birth of the electronics hobbyist.  My theory is
>that electronics as a hobby went through a "dark age" period, maybe
>  
>
Well, I'm not really a hobbyist, but a VERY small business (just me, and 
sometimes
a part-timer to help solder boards.)  But, the level of stuff I'm doing 
(in my home
business) is maybe close to hobby level.  You might look at my web pages on
that project, and see if it is of interest : 
http://pico-systems.com/motion.html
All of the "control" or "controller" products have at least one FPGA in 
them.
The PPMC has one FPGA and 2 CPLDs for the basic set.  No way could I have
done these without FPGAs.  I have never used a development board, just 
bludgeoned
ahead with my best guess of what the prototype should look like.  And, 
just 2-layer
boards, too.

Jon


Article: 94582
Subject: Re: Don't even get me started on lead,
From: "dp" <dp@tgi-sci.com>
Date: 13 Jan 2006 15:17:49 -0800
Links: << >>  << T >>  << A >>
Al Clark wrote:

> Just imagine if the billions of dollars being spent on converting
> electronics to lead free could have been spent on something that would
> actually have an impact on improving the environment.
>
> Just a simple, back of the envelope calculation would have shown that this
> whole initiative is crazy.

I would say it only looks crazy. Those politicians who have promoted
this just cannot be that stupid (although if really caught they will
claim
exactly that). Nobody is that stupid. I do not know what this is about,
but it obviously is not what they claim it is. Perhaps it is just
about the money. Perhaps it is a well thought intelligence plan (CIA,
KGB,
you name it) plan to ruin the European electronics industry (which is
not
that much alive anyway). Perhaps something I cannot think of now, can
be
anyones guess. Of course, your original assumption of plain
crazyness/stupidity cannot be ruled out, either....

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------


Article: 94583
Subject: Re: how do I minimize the logic in this function?
From: "Brannon" <brannonking@yahoo.com>
Date: 13 Jan 2006 15:17:58 -0800
Links: << >>  << T >>  << A >>
Okay: lets suppose I use eight ROM64x1 prims. Is that really fewer
recourses and/or comparable in speed to a four bit subtracter plugged
into the switch 6b x 16el mux with constants on all its data? What
resources does a ROM64x1 use?


Article: 94584
Subject: Re: Don't even get me started on lead,
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Fri, 13 Jan 2006 23:23:15 -0000
Links: << >>  << T >>  << A >>
> Nobody is that stupid.

I think you're underestimating the 'ministers' in the European
'parliament'. It's supposed to be the biggest gravy train going,
the auditors have refused to sign the accounts for the last few years!

Still it's only our (anyone who lives in the EU) money that's
paying for the whole debacle.



Nial (not at all cynical).






Article: 94585
Subject: Re: how do I minimize the logic in this function?
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 13 Jan 2006 15:36:58 -0800
Links: << >>  << T >>  << A >>
Brannon,

I am proposing you load up a BRAM with the values you need for the 
addresses you have.

A simple large table lookup.  Done in one cycle.  Uses one BRAM block, 
but, do you sue them anyway?  Do you have a spare one?

Sure it is more real estate than just about every other method, but it 
is fast, and simple.  And if you have any unused BRAMs lying about, it 
is done.

Austin

Brannon wrote:

> Okay: lets suppose I use eight ROM64x1 prims. Is that really fewer
> recourses and/or comparable in speed to a four bit subtracter plugged
> into the switch 6b x 16el mux with constants on all its data? What
> resources does a ROM64x1 use?
> 

Article: 94586
Subject: Re: Attack of the clones
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sat, 14 Jan 2006 12:48:35 +1300
Links: << >>  << T >>  << A >>
logjam wrote:

> Well, all of the old mac websites were sent C&D letters threating them
> if they didn't remove system software required to run a mac from 1984.
> 
> If you aren't a mac guy already, it would be pretty hard to get one of
> those old machines running because of Apple's actions.

  You could write to Steve, and tell him what you are trying to do ?

  Ponders: With the new Intel MACs, and Linux FPGA tools, how close are
we to being able to do a FPGA build of a MAC, on an Apple PC ?
  [ Apple's marketing guys could love that.... ]


  Mention that more enlightened companies, like Borland
- and even (gasp) Microsoft have Museum policies, where you can
either download, or freely use, some of their really old software.
  Some companies are proud of their heritage..... and the WEB is
ideal for this type of repositry.

  In some cases is it just a lawyer reflex, or they may be worried about
possible support questions, but the commercial impact is going to be Nil.

  -jg


Article: 94587
Subject: Re: Xilinx Virtex-4 BRAM-16 Simulation
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Fri, 13 Jan 2006 15:55:28 -0800
Links: << >>  << T >>  << A >>

Thanks for words of encouragement Ray.

I went back to double check if all the simulation
and libraries were downloaded and installed. It
seems as if they are.  All from the download page
that Xilinx is advertising on the home page right
now for the 8.i software. Three packages in all,
the ISE, ModelSim III, and it's library.

I am still not getting any output from the RAMB16
primitive.  Seems to get stuck on the 0th address.
I have wiggled all the signals but I all I can see is
is the init value and the 0th address value.  Please
take a look at my wrapper file and I also included
the VHDL generated from the Waveform tool after
the Generate Expected Value option. I know it is
probably some silly mistake.

Brad Smallridge aivision

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity bram9p is
 port (
   clkb   :  IN std_logic;
   enb    :  IN std_logic;
   ssrb   :  IN std_logic;
   regceb :  IN std_logic;
   addrb  :  IN std_logic_VECTOR(14 downto 0);
   web    :  IN std_logic_VECTOR( 3 downto 0);
   doutb  : OUT std_logic_VECTOR(31 downto 0) );
end bram9p;

architecture Behavioral of bram9p is

begin

   -- RAMB16: Virtex-4 16k+2k Parity Paramatizable BlockRAM
   -- Xilinx  HDL Language Template version 8.1i
   RAMB16_inst : RAMB16
   generic map (
      DOA_REG => 0, -- Optional output registers on the A port (0 or 1)
      DOB_REG => 0, -- Optional output registers on the B port (0 or 1)
      INIT_A => X"000000000", --  Initial values on A output port
      INIT_B => X"000000003", --  Initial values on B output port
      INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output 
registers (TRUE or FALSE)
      INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output 
registers (TRUE or FALSE)
      RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
      RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
      READ_WIDTH_A => 36, -- Valid values are 1,2,4,9,18 or 36
      READ_WIDTH_B => 36, -- Valid values are 1,2,4,9,18 or 36
      SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", 
"WARNING_ONLY", "GENERATE_X_ONLY
                                   -- or "NONE
      SRVAL_A => X"000000000", --  Port A ouput value upon SSR assertion
      SRVAL_B => X"CCCCCCABC", --  Port B ouput value upon SSR assertion
      WRITE_MODE_A => "READ_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      WRITE_MODE_B => "READ_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      WRITE_WIDTH_A => 36, -- Valid values are 1,2,4,9,18 or 36
      WRITE_WIDTH_B => 36, -- Valid values are 1,2,4,9,18 or 36
      -- The following INIT_xx declarations specify the initial contents of 
the RAM
      INIT_00 => 
X"00D00A0100010B01000100010001000100010001000100010001DEAD00100112",
      INIT_01 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => 
X"00D00A0100010B01000100010001000100010001000100010001DEAD00100112",
      -- The next set of INITP_xx are for the parity bits
      INITP_00 => 
X"00D00A0100010B01000100010001000100010001000100010001DEAD00100112",
      INITP_01 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => 
X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => 
X"00D00A0100010B01000100010001000100010001000100010001DEAD00100112")
   port map (
      CASCADEOUTA => open,                  -- 1-bit cascade output
      CASCADEOUTB => open,                  -- 1-bit cascade output
      DOA         => open,                  -- 32-bit A port Data Output
      DOB         => doutb(31 downto 0),    -- 32-bit B port Data Output
      DOPA        => open,                  -- 4-bit  A port Parity Output
      DOPB        => open,                  -- 4-bit  B port Parity Output
      ADDRA       => (others=>'0'),         -- 15-bit A port Address Input
      ADDRB       => addrb(14 downto 0),    -- 15-bit B port Address Input
      CASCADEINA  => '0',                   -- 1-bit cascade A input
      CASCADEINB  => '0',                   -- 1-bit cascade B input
      CLKA        => '0',                   -- Port A Clock
      CLKB        => clkb,                  -- Port B Clock
      DIA         => (others=>'0'),         -- 32-bit A port Data Input
      DIB         => (others=>'0'),         -- 32-bit B port Data Input
      DIPA        => (others=>'0'),         -- 4-bit  A port parity Input
      DIPB        => (others=>'0'),         -- 4-bit  B port parity Input
      ENA         => '0',                   -- 1-bit  A port Enable Input
      ENB         => enb,                   -- 1-bit  B port Enable Input
      REGCEA      => '0',                   -- 1-bit A port register enable 
input
      REGCEB      => regceb,                -- 1-bit B port register enable 
input
      SSRA        => '0',                   -- 1-bit  A port Synchronous 
Set/Reset Input
      SSRB        => ssrb,                  -- 1-bit  B port Synchronous 
Set/Reset Input
      WEA         => "0000",                -- 4-bit  A port Write Enable 
Input
      WEB         => web );                 -- 4-bit  B port Write Enable 
Input

end Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY waveform IS
END waveform;

ARCHITECTURE testbench_arch OF waveform IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

    COMPONENT bram9p
        PORT (
            clkb : In std_logic;
            enb : In std_logic;
            ssrb : In std_logic;
            regceb : In std_logic;
            addrb : In std_logic_vector (14 DownTo 0);
            web : In std_logic_vector (3 DownTo 0);
            doutb : Out std_logic_vector (31 DownTo 0)
        );
    END COMPONENT;

    SIGNAL clkb : std_logic := '0';
    SIGNAL enb : std_logic := '0';
    SIGNAL ssrb : std_logic := '0';
    SIGNAL regceb : std_logic := '0';
    SIGNAL addrb : std_logic_vector (14 DownTo 0) := "000000000000000";
    SIGNAL web : std_logic_vector (3 DownTo 0) := "0000";
    SIGNAL doutb : std_logic_vector (31 DownTo 0) := 
"UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 200 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 0 ns;

    BEGIN
        UUT : bram9p
        PORT MAP (
            clkb => clkb,
            enb => enb,
            ssrb => ssrb,
            regceb => regceb,
            addrb => addrb,
            web => web,
            doutb => doutb
        );

        PROCESS    -- clock process for clkb
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                clkb <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                clkb <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS
            PROCEDURE CHECK_doutb(
                next_doutb : std_logic_vector (31 DownTo 0);
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (doutb /= next_doutb) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns doutb="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, doutb);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_doutb);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.writeline(RESULTS, TX_LOC);
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            BEGIN
                -- -------------  Current Time:  85ns
                WAIT FOR 85 ns;
                ssrb <= '1';
                addrb <= "000000000000001";
                -- -------------------------------------
                -- -------------  Current Time:  115ns
                WAIT FOR 30 ns;
                CHECK_doutb("00000000000000000000000000000011", 115);
                -- -------------------------------------
                -- -------------  Current Time:  285ns
                WAIT FOR 170 ns;
                ssrb <= '0';
                addrb <= "000000000000010";
                -- -------------------------------------
                -- -------------  Current Time:  485ns
                WAIT FOR 200 ns;
                enb <= '1';
                addrb <= "000000000000011";
                -- -------------------------------------
                -- -------------  Current Time:  515ns
                WAIT FOR 30 ns;
                CHECK_doutb("00000000000100000000000100010010", 515);
                -- -------------------------------------
                -- -------------  Current Time:  685ns
                WAIT FOR 170 ns;
                regceb <= '1';
                addrb <= "000000000000100";
                -- -------------------------------------
                -- -------------  Current Time:  885ns
                WAIT FOR 200 ns;
                addrb <= "000000000000101";
                -- -------------------------------------
                -- -------------  Current Time:  1085ns
                WAIT FOR 200 ns;
                regceb <= '0';
                addrb <= "000000000000110";
                -- -------------------------------------
                -- -------------  Current Time:  1285ns
                WAIT FOR 200 ns;
                enb <= '0';
                addrb <= "000000000000111";
                -- -------------------------------------
                -- -------------  Current Time:  1485ns
                WAIT FOR 200 ns;
                regceb <= '1';
                addrb <= "000000000001000";
                -- -------------------------------------
                -- -------------  Current Time:  1685ns
                WAIT FOR 200 ns;
                regceb <= '0';
                addrb <= "000000000001001";
                -- -------------------------------------
                -- -------------  Current Time:  1885ns
                WAIT FOR 200 ns;
                addrb <= "000000000001010";
                web <= "1111";
                -- -------------------------------------
                -- -------------  Current Time:  2085ns
                WAIT FOR 200 ns;
                enb <= '1';
                addrb <= "000000000001011";
                -- -------------------------------------
                -- -------------  Current Time:  2285ns
                WAIT FOR 200 ns;
                enb <= '0';
                regceb <= '1';
                addrb <= "000000000001100";
                -- -------------------------------------
                -- -------------  Current Time:  2485ns
                WAIT FOR 200 ns;
                regceb <= '0';
                addrb <= "000000000001101";
                -- -------------------------------------
                -- -------------  Current Time:  2685ns
                WAIT FOR 200 ns;
                addrb <= "000000000001110";
                web <= "0000";
                -- -------------------------------------
                -- -------------  Current Time:  2885ns
                WAIT FOR 200 ns;
                addrb <= "000000000001111";
                -- -------------------------------------
                -- -------------  Current Time:  3085ns
                WAIT FOR 200 ns;
                addrb <= "000000000010000";
                -- -------------------------------------
                -- -------------  Current Time:  3285ns
                WAIT FOR 200 ns;
                ssrb <= '1';
                addrb <= "000000000010001";
                -- -------------------------------------
                -- -------------  Current Time:  3485ns
                WAIT FOR 200 ns;
                ssrb <= '0';
                addrb <= "000000000010010";
                -- -------------------------------------
                -- -------------  Current Time:  3685ns
                WAIT FOR 200 ns;
                addrb <= "000000000010011";
                -- -------------------------------------
                -- -------------  Current Time:  3885ns
                WAIT FOR 200 ns;
                addrb <= "000000000010100";
                -- -------------------------------------
                -- -------------  Current Time:  4085ns
                WAIT FOR 200 ns;
                addrb <= "000000000010101";
                -- -------------------------------------
                -- -------------  Current Time:  4285ns
                WAIT FOR 200 ns;
                addrb <= "000000000010110";
                -- -------------------------------------
                -- -------------  Current Time:  4485ns
                WAIT FOR 200 ns;
                addrb <= "000000000010111";
                -- -------------------------------------
                -- -------------  Current Time:  4685ns
                WAIT FOR 200 ns;
                addrb <= "000000000011000";
                -- -------------------------------------
                -- -------------  Current Time:  4885ns
                WAIT FOR 200 ns;
                addrb <= "000000000011001";
                -- -------------------------------------
                WAIT FOR 315 ns;

                IF (TX_ERROR = 0) THEN
                    STD.TEXTIO.write(TX_OUT, string'("No errors or 
warnings"));
                    STD.TEXTIO.writeline(RESULTS, TX_OUT);
                    ASSERT (FALSE) REPORT
                      "Simulation successful (not a failure).  No problems 
detected."
                      SEVERITY FAILURE;
                ELSE
                    STD.TEXTIO.write(TX_OUT, TX_ERROR);
                    STD.TEXTIO.write(TX_OUT,
                        string'(" errors found in simulation"));
                    STD.TEXTIO.writeline(RESULTS, TX_OUT);
                    ASSERT (FALSE) REPORT "Errors found during simulation"
                         SEVERITY FAILURE;
                END IF;
            END PROCESS;

    END testbench_arch;


 



Article: 94588
Subject: Re: OT: RoHS and Lead?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sat, 14 Jan 2006 13:03:49 +1300
Links: << >>  << T >>  << A >>
Al Clark wrote:

> "Martin" <0_0_0_0_@pacbell.net> wrote in
> news:XiBxf.287$or4.4@newssvr12.news.prodigy.com: 
> 
> 
>>Excuse the OT post, but I figured people in this group may have an
>>answer for this odd question:
>>
>>In transitioning to RoHS, can you mix Lead-free parts into a standard
>>PbSn process?  The idea is to start buying RoHS parts while depleting
>>the existing stock of PbSn components.
>>
>>Good? Bad? Ugly?
>>
>>Thanks,
>>
> 
> 
> You are going to have no real problems soldering leadfree parts with tin-
> lead solder. The big exception to this are BGAs. The ball of a BGA is 
> solder. If it is leadfree, it will need to be soldered at a higher 
> temperature. You CM will need to know this.
> 
> Many parts have been supplied leadfree for several years. This includes 
> many of the passives that you probably are already using. They might not 
> have been labeled as such.
> 
> We have started using lead free pcbs as well. In our case we have opted for 
> ENIG (electroless nickel/immersion gold). They are easy to solder with PbSn
> 
> No one really knows the long term effects of moving to RoHS. I am hoping 
> that the EU decides that July is too soon since industry is not really 
> ready. Nevertheless, I think it is prudent to plan for it to happen. For 
> example, try buying Altera PLDs. They seem to be readily available in lead 
> but not available in the lead free versions (of course, Altera claims they 
> have both). Part of this situation is caused because everyone 
> (distributors, manufacturers, etc) wants to get rid of their non RoHs 
> inventory. It's hardest on those of us on the end of the chain, since we 
> have the least amount of time to transition.
> 
> I think one of the biggest problems will be for products that have 
> relatively long lives and small volume. I have already seen parts that were 
> discontinued just because the mfr didn't want to change to a lead free 
> process. How many designs will have to be completely redone, just to deal 
> with a part that has been obsoleted prematurely. Even if you could buy 
> enough existing material, you still couldn't ship the existing design 
> because there it will never be a RoHS compliant part.

  I think there are enough escape clauses in the RoHS, that you do not
have to terminate and dump a product line, due to one non complying part.
  If you can prove that there IS no lead free alternative (yet), ( and
that you are diligent in using lead Free, where avaialable) then
that's one path.

  Another is that a single part, in a Lead-free flow, is unlikely to
trigger lead threshold alarms.
  Product reliability is a different question....

-jg



Article: 94589
Subject: Re: how do I minimize the logic in this function?
From: "Brannon" <brannonking@yahoo.com>
Date: 13 Jan 2006 16:11:14 -0800
Links: << >>  << T >>  << A >>
"one cycle" is the whole issue. I don't have any spare cycles. This has
to be done asynchronously.


Article: 94590
Subject: Re: FPGA Journal Article
From: Eric Smith <eric@brouhaha.com>
Date: 13 Jan 2006 16:16:11 -0800
Links: << >>  << T >>  << A >>
"Peter Alfke" <peter@xilinx.com> writes:
> I have struggled for decades to come up with enticing demo projects for
> digital circuits, and I have made my rules:
> It must be something that cannot be done with just a microprocessor.
> That means it must be something fast. Audio, video, radio, robotics
> come to mind.

What?  No traffic lights and vending machines?  :-)

It's always entertaining when people pop up in various newsgroups
(including this one), wanting help with their vending machine project,
and insisting that it isn't homework.

Article: 94591
Subject: Re: Don't even get me started on lead,
From: Roel <electronics_designer@hotmail.com>
Date: Sat, 14 Jan 2006 01:21:57 +0100
Links: << >>  << T >>  << A >>
dp wrote:
 >
 > This whole ROHS thing is such an idiotic thing to do that it
 > is really frightening how easy it was to drag the whole industry
 > into it...
 >

Austin Lesea wrote:
 > There is absolutely no reason to go through this nonsense when
 > automotive lead acid car batteries are thrown away by the roadside and
 > in landfills every day...

Al Clark wrote:
 > Just imagine if the billions of dollars being spent on converting
 > electronics to lead free could have been spent on something that would
 > actually have an impact on improving the environment.
 >
 > Just a simple, back of the envelope calculation would have shown that 
this
 > whole initiative is crazy.
 >

First of all: ROHS is not only about Lead! Itís also about mercury, 
cadmium, hexavalent chromium, PBB or PBDE, etc.

It's amazing that there are still people saying that such substances may 
just be dumped permanently in the environment that should be the 
environment for the next million years of civilization.

There is done amazingly much research of the effect to humans of these 
kinds of substances in the environment. Read the background stories of 
RoHS and WEEE and you probably finally will understand it all. And yes 
there is much more to do, but this is a very good start.

The EU was late already with these kind of regulations. Japan was 
smarter already for years. Lucky enough China is the first big one to 
follow. It's a shame that US, far the largest polluter in the world, 
still hasn't regulations in this area (the only serious exception is 
California).

Roel







Article: 94592
Subject: Re: FPGA Journal Article
From: Eric Smith <eric@brouhaha.com>
Date: 13 Jan 2006 16:23:44 -0800
Links: << >>  << T >>  << A >>
Francesco wrote:
> (even if I think that the starter kit are still too expensive for
> people that want electronics as an hobby)

I can't claim to know the economics of hobbyists elsewhere in the world,
but IMNSHO in the US, someone who can't afford to spend USD $99 on
something needed for their hobby doesn't realy qualify as a "hobbyist".
People routinely spend orders of magnitude more than that on hobbies
other than electronics.

And yes, I remember back when I was a starving college student.  Even
then I managed to spend much more than $99/year on hobby items, though
perhaps I shouldn't have.

One guy I knew back then complained that he couldn't afford a $100
computer (a Timex/Sinclair or the like), even though he typically spent
well over $100 per month on accessorizing his sports car.  It's a matter
of priorities.

Article: 94593
Subject: Re: A Better Way?
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Fri, 13 Jan 2006 16:26:27 -0800
Links: << >>  << T >>  << A >>

Austin Lesea wrote:

> Ray,
> I know, I know!
> We are really open to any good ideas.

It's not that complicated.

First, Xilinx needs more examples.

Every release of a board, silicon, or software version should have
an example tutorial of every basic component that a beginner would
use.  Right now Xilinx has a tutorial on how to simulate a counter.
Whoop-De-Doo.  There should be a tuorial on every simple component,
fifos, serial ports, brams, iserdes, etc.  Probably about 50 basic componets
would suffice.  Now that's a lot of writing, but it's probably more 
expensive
having your case support people supporting everybody individually. And
the software would be tested when it left the factory.

Second,  the support should be open.  This case stuff doesn't help. Xilinx
wants to route all these cases to an engineer that can answer the question,
good luck.  I have submitted three cases in the past two weeks and not 
gotten
anything constructive.  I have just discovered your forums but I see there
isn't too much traffic there.  I use to get answers from Xilinx engineers 
here
 on comp.arch.fpga. Have they been gaged?

In terms of the old answers, and multitude of the information, I would only
hope that Google can sort it all out.  Seems like any Answer that says the
problem is resolved with release so-and-so should be fine.

Brad Smallridge
aivision









Article: 94594
Subject: Re: FPGA Altair Advice
From: Eric Smith <eric@brouhaha.com>
Date: 13 Jan 2006 16:39:05 -0800
Links: << >>  << T >>  << A >>
"logjam" <grant@cmosxray.com> writes:
> Is the T80 core accurate enough to produce
> the two clock phases and all of the bus signals?

No, no two-phase clock.  You'd have to add something to generate it.
The T80 bus is much closer to the Z80 bus than the 8080 bus.

> What development board would you suggest I buy for this purpose?

I like the Spartan-3 Starter Kit, which you can buy from Digilent with
an XC3S1000 for $149.

The I/O expansion connectors suck, though.

> I've heard about schematic entry for the logic, and I'd like to have that
> tool as an option. 

Personally, I find it much easier to deal with equations in an HDL.
I can understand logic symbols on a schematic just fine, but if someone
asks me to draw a schematic, it takes me more time to convert my mental
concept into a bunch of logic symbols than to just type an equation.
However, other people find the opposite to be true.

Anyhow, the Altair logic uses lots of asynchronous crap like one-shots.
I suppose you could simulate the oneshots by counters with a really high
clock rate, but the design would still be fundametally asynchronous.
Async logic in FPGAs is not a good idea; other people here can tell you
horror stories about it.

Article: 94595
Subject: Re: Attack of the clones
From: Eric Smith <eric@brouhaha.com>
Date: 13 Jan 2006 16:54:47 -0800
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> Xerox PARC tried to buy a DEC 10, but DEC wouldn't sell them one.

No.  Xerox wouldn't let them, since they'd just purchased Scientific
Data Systems (SDS), which they renamed to XDS.  The corporate types
thought (perhaps correctly) that it would negatively impact XDS sales
if customers got wind that XDS machines weren't good enough for Xerox'
own internal use.

Of course, the fact that PARC built their own PDP-10 rather than using
XDS machines would send the same message to customers.

> So, Xerox got the schematics, put everyone to work, and built one.

Xerox may or may not have had the DEC schematics, but they designed their
own PDP-10 clone ("MAXC") from the ground up.  There was no real similarity
to the DEC hardware; MAXC was simply designed to execute the same
instruction set.

> Just one.

Two, actually.  And the second was a redesign, not a copy of the first.

> Used it for research.  Even made their own operating system for
> it.

They wrote their own operating systems for various small computers they
developed, but on MAXC they used TENEX, which came from BBN.  A few
years later DEC used TENEX as the basis for TOPS-20, which ran on the
PDP-10 processor of the DECSYSTEM-20.

> Nothing DEC could do:  Xerox PARC did not derive any profit from it,
> did not use it to do any product (and they had the losses to prove
> it!).

That wasn't the issue.  There weren't any patents on the PDP-10 instruction
set.  If there were, DEC might have had grounds to sue, even though PARC
didn't ship it as a product.

Profit is not the same as economic benefit.  Even if Xerox posted a loss
every year that they were using MAXC, it's quite possible that they would
have had a larger loss without it.  MAXC contributed to the development
of many successful Xerox products.

If company A sells some patented product P, and company B decides that
buying a P would save them lots of money, but builds their own P to
save even more, you can bet that company A will sue if they get wind
of it.

Unless, of course, company B develops P2, which does not use the patent
claims held by A.  In which case they still might get sued, but will
have a better defense.

I've personally been involved in a case where a company build a clone
of something, carefully avoiding the patents, but was threatened with
litigation and negotiated a license rather than spend a bunch of money
to try to defend it.

> I wonder if today Apple would even care if you went into business
> offering (old) Mac Clones?

They're not going to care unless you include a copy of the Mac ROM,
which is the main component of the "secret sauce" of the Macintosh.

> As long as you are not using their IP, their patents (and not
> impacting their present business), they really have no reason to care.

But of what use is a Mac clone without a ROM?  It's arguably of even
less use than a newborn baby.

Article: 94596
Subject: Re: FPGA Journal Article
From: "Piotr Wyderski" <wyderski@mothers.against.spam-ii.uni.wroc.pl>
Date: Sat, 14 Jan 2006 01:55:00 +0100
Links: << >>  << T >>  << A >>
Kevin Morris wrote:

> My theory is that electronics as a hobby went through a "dark age"
> period, maybe from the early/mid 1970s until recently becuase of the
inaccessibility
> and cost of designing with state-of-the-art technology.

I think it is not true. Hobbyists do not need state-of-the-art technology,
they need satisfaction -- this is the key difference compared to
professional
electronics. For one person a simple LED blinker is perfectly enough,
somebody else is happy when his three transistor AM radio is working,
there also are hobbyists doing DSP using FPGAs just for fun.

The next problem is related with the lack of appropriate technologies.
SMD parts were useless, because we didn't know how to produce
good enough single layer PCBs at home, not to mention double layer
boards. Now we have two competitive technologies (optical, based on
photoactive resins and the second one, called "thermotransfer", which
directly transfers the pattern from a sheet of paper printed by a laser
printer onto the copper surface using a flatiron and two rags). We've
even learned how to make precise two-sided PCBs using that technologies.
Now the SMD components in TQFP/SO/TSSOP are no longer a
problem. But we still don't know how to solder BGAs and QFNs...

>  Radio Shack shifted their focus from 50-in-1 project kits

I think that kits are a big misunderstanding, because you just need to
connect provided parts as described on a provided diagram. Even
a chimp could do it. The trick is to design the device yourself, from
scratch. It needn't be perfect, it sometimes produces smoke, but it's
_yours_.

> (as often evidenced in this group).

Hmm, really? ;-) As far as I know the only "pure" hobbyists
here are Antti and myself, the rest is more or less professional.

> I know, Austin will probably post a strong technical argument that
> Xilinx FPGAs are uniquely attractive to the hobbyist

Hard to obtain in small quantities...

> and Actel and Lattice people will post just to remind us
> that they have low-cost kits too

But they do not  provide free simulators, so they are virtually useless for
hobbyists.

> but I'm primarily interested in some info from real, live, "working"
hobbyists.

Well, I hope it's useful... . :-)

    Best regards
    Piotr Wyderski

--
"If you were plowing a field, which would you rather use?
Two strong oxen or 1024 chickens?" -- Seymour Cray


Article: 94597
Subject: Re: how do I minimize the logic in this function?
From: Eric Smith <eric@brouhaha.com>
Date: 13 Jan 2006 16:56:55 -0800
Links: << >>  << T >>  << A >>
"Brannon" <brannonking@yahoo.com> writes:
> I have an async function with six bits in and eight bits out (listed
> below).  It appears that most kmap tools will support six bits in but
> only one bit out.

So split it into eight functions that each take six bits in and produce
one bit out.  Then minimize each one separately.

Better yet, just write it in an HDL and let the synthesis tools take
care of it.  For all but the most timing-critical cases, you'll wind
up with perfectly acceptable results.

Article: 94598
Subject: Re: how do I minimize the logic in this function?
From: "John_H" <johnhandwork@mail.com>
Date: Sat, 14 Jan 2006 01:16:06 GMT
Links: << >>  << T >>  << A >>
"Brannon" <brannonking@yahoo.com> wrote in message 
news:1137194278.231562.68890@f14g2000cwb.googlegroups.com...
> Okay: lets suppose I use eight ROM64x1 prims. Is that really fewer
> recourses and/or comparable in speed to a four bit subtracter plugged
> into the switch 6b x 16el mux with constants on all its data? What
> resources does a ROM64x1 use?

The ROM64x1 uses 4 16-bit LUTs, two MUXF5s and a MUXF6.  You would have 6 
bits of address with fanouts of 6-24 with 1 LUT through MUXF5 and MUXF6 as 
your delay times.  The total resources: 16 slices. 



Article: 94599
Subject: Re: Don't even get me started on lead,
From: "John_H" <johnhandwork@mail.com>
Date: Sat, 14 Jan 2006 01:28:54 GMT
Links: << >>  << T >>  << A >>
"Roel" <electronics_designer@hotmail.com> wrote in message 
news:dq9g76$ndq$1@news4.zwoll1.ov.home.nl...
<snip>
> It's amazing that there are still people saying that such substances may 
> just be dumped permanently in the environment that should be the 
> environment for the next million years of civilization.
<snip>

It's amazing anyone thinks civilization would last a million years. 





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