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Hello, The PCI Express Base Specification v1.1 doesn't specify a reference clock; the reason is that PCI Express is designed to operate without a common reference clock between components. What the PCI Express Base Specification v1.1 does specify is the allowed ppm difference (+/- 300 ppm) on the unit interval (400 ps). Technically, you can use whatever reference clock you want, at whatever frequency you may desire, as long as your device's transmitter observes the UI specification and your device's receiver is able to lock onto a signal (from another device) that also observes the UI specification. In the most general case, this a pleisochronous interface. While we are on the topic of common signals distributed to components, the PCI Express Base Specification v1.1 does not specify a common, distributed reset signal. It also does not specify a common, distributed power managment event signal. There are mechanisms to communicate these "events" in-band. Now, all that being said, there is another document, the PCI Express Card Electromechanical Specification v1.1, which defines a standard card and slot form factor. One of the features of this form factor is the availability of a distributed reference clock that is nominally 100 MHz and has specified electrical characteristics. You can use it, or not. If you need some other frequency, like 125 MHz, or you need it in some other electrical signaling standard, you will need to provide for that conversion. There are some significant advantages to using this reference clock. One is that you don't need to provide your own oscillator. Another advantage of using a common reference clock is that it turns what was a pleisochronous interface into something that is mesochronous which will, based on the specifications, tolerate the use of spread spectrum clocking on the reference clock. I am also told that this arrangement enables CDR circuits in receivers to lock much more quickly, facilitating low latency exits from PCI Express power saving states. I think that's because the lock to data step doesn't have far to go from the lock to reference, but I don't design PLLs so don't quote me on that. The PCI Express Card Electromechanical Specification v1.1 also defines a reset signal, PERST#, and a power management event signal, WAKE#. These provide an alternate side-band (versus in-band) mechanism for signaling these events. Their operation and use is described in this separate document because they are NOT part of the base specification. Eric Crabill Xilinx, IncorporatedArticle: 94551
"Anonymous" <someone@microsoft.com> schrieb im Newsbeitrag news:wuOxf.10419$Kp.2204@southeast.rr.com... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:dq7m71$s50$03$1@news.t-online.com... >> "Anonymous" <someone@microsoft.com> schrieb im Newsbeitrag >> news:rRFxf.9618$Kp.656@southeast.rr.com... >> > This is a commercial project. I was under the impression Xilinx >> > provides > a >> > working Linux build for the V4? I don't expect to be doing much Linux >> > hacking per se, maybe just a custom device driver to interface to my >> > DSP >> > circuit/code. >> > >> > "John Williams" <jwilliams@itee.uq.edu.au> wrote in message >> > news:newscache$6670ti$oeg$1@lbox.itee.uq.edu.au... >> >> Anonymous wrote: >> >> > Thanks. But that brings up another question: Is it better to go with >> > ucLinux >> >> > or use the PPC version of linux? I suspect the latter if I have the > FX >> > part, >> >> > right? >> >> >> >> Being the maintainer of the MicroBlaze uClinux port, and offering >> >> commercial services for the platform, I'm obviously biased :), however > I >> >> think the decision is not as automatic as you suggest. >> >> >> >> Unless you are prepared to shell out a reasonable number of dollars to >> >> MontaVista, developing for uClinux with the free tools is a lot easier >> >> than PPC. There are some guides out there on DIY Linux for Xilinx >> >> PPC, >> >> but they aren't for the faint-hearted. >> >> >> >> The board port/bringup procedure for uClinux on MicroBlaze is also a > lot >> >> faster than PPC Linux, with the free auto-config tools. >> >> >> >> It depends on what you are trying to do, and how much you value your >> >> time. >> >> >> >> Is this a hobbyist, study or commercial project? >> >> >> >> Regards, >> >> >> >> John >> >> >> >> I stand here with John - the Xilinx PPC linux setup is not for >> faint-hearted. >> >> That is because of Xilinx politics - everybody who is not MontaVista >> gets just ignored - DENX was doing lots of work towards PPC linux >> support but as Xilinx did not talk to them so Denx dropped any further >> work on Xilinx support for PPC linux. Thats too bad. >> >> Setting up a new MicroBlaze uCLinux systems is just a piece of cake >> So if you need some DSP code setup uClinux/Microblaze, connect >> your DSP functions to FSL links and you are all set >> >> -- >> Antti Lukats >> http://www.xilant.com >> >> > > That's interesting. So if I have an FX12 part, for example, your > suggestion > is that I run uclinux in a soft core and implement my DSP code in the PPC > core? This is the opposite of what I had expected. > > What do I give up for ucLinux versus PPC Linux? Speed? Device driver > support? > > Also, what's your suggestion for unit control? I imagined a webserver > interfaced to some type of CGI. Maybe perl scripts or php? > > Thanks, > Clark > > Hi Clark, you dont have to give up PPC, but it is WAY easier to use uClinux/Microblaze, as of using PPC for DSP, well I did not suggest that, you did - and that is defenetly a good idea, so could end up MicroBlaze/uClinux for network and management PPC "ultracontroller" and dedicated DSP for DSP functions and yes, you can use the Xilinx Webserver demo as control application for first demo testing later is up to you if you run uClinux also or not http://www.eubus.net the HCU units there use Spartan3 in DIP40 as the network engine MicroBlaze/uClinux control of those is over telnet and custom protocols -- Antti Lukats http://www.xilant.comArticle: 94552
I have solve this problem,the most important is a system file named windrvr.sys.When this file version is 6.03,the impact doesn't work correctly in win2000 sp4,but the version is 5.05,all is ok.Article: 94553
On 12 Jan 2006 12:15:13 -0800, "Kevin Morris" <kevin@techfocusmedia.com> wrote: >I'm writing a feature article for FPGA Journal (www.fpgajournal.com) >about FPGAs and the re-birth of the electronics hobbyist. My theory is >that electronics as a hobby went through a "dark age" period, maybe >from the early/mid 1970s until recently becuase of the inaccessibility >and cost of designing with state-of-the-art technology. Radio Shack >shifted their focus from 50-in-1 project kits and hobbyist parts to >selling toys, cell-phones, and stereo equipment. > >Now, with the emergence of low-cost, high-capability FPGAs, development >boards, and design software, I see a new age of hobbyist activity >beginning (as often evidenced in this group). > >I'm looking for a few people that would be willing to express views on >this topic for the article. > >I know, Austin will probably post a strong technical argument that >Xilinx FPGAs are uniquely attractive to the hobbyist, somebody from >Altera will send me a Cubic Cyclonium prototyping paperweight (they're >very cool), and Actel and Lattice people will post just to remind us >that they have low-cost kits too, but I'm primarily interested in some >info from real, live, "working" hobbyists. > >Any takers? I *used* to be an electronics hobbyist, but now I do it full-time. The trend here is increasingly towards digital and software, increasingly away from actual electricity. The tools of choice become PCs and green eyeshades, same as the gear needed to be an accountant. This is partly because it's less messy, and because universities can replace expensive lab benches and test equipment with cheap laptop PCs that the students have to buy themselves. Hell, you can get an "EE" degree now without studying electromagnetics! I walked through the EE department at Cornell and counted screens. PC screens outnumbered oscilloscope screens by about 6:1. That's fine by me: I design instrumentation that's analog intense, and the uPs and FPGAs play supporting roles. But a lot of kids are missing the luxury boat if the only numbers they know how to count are 0 and 1. JohnArticle: 94554
All, I've got some directed routing constraints in my UCF file. After some recent changes I get the following message in the P&R PAR file:- # of EXACT MODE DIRECTED ROUTING found:14, SUCCESS:9, FAILED:5 Anyone know how to find out which nets are failing? I can't find anything in the report files. TIA, Syms.Article: 94555
Hello Kevin, You are welcome to contact me directly. You know what they say about opinions... I have one, too. You can check out my hobby-ish activites at: http://www.fpga-games.com (self-funded hobby) http:///www.engr.sjsu.edu/crabill (some funds from Ahhhnold and the State of California) I'm standing on the shoulders of great people like Mr. Mike J from FPGA Arcade over at: http://www.fpgaarcade.com Also, I think another very interesting product for recreational learning is the XGS, see: http://www.xgamestation.com Of course, you could implement the whole XGS in a small FPGA, but for someone with a CS background (or none at all) a product like the XGS might be a very enticing first step into the world of electronics. Eric Crabill Speaking for MyselfArticle: 94556
It's not supported. I didn't pay enough attention to the specs because I see it now on the web page. Is 8.i now available for the ML402/SX35?Article: 94557
I use to be able to write over text by pressing the Insert key. What has changed? Is there another way to write over?Article: 94558
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:cikfs115adje37jmlu0dtflp824oivqf7q@4ax.com... > > I walked through the EE department at Cornell and counted screens. PC > screens outnumbered oscilloscope screens by about 6:1. > > That's fine by me: I design instrumentation that's analog intense, and > the uPs and FPGAs play supporting roles. But a lot of kids are missing > the luxury boat if the only numbers they know how to count are 0 and > 1. > Hi John, I design the same stuff. However, I find I'm using my PC more and more. Simulating it and getting the design right first spin is much nicer than fixing it later, at least that's what the CEO says. I have software on my PC that (I hear) uses lots of 0's and 1's together to model real numbers. Lovely! ;-) Cheers, Syms. p.s. But you're right. I don't own a boat.Article: 94559
All, The presence of the U238 to Pb206 chain in lead is well known. Just go back a few years to our alpha particle contamination issue! http://direct.xilinx.com/bvdocs/whitepapers/wp208.pdf The solder bumps were roughly 50 counts per hour (alpha emission). That led to one soft error in 80 days on a 2V6000 (roughly 1200 solder bumps). Believe me, replacing every part that had the contamination was not something Xilinx would ever like to do ever again! It had just one bright side: it made everyone aware of the issue, and also made them aware of cosmic ray induced SEUs. So all the work we had done to improve our hardness to upsets began to be noticed... http://tinyurl.com/c575m Now an alpha is stopped by a piece of paper, so only flip chip parts, with 'solder' bumps, were affected (in our product line). The solution is purified lead, which is known as ultra-low alpha emitting, which comes in at less than 0.01 counts per hour. Even lead which is completely pure will be "activated" by errant cosmic rays, and will eventually start emitting alphas again as some lead transmutes to polonoium, thorium, etc. http://products.teckcominco.com/Products/AdvancedMaterialProducts.html So, is lead stable? Maybe 1500 meters below ground, or at the bottom of the ocean (like IBM buying old ship's ballast lead for their packages after they first encountered the issue). But once you have it at sea level (or higher), alphas begin to happen again. http://www.research.ibm.com/journal/rd/494/gruber.html As well there are isotopes which have billion year, and hundreds of thousands of year half life which can not be separated adequately, so when these finally break down, you are left with the series that now emits alphas every few days/weeks/months again... http://www.lbl.gov/abc/wallchart/chapters/03/1.html http://eesc.columbia.edu/courses/ees/lithosphere/labs/lab12/NuclearTable1.html 'Lead free' just means you didn't intentionally put any lead into the mix, but with leaded fuels still used in parts of the world, turns out that even organic materials have lead in them! And they emit alphas. That makes packaging SRAM chips a real pain (just go ask Cypress) as just about anything you use as a binder in eopoxy for packaging emits some low level of alphas! http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=ZTPV3Z0NYUA1QQSNDBOCKHSCJUMEKJVN?articleID=19400052&_requestid=150196 http://tinyurl.com/944q8 And, Chernobyl didn't help. Nor does bessemer steel processing (which concentrates atmospheric radioactive materials, and binds them into steel). Nor the processing of scrap that accidentially contaminates tons of material with medical radiological chemical wastes. If you haven't been bit by alphas (yet), then you should go make sure you will not be! If you are buying ASIC's, well you better go make sure your supplier knows what they are doing! An alpha problem there will drive you nuts. IBM has been bit, HP has, ... and Xilinx has (we are the some of the few who at least admitted it, faced it head on, and 'solved it' for our customers!) RoHS does nothing whatsoever for the alpha problem. You will need to buy low alpha, or ultra low alpha RoHS compliant solder pastes, balls, etc. if that is part of your business! And you will need to test for it, monitor manufacturing processes, use independent work stations and tools to prevent cross contamination .... So much fun. Austin Symon wrote: > Dimiter, > I'll try again. ;-) > Production of Solder and Flux with Low Radioactivity > http://hep1.snu.ac.kr/misc/nim1997.ps > > Quote:- > "The lead in solder typically contains trace amounts of U238, Th 232 and > K40." > > I agree the RoHS is nonsense. However, Kolja is correct that putting lead in > solder makes it slightly radioactive. Not because of the lead; because of > the contaminants. The contaminants are present as most lead is radiogenic. > > Cheers, Syms. > > p.s. Here's another link! > http://www.puretechnologies.com/category_s/17.htm > >Article: 94560
"Brad Smallridge" <bradsmallridge@dslextreme.com> schrieb im Newsbeitrag news:11sfmstr7fedpbb@corp.supernews.com... >I use to be able to write over text by pressing the Insert key. > What has changed? Is there another way to write over? > they f*2323 all the known hotkeys in ISE 8.1 editor :) I am very used to use <shift>+INS as "Paste" that does not work anymore ! also on german keyboard getting this | by using (right)ALT doesnt work any more (at least sometimes?) so I start notepad, insert | copy paste it to clipboard then switch to ISE an paste it I really doesnt understand what sense does it make to mess up all normal windows hotkeys ? maybe its KDE emulation for WinXP !? for me its only annoying. -- Antti Lukats http://www.xilant.comArticle: 94561
Thank you all for your answers. Stéphane. "sjulhes" <t@aol.fr> a écrit dans le message de news: 43c75f44$0$19976$626a14ce@news.free.fr... > Hello, > > I don't have the specification of PCI e ( that doesn't help ! ) and I'm > trying to figure out how the clock scheme works on PCI express. > > For me when using serial high speed links, the clock was included within the > 8B/10B and hardware low layers stuffs. > I did a design with aurora and MGT on fiber links, and no clock was > transmitted as a signal, it was integrated on the data line. > > For me PCIe is the same thing but on LVDS. > And I saw on a reference design that a LVDS clock was given the PCIe > interface chip and send to the bus connector. > > So when I design a PCIe board, what is the clock scheme to implement ? > Clock generation or not on the bus ?!! > > I'm missing something. Obviously..... > > Thanks for your help ! > > Stéphane. > >Article: 94562
Workaround is to Windows->Float This gives a separate editor window for the file. Hot keys should work in this editor. Thanx Krishnan Antti Lukats wrote: > "Brad Smallridge" <bradsmallridge@dslextreme.com> schrieb im Newsbeitrag > news:11sfmstr7fedpbb@corp.supernews.com... > >I use to be able to write over text by pressing the Insert key. > > What has changed? Is there another way to write over? > > > > they f*2323 all the known hotkeys in ISE 8.1 editor :) > > I am very used to use <shift>+INS as "Paste" that does not work anymore ! > > also on german keyboard getting this > > | > > by using (right)ALT doesnt work any more (at least sometimes?) so I start > notepad, insert > > | > > copy paste it to clipboard then switch to ISE an paste it > > I really doesnt understand what sense does it make to mess up all normal > windows hotkeys ? > maybe its KDE emulation for WinXP !? for me its only annoying. > > -- > Antti Lukats > http://www.xilant.comArticle: 94563
Does anyone have a Virtex-4 BRAM16 simulation running? I have been trying for two days now to get a simulation to work to no avail using coregen, primitives, ISE simulator and ModelSim_XE. Brad Smallridge aivision dot comArticle: 94564
Thanks! it really fixed it. still why was it needed to brake the hotkeys in first place?? <krishnans@hotmail.com> schrieb im Newsbeitrag news:1137175087.176495.109080@g14g2000cwa.googlegroups.com... > Workaround is to > Windows->Float > This gives a separate editor window for the file. > Hot keys should work in this editor. > Thanx > Krishnan > > Antti Lukats wrote: >> "Brad Smallridge" <bradsmallridge@dslextreme.com> schrieb im Newsbeitrag >> news:11sfmstr7fedpbb@corp.supernews.com... >> >I use to be able to write over text by pressing the Insert key. >> > What has changed? Is there another way to write over? >> > >> >> they f*2323 all the known hotkeys in ISE 8.1 editor :) >> >> I am very used to use <shift>+INS as "Paste" that does not work anymore ! >> >> also on german keyboard getting this >> >> | >> >> by using (right)ALT doesnt work any more (at least sometimes?) so I start >> notepad, insert >> >> | >> >> copy paste it to clipboard then switch to ISE an paste it >> >> I really doesnt understand what sense does it make to mess up all normal >> windows hotkeys ? >> maybe its KDE emulation for WinXP !? for me its only annoying. >> >> -- >> Antti Lukats >> http://www.xilant.com >Article: 94565
Brad, Answer Record # 22029: LogiCORE Dual Port Block Memory v6.3 - Mismatch on both DOUTA and DOUTB for the DPBLKMEM for V-4 using NCSIM ... dual, port, block memory, block RAM, BRAM, ramb16, dp ... blkmem, dout, douta, doutb, ncsim, simulation, timing issue ... Memory v6.3, targeting the Virtex-4 family and ... - 24k - Cached Answer Record # 21848: LogiCORE FIFO Generator v2.2 - Release Notes and Known Issues for FIFO Generator Core ... asynchronous, synchronous, common, clocks, memory, BRAM, RAMB16, FIFO16 ... When using Virtex-4 FIFO16 type ... recommended that you use Structural simulation model. ... - 26k - Cached Answer Record # 19959: 6.3i Install - ISE Service Pack 3 Release Notes/README ... 19853) (SP1) 6.3i NetGen, Timing Simulation - Simulator errors ... II PAR - Placer check rejects valid 512x36 BRAM vs ... Answer 19922) (SP1) 6.3i Virtex-4 PAR - Router ... - 51k - Cached Did you check these three tech answers? using http://www.xilinx.com/support/library.htm It isn't the best way to communicate, but it does exist, and we are diligent about reporting and updating stuff... Perhaps someone else can comment as well. Austin Brad Smallridge wrote: > Does anyone have a Virtex-4 BRAM16 simulation running? > > I have been trying for two days now to get a simulation > to work to no avail using coregen, primitives, ISE simulator > and ModelSim_XE. > > Brad Smallridge > aivision dot com > >Article: 94566
Austin, > ... > The solder bumps were roughly 50 counts per hour (alpha emission). > ... Well I was perceiving that as low activity. It is certainly interesting to know it can be too much in this area. But at the tiny geometries today, I should have guessed it was. Thanks for the posting! > > RoHS does nothing whatsoever for the alpha problem. You will need to > buy low alpha, or ultra low alpha RoHS compliant solder pastes, balls, > etc. if that is part of your business! That was my main point, lead or not activity problems would be the same, it appears they are hard rather than non-existant in this busyness (as I naively thought). And the point which wakes the beast in me is the total uselessness of that RoHS nonsense, I wish we could do something about it .... Thanks again, Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 94567
Dimiter, As for "does RoHs make my life any safer applied to electronics?" I would have to agree with you: it does not. There is absolutely no reason to go through this nonsense when automotive lead acid car batteries are thrown away by the roadside and in landfills every day... I would say clean up the major polluters first, and then go after the next tier. To go after electronics, and electronics assemblies when they conrtibute practically no lead to the environment is just silly. I can understand not using lead in paint for homes! Or no lead water pipes! But is this a case of over zealousness? How about requiring a non-polluting lithium or nickel hydride battery to start the cars, first? Maybe we should go back to a hand crank (with a super capacitor/generator)? Talk about removing 99.99% of the lead from our environment! AustinArticle: 94568
Brad, It works fine with instantiated RAMB16 primitives instead of coregen. The Virtex4 primitives are a little easier to use than the old Virtex2 memory primitives because with the V4 ones, it is one primitive for all aspect ratios. Well at least for a parameterized component where the memory depth is dependent on generic parameters. I vaguely recall there being an issue with the coregen memory generator for V4, but I'll be darned if I can find it now. I generally do not use coregen because of a combination of less than stellar experience with it, an accumulated library of equivalent functions, and no visibility into what it is doing or more importantly the lack of hooks to make minor changes to fit a particular application better. Anyway, try using a generate statement to instantiate the RAMB16 primitives and you should be fine. This is a fairly simple macro to write, and one that you will undoubtedly use quite a bit going forward. Austin, See that's the trouble with the current Xilinx handling of issues like this. Yeah, you publish solutions but unless you know exactly what you are looking for and know that there is an issue you are very unlikely to find it. I looked at the three answer records you posted, and I don't believe any of them address his situation. Answer 22029 is a non-answer that is specific to NCSIM. Brad specifically stated he is using Modelsim. Answer 21848 is a release note for the fifo coregen, which I don't think applies to Brad's question (and certainly doesn't address the more serious issues with the FIFO16 primitive). Answer 19959 is installation instructions and release notes for ISE 6.3i, again, not all that relevant as far as I can see. I'm sure there is probably something more relevant in the Answers database, but without the exact magic incantation to get to it, it will likely lie buried for eternity. While the answers data base is a good idea, it is badly crippled by poor organization and a picky search engine that more often than not only finds irrelevant stuff. The answers data base is certainly not the whole answer either, and is an area that Xilinx very much needs to improve. Austin Lesea wrote: > Brad, > > Answer Record # 22029: LogiCORE Dual Port Block Memory v6.3 - Mismatch > on both DOUTA and DOUTB for the DPBLKMEM for V-4 using NCSIM > ... dual, port, block memory, block RAM, BRAM, ramb16, dp ... blkmem, > dout, douta, doutb, > ncsim, simulation, timing issue ... Memory v6.3, targeting the Virtex-4 > family and ... > - 24k - Cached > > Answer Record # 21848: LogiCORE FIFO Generator v2.2 - Release Notes and > Known Issues for FIFO Generator Core > ... asynchronous, synchronous, common, clocks, memory, BRAM, RAMB16, > FIFO16 ... When using > Virtex-4 FIFO16 type ... recommended that you use Structural simulation > model. ... > - 26k - Cached > > Answer Record # 19959: 6.3i Install - ISE Service Pack 3 Release > Notes/README > ... 19853) (SP1) 6.3i NetGen, Timing Simulation - Simulator errors ... > II PAR - Placer check > rejects valid 512x36 BRAM vs ... Answer 19922) (SP1) 6.3i Virtex-4 PAR - > Router ... > - 51k - Cached > > Did you check these three tech answers? using > http://www.xilinx.com/support/library.htm > > It isn't the best way to communicate, but it does exist, and we are > diligent about reporting and updating stuff... > > Perhaps someone else can comment as well. > > AustinArticle: 94569
Austin Lesea wrote: > Dimiter, > > As for "does RoHs make my life any safer applied to electronics?" I > would have to agree with you: it does not. > > There is absolutely no reason to go through this nonsense when > automotive lead acid car batteries are thrown away by the roadside and > in landfills every day... > > I would say clean up the major polluters first, and then go after the > next tier. To go after electronics, and electronics assemblies when > they conrtibute practically no lead to the environment is just silly. > > I can understand not using lead in paint for homes! Or no lead water pipes! > > But is this a case of over zealousness? > > How about requiring a non-polluting lithium or nickel hydride battery to > start the cars, first? Maybe we should go back to a hand crank (with a > super capacitor/generator)? > > Talk about removing 99.99% of the lead from our environment! > > Austin My dad told me that back in the days when a hand crank was used to start a car, that the crank could break the driver's arm or wrist if the engine back-fired. So perhaps the solution is to use a car sized version of the generator in that flashlight that's advertised on TV that you shake before turn on the flashlight ;) -Dave PollumArticle: 94570
On Fri, 13 Jan 2006 16:56:20 -0000, "Symon" <symon_brewer@hotmail.com> wrote: >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:cikfs115adje37jmlu0dtflp824oivqf7q@4ax.com... >> >> I walked through the EE department at Cornell and counted screens. PC >> screens outnumbered oscilloscope screens by about 6:1. >> >> That's fine by me: I design instrumentation that's analog intense, and >> the uPs and FPGAs play supporting roles. But a lot of kids are missing >> the luxury boat if the only numbers they know how to count are 0 and >> 1. >> >Hi John, >I design the same stuff. However, I find I'm using my PC more and more. >Simulating it and getting the design right first spin is much nicer than >fixing it later, at least that's what the CEO says. I have software on my PC >that (I hear) uses lots of 0's and 1's together to model real numbers. >Lovely! ;-) >Cheers, Syms. >p.s. But you're right. I don't own a boat. > So, I wonder, how many people here are exclusively logic designers, and how many are more general EEs, who deal with the analog, power, thermal, and other aspects of electronic design? JohnArticle: 94571
I was working on a Macintosh clone project (a clone of the original 128k), but I'm not willing to invest any more time in something that Apple would probably kill with a C&D order. I'm now working on a hardware replica of the Altair. I'm scanning the PCB layout and creating historically accurate replicas. I've come to the conclusion that the average person is not going to be able to afford a kit "just for the fun of it". There are literally square feet of PCBs required and a lot of the components will be expensive. This leads me to the idea of putting the Altair into an FPGA for people who want the blinking light effect but could care less about the guts. This would be similar to the PDP-8 clone that is an inch thick and can be hung on a wall like an interactive picture. I don't have any experience designing logic for FPGAs, but like learning C/Assembler/Visual basic...I can probably use code examples to teach myself. Basically what I'm looking for is an FPGA development board that would be suited to hold the 8080. I would also like to integrate an "optional" boot ROM, RAM, serial card, cassette card, etc. These devices wouldn't take up too many resources I'd think. The only possible problem I can think of for an Altair FPGA is that I would want all the bus signals brought out for the front panel and for optional interface cards. Is the T80 core accurate enough to produce the two clock phases and all of the bus signals? What development board would you suggest I buy for this purpose? I've heard about schematic entry for the logic, and I'd like to have that tool as an option. Thanks for your time, GrantArticle: 94572
"Dave Pollum" <vze24h5m@verizon.net> wrote in news:1137182388.324177.116380@g47g2000cwa.googlegroups.com: > > Austin Lesea wrote: >> Dimiter, >> >> As for "does RoHs make my life any safer applied to electronics?" I >> would have to agree with you: it does not. >> >> There is absolutely no reason to go through this nonsense when >> automotive lead acid car batteries are thrown away by the roadside >> and in landfills every day... >> >> I would say clean up the major polluters first, and then go after the >> next tier. To go after electronics, and electronics assemblies when >> they conrtibute practically no lead to the environment is just silly. >> >> I can understand not using lead in paint for homes! Or no lead water >> pipes! >> >> But is this a case of over zealousness? >> >> How about requiring a non-polluting lithium or nickel hydride battery >> to start the cars, first? Maybe we should go back to a hand crank >> (with a super capacitor/generator)? >> >> Talk about removing 99.99% of the lead from our environment! >> Just imagine if the billions of dollars being spent on converting electronics to lead free could have been spent on something that would actually have an impact on improving the environment. Just a simple, back of the envelope calculation would have shown that this whole initiative is crazy. >> Austin > > My dad told me that back in the days when a hand crank was used to > start a car, that the crank could break the driver's arm or wrist if > the engine back-fired. > So perhaps the solution is to use a car sized version of the generator > in that flashlight that's advertised on TV that you shake before turn > on the flashlight ;) > -Dave Pollum > > -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 94573
I have an async function with six bits in and eight bits out (listed below). I need to minimize the logic usage (in a Virtex2) for this function. It appears that most kmap tools will support six bits in but only one bit out. Anyone have a tool or method they would recommend to help with my problem? I do it currently with two three bit subtracters (in LUTs, not CarryChain) and a 6bit x 16 element mux (using muxf prims) running as a lookup table. The output of one adder drives the mux S input. It just takes too much time and space. In Out 0 0 1 66 2 128 3 0 4 64 5 65 6 66 7 64 8 130 9 128 10 136 11 130 12 0 13 66 14 128 15 0 16 68 17 69 18 65 19 68 20 80 21 81 22 69 23 80 24 64 25 65 26 66 27 64 28 68 29 69 30 65 31 68 32 138 33 136 34 160 35 138 36 130 37 128 38 136 39 130 40 162 41 160 42 168 43 162 44 138 45 136 46 160 47 138 48 0 49 66 50 128 51 0 52 64 53 65 54 66 55 64 56 130 57 128 58 136 59 130 60 0 61 66 62 128 63 0 Thanks for your time.Article: 94574
Ray,
I know, I know!
We are really open to any good ideas.
The whole 'technical answers' thing was great when it first arrived:
virtually instant, and (often) useful information.
The newsgroup was great at its start as well.
In today's world, either we can't search what we have (too much stuff),
or the whole idea of tech answers/newsgroups is outdated, or with ~
250,000 users of our software there is no way to cull through the mass
of information we are collecting every minute of every day...
One idea (let me emphasize "idea") is that we collect all answers more
than X days (weeks, months?) old, add them to the specification (change
the datasheet) and then delete them from the answers database.
(Basically, where should old answers go? How to they 'go away'? Do
they just collect forever, until no one cares about that part anymore?).
There are folks out there who shudder at the thought of the
specification sheet changing every X days (weeks, months).
There are folks out there who would welcome finding what they need to
know in one place.
How do you make component engineers happy, and also make design
engineers happy? The world needs them both, and one or the other is
ignored at your peril. I would even try to make the test engineer happy!
Another idea is a "FAQ sheet" for each family/part that lists the
basics...updated whenever something new becomes known?
How about a "wiki" page ('Xiki-Wiki'tm 2006) for each component or
family? A blog?
Additions/deletions to the information is: Unguarded? Managed?
Austin
Ray Andraka wrote:
> Brad,
>
> It works fine with instantiated RAMB16 primitives instead of coregen.
> The Virtex4 primitives are a little easier to use than the old Virtex2
> memory primitives because with the V4 ones, it is one primitive for all
> aspect ratios. Well at least for a parameterized component where the
> memory depth is dependent on generic parameters. I vaguely recall there
> being an issue with the coregen memory generator for V4, but I'll be
> darned if I can find it now. I generally do not use coregen because of
> a combination of less than stellar experience with it, an accumulated
> library of equivalent functions, and no visibility into what it is doing
> or more importantly the lack of hooks to make minor changes to fit a
> particular application better.
>
> Anyway, try using a generate statement to instantiate the RAMB16
> primitives and you should be fine. This is a fairly simple macro to
> write, and one that you will undoubtedly use quite a bit going forward.
>
>
> Austin,
> See that's the trouble with the current Xilinx handling of issues like
> this. Yeah, you publish solutions but unless you know exactly what you
> are looking for and know that there is an issue you are very unlikely to
> find it. I looked at the three answer records you posted, and I don't
> believe any of them address his situation. Answer 22029 is a non-answer
> that is specific to NCSIM. Brad specifically stated he is using
> Modelsim. Answer 21848 is a release note for the fifo coregen, which I
> don't think applies to Brad's question (and certainly doesn't address
> the more serious issues with the FIFO16 primitive). Answer 19959 is
> installation instructions and release notes for ISE 6.3i, again, not all
> that relevant as far as I can see. I'm sure there is probably something
> more relevant in the Answers database, but without the exact magic
> incantation to get to it, it will likely lie buried for eternity. While
> the answers data base is a good idea, it is badly crippled by poor
> organization and a picky search engine that more often than not only
> finds irrelevant stuff. The answers data base is certainly not the
> whole answer either, and is an area that Xilinx very much needs to improve.
>
> Austin Lesea wrote:
>
>> Brad,
>>
>> Answer Record # 22029: LogiCORE Dual Port Block Memory v6.3 - Mismatch
>> on both DOUTA and DOUTB for the DPBLKMEM for V-4 using NCSIM
>> ... dual, port, block memory, block RAM, BRAM, ramb16, dp ... blkmem,
>> dout, douta, doutb,
>> ncsim, simulation, timing issue ... Memory v6.3, targeting the
>> Virtex-4 family and ...
>> - 24k - Cached
>>
>> Answer Record # 21848: LogiCORE FIFO Generator v2.2 - Release Notes
>> and Known Issues for FIFO Generator Core
>> ... asynchronous, synchronous, common, clocks, memory, BRAM, RAMB16,
>> FIFO16 ... When using
>> Virtex-4 FIFO16 type ... recommended that you use Structural
>> simulation model. ...
>> - 26k - Cached
>>
>> Answer Record # 19959: 6.3i Install - ISE Service Pack 3 Release
>> Notes/README
>> ... 19853) (SP1) 6.3i NetGen, Timing Simulation - Simulator errors ...
>> II PAR - Placer check
>> rejects valid 512x36 BRAM vs ... Answer 19922) (SP1) 6.3i Virtex-4 PAR
>> - Router ...
>> - 51k - Cached
>>
>> Did you check these three tech answers? using
>> http://www.xilinx.com/support/library.htm
>>
>> It isn't the best way to communicate, but it does exist, and we are
>> diligent about reporting and updating stuff...
>>
>> Perhaps someone else can comment as well.
>>
>> Austin
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