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rsriragh wrote: > Using the internal 50 MHz clock of the Spartan 3 board, my design > synthesized to a speed of 200MHz . If I want my design to synthesize > using a new clock( say 4 times the clock freq provided by the > board(200MHz)), what should I do? first of all you should place and route the design and then measure the speed, after synthesis you are not taking the routing delay into account > I instantiated the BUFG_DFS_SUBM in my design, which does produce a > 200MHz clkfx signal, after a time lag of 950ns. Could you tell me what > the LOCK signal is? What is it role and how to use it? Now in my > design, in place of using the "clk" of the board, if I use the "clkfx" > that I just generated, will my design now synthesize to a higher speed? NO it will not.(assuming you are not canging the vhdl code) > or is there something else I need to do? try to put some timing constraints to the CLK (int a *.ucf file) and see what you get > Also what is the Xilinx Clocking Wizard? When is it used..what purpose? to help the customers to configure the DCM (and not only) in a more friendly way > What does the. xaw file do? > AurashArticle: 94151
Can you speak English? ;-) http://en.wikipedia.org/wiki/Calculus http://en.wikipedia.org/wiki/Digital_signal_processing Both articles give you a basic start. The links at the bottom of these pages send you to a load of free online stuff to help you learn more. Links like this one:- http://www.spectrum-analyzer.info/ Hopefully you can use this online stuff along with your Spartan kit to learn pretty efficiently. When you get stuck, I'm sure folks on CAF and comp.dsp will be more than glad to offer you further pointers. People seem to be more helpful if you've put in some work yourself; they tend to be wary of 'homework' posts! HTH and good luck, Syms. p.s. Just to make sure, you know about http://en.wikibooks.org/wiki/Main_Page , right? "drg" <drgenio@gmail.com> wrote in message news:1136499024.670241.215990@g43g2000cwa.googlegroups.com... > but it's very difficult to get off the ground in a dark, remote place > where you don't know anyone and don't speak their language :P >Article: 94152
yes I am trying to look at if I can implement an ethernet multiplexer in FPGA if you have any info please forward it to me. thanks & regards KedarArticle: 94153
kedarpapte@gmail.com wrote:
> Hi All,
>
> I want some guidence for encoding schemes used in ethernet
>
> I know that for gigabit ethernet mostly the 8b10b encoding scheme is
> used
> and also I have heard about 64b/66b scheme.
>
> which one is actually used....?
8b/10b is used for Gigabit Ethernet, 64b/66b for 10-Gigabit-Ethernet.
Both encoding schemes are not only used for Ethernet, but for all sorts
of high-speed serial interfaces, like Fibre Channel and the like.
Obviously, the overhead is much less for 64b/66b (3% compared to 20%),
but it's more "complicated" to implement, so you have to find the
trade-off there. 8b/10b is usually done with a simple look-up-table,
some sort of memory that holds all the possible encoded values. For
64b/66b this table would be too big, so there's ways to do the encoding
in logic, like in this appnote:
http://direct.xilinx.com/bvdocs/appnotes/xapp687.pdf
> If I need to send my data on ethernet which one I should use and while
> receiving any data, is there any method for detecting that the
> receiving data is coded in which scheme...?
Usually, the encoding is done in a PHY, not in the FPGA-logic. Normally
you would implement the Ethernet MAC inside the FPGA and then use one of
the MII-interfaces or maybe XAUI to connect it to an external PHY, who
does the encoding and the actual transmission over copper or fiber cables.
Now it depends on what kind of FPGA you're using. Virtex II Pro and
Virtex 4 FX (except the smallest parts) have RocketIOs embedded that
have units für 8b/10b ("normal" RocketIO) or 64b/66b (RocketIO-X) en-
and decoding, so you don't need to do anything there anyway. Virtex 4 FX
also have ready-to-use Ethernet MACs built in, so you don't even have to
implement that.
You need the PHY anyway, be it inside the FPGA or as an external
component, so normally I'd say there's no need to worry about the
encoding schemes because you have some other component that handles it.
cu,
Sean
Article: 94154"Andrew Greensted" <ajg112@ohm.york.ac.uk> wrote in message news:dplcar$ev5$1@pump1.york.ac.uk... > Hans wrote: >> It has been a few years since I looked at the FLI but wouldn't it be >> easier to just allocate an integer array using mti_malloc, read and write >> from the array as normal followed by converting the integers to/from >> signals? >> > > :-) That is exactly what I had been doing... Are you sure?, you are creating an array using mti_CreateArrayType command whereas I suggest to use a simple C array. Have a look at my Fractal FLI demo (not sure it will work with Modelsim 6.x though :-) Another suggestion is to take the memory array out of your FLI code, Regards, Hans www.ht-lab.com > > The problem is, I wanted to create the memory block as an actual signal so > that I could access its contents with modelsim as if it was a standard > VHDL module. > > At some point I'll be replacing the FLI block with actual VHDL, so I > wanted the two to look (from modelsim's perspective) the same. > > Doing it this way would also means I can more easily display memory > content on the modelsim wave and list windows. > > Thanks for the suggestion though. > > Andy > > -- > Dr. Andrew Greensted Department of Electronics > Bio-Inspired Engineering University of York, YO10 5DD, UK > > Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk > Fax: +44(0)1904 433224 Web: www.bioinspired.com/users/ajg112Article: 94155
Antti Lukats wrote: > > you could try there > http://www.xilinx.com/s3ediscount > but I am afraid it may as well not lead to the actual online entry form :( > I received the sample pack in the mail yesterday (from Avnet/US); the $25 discount offer on the case says it's valid until the end of January, but if you click the link it says: "The introductory pricing period for the Spartan-3E Kit is now over" Over before it started, eh... The other funny thing was, when I took the board out of the case there was a strategically placed piece of electrical tape on the board whose only purpose seemed to be to obscure the "Linear Technology" logo on the silkscreen. The card has pads for four of the new Digilent 6 pin I/O headers, plus one of those %#@$&!! forty pin, one ground I/O headers. have fun, BrianArticle: 94156
Is There any recommended book which includes RISC cpu examples for me to start with? I think follow with samples is more efficient.Article: 94157
Hans wrote: > Are you sure?, you are creating an array using mti_CreateArrayType command > whereas I suggest to use a simple C array. Hans, sorry, I should have been more clear. I'd originally modelled the memory using a standard C array, reading and writing values to that. But, then I wanted to be able to access the memory from modelsim, so went over to creating a signal that stored the values. This signal being accessible and displayable on the modelsim wave and list windows. Andy -- Dr. Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, YO10 5DD, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.com/users/ajg112Article: 94158
Thanks all. In the spirit of pets and FPGA's, I think I'll start naming my designs after my pet snakes. Boa and Anaconda are too easy, let marketing try to sell the latest "Albino Corn Snake Processor".Article: 94159
CoreGen (as I know) will be available in ISE WebPack 8.1i. A+ MehdiArticle: 94160
Hello, I have interfaced a 8 bit parallel data bus and a clock signal of the USB device to a CPLD. I need to store 32bits of data in a buffer. And then serially shift out the 32 bits. The loading of the data into the buffer can only be done by using the clock coming from the USB device because when USB generates data it generates clock with it. So I decided to use another clock to serial out the data. The problem is the handshaking between the USB process and the serial out process. The two processes have different clocks so the serial out process could miss the signal form the USB process that the buffer is ready to be serial out. Please advice a solution, thanks JohnArticle: 94161
Hello: I have absolutely no experience in ASIC design. I do however have experience in FPGA. I have a CPU design that is currently working in a Xilinx FPGA. The design fits in a spartan3 XCS200 (144pin Package). I want to migrate to a fully custom chip in a different package. My design only has 10 pins that are used for signals so I want to get into a very small package such as a SOIC20 or a micro lead frame (QFN) 32 package. Is it possible to take a synthesizable netlist to an ASIC vendor and get a custom chip in a custom package? What kind of Costs should I expect? Right now the FPGA solution is too big and to expensive for the runs I need. The Spartan chips need to get to around $4 (and in a smaller package) to become cost effective (rather than $20). Also, I want to get rid of the configuration FLASH to save $$ (Hence the ASIC) Thanks, EliArticle: 94162
The solution is simple, but far from obvious. You need to download and apply the patch for ISE 7.1 or install the latest service pack (4). There is a bug that inverts all of the outputs of CPLDs (with no service pack and also maybe SP1). Go to www.xilinx.com, select downloads, log in (or create a new account), then select your ISE version and OS. Xilinx has refused to post this information to their download page. I even talked to a factory FAE and he could not get them to post it. The only way you can find out about it is to search their site for key words that match the article. MarcArticle: 94163
"Eli Hughes" <emh203@psu.edu> schrieb im Newsbeitrag news:dpm1ca$1kqc$1@f04n12.cac.psu.edu... > Hello: > > I have absolutely no experience in ASIC design. I do however have > experience in FPGA. I have a CPU design that is currently working in a > Xilinx FPGA. The design fits in a spartan3 XCS200 (144pin Package). > > I want to migrate to a fully custom chip in a different package. My > design only has 10 pins that are used for signals so I want to get into a > very small package such as a SOIC20 or a micro lead frame (QFN) 32 > package. > > > Is it possible to take a synthesizable netlist to an ASIC vendor and get a > custom chip in a custom package? What kind of Costs should I expect? > Right now the FPGA solution is too big and to expensive for the runs I > need. The Spartan chips need to get to around $4 (and in a smaller > package) to become cost effective (rather than $20). Also, I want to get > rid of the configuration FLASH to save $$ (Hence the ASIC) > > Thanks, > Eli Xilinx chips can go as low as $4, but well depends on quantity and the config flash is a pain but check also Actel PA3 in CSP package offering, the package is just a bit larger than QFN32, but I think the PCB estate a little smaller than SOIC20 - well cost can be too high, Lattice doesnt have QFN so far, only BGA what is possible too big for you www.chipx.com has qfn56 as smallest package anttiArticle: 94164
Have you looked at Altera's HardCopy device? It allows you to migrate a FPGA (Startix/Cyclone) design to a HardCopy device. It is suppose to have some of the advantages of ASIC device (price was one of them). DerekArticle: 94165
I think what you need is a design flow/ISE tutor document, it's somewhere on Xilinx web. Some more suggestions: Try using simulator (Model sim or Xilinx Sim in 7.1) Read the fitter report to see the implemented equations Also try the ChipViewer to see internal signals After all of these verification steps are done and the board still won't work as expected, Check your configuration method (JTAG? ), verify if your *.jed file has been loaded correctly? Now, you may think of a hardware issue Cheers,Article: 94166
Concur, definitely Altera. Xilinx schematic entry and conversion to HDL is full of bugs. Rob wrote: > Definitely Altera. > > "Thomas Entner" <aon.912710880@aon.at> wrote in message > news:43bc292b$0$16891$91cee783@newsreader01.highway.telekom.at... > >> I'm looking at doing some basic CPLD designs via Schematic Entry. Who > >> has easier to learn/use schematic entry software, Xilinx or Altera? > > > > Altera > > > > Regards, > > > > Thomas > >Article: 94167
news.guardiani@gmail.com wrote: > The solution is simple, but far from obvious. You need to download and > apply the patch for ISE 7.1 or install the latest service pack (4). > There is a bug that inverts all of the outputs of CPLDs (with no > service pack and also maybe SP1). > > Go to www.xilinx.com, select downloads, log in (or create a new > account), then select your ISE version and OS. > > Xilinx has refused to post this information to their download page. I > even talked to a factory FAE and he could not get them to post it. The > only way you can find out about it is to search their site for key > words that match the article. > > Marc I hadn't thought to ask what service pack he had downloaded. Perhaps SP4 will fix all of his problems. On the other hand, if there are _no_ bypass caps on the board, I assume that could cause problems, too. I wonder who he bought the board from. -Dave PollumArticle: 94168
I'm confused (doesn't take much these days). I'm thinking of using Chipscope. The Xilinx shop says 'License Note: In order to use the ChipScope Pro, you must instantiate any of the ILA, IBA, ATC or ATC2 cores within your Xilinx design. Therefore, you will need to be a licensed user of a Xilinx development system in order to implement your design.' Am I a licensed user if I use Webpack 7.x, or do I need Foundation ? DaveArticle: 94169
As far as I know, you have to buy a separate license for Chipscope.Article: 94170
Dave I think those words refer to having bought a Chipscope license. For build I think you should be ok with Webpack providing it covers the device you are using. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development Board. http://www.enterpoint.co.uk "Dave" <dave.garnett@metapurple.co.uk> wrote in message news:1136573106_4101@spool6-east.superfeed.net... > I'm confused (doesn't take much these days). I'm thinking of using > Chipscope. > > The Xilinx shop says > > 'License Note: In order to use the ChipScope Pro, you must instantiate > any of the ILA, IBA, ATC or ATC2 cores within your Xilinx design. > Therefore, you will need to be a licensed user of a Xilinx development > system in order to implement your design.' > > Am I a licensed user if I use Webpack 7.x, or do I need Foundation ? > > Dave >Article: 94171
The ISE feature doc http://www.xilinx.com/ise/devsys_feature_guide.pdf appears to show that Coregen and FPGA Editor are now in Webpack as from revision 8.1. A lot of our customers will be pleased if this document is correct. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan3 PCI Development Board. http://www.enterpoint.co.uk <acetylcholinerd@gmail.com> wrote in message news:1136498960.043093.161570@g49g2000cwa.googlegroups.com... > First, thank you xilinx for moving the functionality previously > available in Base-X to the free WebPack. I was somewhat confused by the > literature on the website, but a call to support confirmed that the ISE > 8.1 WebPack will support all Base-X devices, including the Virtex-4 > FX12. > > However, no one I talked to could confirm if it was possible to use the > Virtex-4 hard EMAC primitive without coregen (which is unavailable in > WebPack); I have managed to instantiate the "EMAC" in my VHDL design > and get synthesis to run, but since I don't have silicon in front of me > yet I can't "test" my design. > > So, is it possible to just use the EMAC primitive like that, without > coregen at all? I also can't simulate the part, as the SWIFT simulation > models require an advanced ($$$) simulator, but that's a restriction > I'm willing to live with. > > ...Eric >Article: 94172
You will, however, need a licensed copy of ChipScope in order to use the actual ILA application on a PC. I believe that you can request a trial license from Xilinx that's good for at least 30 days.Article: 94173
Hello, I have a Veritex-4 PCI board and I like to program the PowerPC on it. I don't have the EDK from Xilinx. Here are my questions: How can program the PowerPC without buying EDK? As I know the compiler and linker is free (part of GNU) where can I get them for free? How can I download the compiled program to PowerPC? How can I get the output? For example if I write a hello world type of program, can I see the STDIO on screen? Any help is much appreciated. Best regardsArticle: 94174
Hi, I have interfaced the eight bit data bus and the clock signal of the USB device to the CPLD. The USB device stores 8 bit in the CPLD'S buffer at every clcok cycle . I need to store 32 bits in the buffer then serial out those bits. I can not serial out the data on the USB clock because when there is not data there is no clock thats how the USB device works. So, I planned to have another clock which serial out the data. But I am worried about the communication between the the two processes. Because when the buffer is full, it will generate the signal to the serial out process and that Flag signal might be missed. So can somebody advice me with a solution. Thanks Regards John
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