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urielka wrote: > my idea is build a SoC(System on Chip) which will be a Video/Audio > player based on FPGA(Xilinx Spartan 3E 1M gate count). > the video and audio decoders are Vorbis for audio and Theora for video > and will be almost hardware based as posible. ... > from what i understand,doing a full ogg decoder on chip is madness so > what i have to do i build coproccessors that will do most of > clock-expensive and the software will use those coprocessors,right? I'd start here: http://oggonachip.sourceforge.net/ > what you think,it is posible? which soft cpu(s) should i use,which > things the cpu need to preform real fast? is it posible on a IIRC, the report from this project had some analysis on performance issues. http://oggonachip.sourceforge.net/oggonachip-1.0/report.pdf See also the short paper version: http://raweb.informatik.uni-stuttgart.de/research/publications/paper-iscas.pdf I've just found this too, but have not read this one. http://ietfec.oxfordjournals.org/cgi/reprint/E88-A/8/2124.pdf MartinArticle: 96626
I'm researching the difference between SGRAM and GDDR and their counter parts SDRAM and DDR RAM. Browsing the manufacturers' websites, it isn't clear but is GDDR-1 what used to be called SGRAM? Or, because of the introduction of GDDR memory the manufacturers have phased SGRAM out and dropped it from their web sites? One of the differences I have found is that these graphic memory devices offer a way of clearing the memory (erasing the screen) and blitting sections of the screen. What other advantages do they offer compared to their conventional counter parts? If interfacing a SGRAM or GDDR RAM device to a FPGA device are there any special considerations that need to be taken compared to SDRAM or DDR RAM? If you know of any good references that go into the application and use of SGRAM or GDDR, could you pass it on? Thanks, Derek SimmonsArticle: 96627
al99999 wrote: > Hi, > > Has anybody ever designed anything to decode and display GPS NMEA data > coming out in ascii form from a UART? > > Any ideas of where to start or how to go about decoding comma delimted > ascii strings? > > Thanks, > > Al NiosII/e CPU, UART, a very small memory for your code, and you're nearly done - just write some C code that parses the sentences... as I remember the NMEA format should be easy enough where you can look for the starting sequence pretty easily to "sync" the CPU; no need for even a timer peripheral. If you're comfortable with C coding I'd say this is an afternoon project; a more in RTL. Jesse Kempa jkempa -at- altera -dot- comArticle: 96628
Richard, I'm sorry to hear you are having issues with our software. Almost 9000 people have registered for the 8.1i WebPACK and our support volume has been pretty low. Regarding your issues with getting support, the WebPACK always has used the web support model. I checked and we have no record of you calling or submitting a web case within the last year. Please submit a web case regarding your issue and we will look into it. Regards, Steve richard wrote: > I recently "upgraded" three of the systems here to use v8.1 of the > XILINX ISE WebPack software, and its companion MXE simulator version, > only to find that nothing at all works properly any longer. > > The schematic entry program, which was already thoroughly messed up in > v7, doesn't seem to work correctly at all. > > Simulation of old, long-complete, projects is completely impossible, as > is programming of the devices. > > I've also learned that XILINX no longer has phone support for such > matters, and that the "web-based" model they've adopted for support > takes much longer ( a week or so, when it used to take a day or two ) > to raise quasi-human contact and begin to approach a solution. > Further, the last three issues I've raised with their new support > agency have resulted in no solution. > > Has anybody managed to get this thing to work properly? What have you > RECENTLY experienced with support? > > Does this mean we have to abandon XILINX as a device vendor? >Article: 96629
It works OK for me. I just tried it on a large VHDL design and it built OK. A small schematic design was OK, also. LeonArticle: 96630
How do you add signals within your VHDL architechture using Xilinx 7.1 ISE Simulator? Brad Smallridge aivision dot comArticle: 96631
Let me tell you what can be done in Virtex-4 (probably also in Spartan3): A priority "linear encoder" with 4 x N inputs and 4 x N outputs, each output corresponding to a prioritized input. Only one output is ever active, the one corresponding to the highest-priority active input. Total cost: 5N+1 (LUTs+flip-flops). Such a 32-input linear priority encoder uses 41 LUTs = 21 slices (<6 CLBs), and runs at >250 MHz. The design is fully modular (per 4 bits). Peter AlfkeArticle: 96632
Jerome wrote: > * cut an existing USB cable, insert a breakoutinteh middle > * connect D+ & D- (and GND) to the FPGA pins (i guess impedance aspects > are OK since FPGA pin input Z is ~ infinite...) Don't connect them directly to the FPGA, unless you're using an older FPGA with 5V-tolerant inputs. If you're not trying to run high-speed USB, you could simply use a 74LVC buffer chip, which does have 5V tolerant inputs. Keep the stub length very short. If you want to deal with high-speed (480 Mbps) USB, you almost certainly will need to use an actual USB transceiver chip. High-speed USB has a very finicky electrical environment.Article: 96633
Steve Lass wrote: > Richard, > > I'm sorry to hear you are having issues with our software. Almost 9000 > people have registered > for the 8.1i WebPACK and our support volume has been pretty low. > > Regarding your issues with getting support, the WebPACK always has used > the web support model. > I checked and we have no record of you calling or submitting a web case > within the last year. > Please submit a web case regarding your issue and we will look into it. Just to let you know, I've encountered a problem with the latest ISE as well : The error described in Answer record 22167 "8.1i XST - INTERNAL_ERROR:Xst:cmain.c:3068:1.158.12.1 - Creating DSP functions" also happens with inferred distrbuted ram, when the address input of the dist ram comes from a register (in my cas it was iob registers, don't know if it matters). I wanted to submit a webcase but when I login into the webcase system all I get is "Internal Server Error" ... Sylvain > > Regards, > > Steve > > richard wrote: > >> I recently "upgraded" three of the systems here to use v8.1 of the >> XILINX ISE WebPack software, and its companion MXE simulator version, >> only to find that nothing at all works properly any longer. >> >> The schematic entry program, which was already thoroughly messed up in >> v7, doesn't seem to work correctly at all. >> >> Simulation of old, long-complete, projects is completely impossible, as >> is programming of the devices. >> >> I've also learned that XILINX no longer has phone support for such >> matters, and that the "web-based" model they've adopted for support >> takes much longer ( a week or so, when it used to take a day or two ) >> to raise quasi-human contact and begin to approach a solution. >> Further, the last three issues I've raised with their new support >> agency have resulted in no solution. >> >> Has anybody managed to get this thing to work properly? What have you >> RECENTLY experienced with support? >> >> Does this mean we have to abandon XILINX as a device vendor? >> >Article: 96634
Matt Clement wrote: > here is the basic "program" > > LIBRARY IEEE; > USE IEEE.STD_LOGIC_1164.ALL; > > ENTITY CLONE34 IS > PORT > (clk : IN BIT; > SEL : IN BIT_VECTOR(7 DOWNTO 0); > ADD : IN BIT_VECTOR(5 DOWNTO 0); > DAT : INOUT BIT_VECTOR(1 DOWNTO 0); > LED1 : OUT BIT_VECTOR(31 DOWNTO 0)); > > END CLONE34; > > ARCHITECTURE ONE OF CLONE34 IS > TYPE STATE_TYPE IS > (IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34); > SIGNAL STATE: STATE_TYPE; > > BEGIN > > PROCESS (clk, ADD) > VARIABLE DATA : BIT_VECTOR(35 DOWNTO 0); > BEGIN > > IF (clk'EVENT AND clk = '1')THEN > > DAT(0)<='0'; > CASE STATE IS > WHEN IDLE => (snip) You might consider adding an asynchronous reset state to your state machine. -aArticle: 96635
Sylvain Munaut wrote: > > I wanted to submit a webcase but when I login into the webcase > system all I get is "Internal Server Error" ... > I've been having similar problems trying to look up an old webcase for a couple of weeks now, and either : a) can't log in or b) can log in, search, and find the webcase title; but when I click on the webcase link: "The page cannot be displayed" BrianArticle: 96636
Depending on your error.. The New XST doesn't respect the older projects. I found that it had rearranged a 6.x project and then generated internal errors instead of not finding libraries. Next is the single file download DOESN'T automatically install web updates. You have to install the first manually by going to the update centre. There is now only one service pack which covers the free and subscription version. These two things cleared up the internal error that I was receiving. Simon "Brian Davis" <brimdavis@aol.com> wrote in message news:1139358049.342945.179110@g44g2000cwa.googlegroups.com... > Sylvain Munaut wrote: > > > > I wanted to submit a webcase but when I login into the webcase > > system all I get is "Internal Server Error" ... > > > I've been having similar problems trying to look up an old webcase > for a couple of weeks now, and either : > > a) can't log in > > or > > b) can log in, search, and find the webcase title; but when I click > on the webcase link: "The page cannot be displayed" > > Brian >Article: 96637
Jump to the reset vector ? "Karel" <karel@gemidis.be> wrote in message news:xdSdnRgSqP8yIXXeRVn-sg@giganews.com... > Hey all, > > I was wondering how to write a software reset in C-code for > the Xilinx Microblaze. > > Regards > > Karel > > >Article: 96638
Simon Peacock wrote: > Jump to the reset vector ? You need to generate an OPB reset signal, otherwise your peripherals are not reset. A single-bit GPIO driven through a pulse widening state machine , with its output tied to the OPB_Rst signal, is one simple way. JohnArticle: 96639
Thanks Eric, However concerning the 5V tolerance, i'm not sure it is necessary since the D+ & D- level swing stays in the 0V - 3.6 V range My first step will consist in measuring these levels with a scope "Eric Smith" <eric@brouhaha.com> wrote in message news:qhzml2bv91.fsf@ruckus.brouhaha.com... > Jerome wrote: >> * cut an existing USB cable, insert a breakoutinteh middle >> * connect D+ & D- (and GND) to the FPGA pins (i guess impedance >> aspects >> are OK since FPGA pin input Z is ~ infinite...) > > Don't connect them directly to the FPGA, unless you're using an older > FPGA with 5V-tolerant inputs. > > If you're not trying to run high-speed USB, you could simply use a > 74LVC buffer chip, which does have 5V tolerant inputs. > > Keep the stub length very short. > > If you want to deal with high-speed (480 Mbps) USB, you almost certainly > will need to use an actual USB transceiver chip. High-speed USB has > a very finicky electrical environment. >Article: 96640
Yes you are so right, I forgot a lot of stuff. Don't worry we are using matlab, and we are going to finish sims. we really should write some specs for it huh. not so complete plan: * use matlab to design filters/model schemes * model functions using vhdl * simulate and debug * create testbenches * build a prototype circuit * synthesize our code onto fpga * analyze results using various scopes working on block diagrams. sigh.... -PeterArticle: 96641
Clark, After you mentioned using GNU Radio, I looked it up and yes we are going to do something similiar. We are building this demo board ourselves as best we could as a senior design project. We dont know enough about USRP to decide to jump into using it yet. -PeterArticle: 96642
If you mean how to add signals to the simulation graphic, just open the whole tree of the UUT on your Sim Hierarchy tab (on the left side, beside Process View), choose the signal you need, drag and drop it inside the simulation graphic and you're done. Then re-run the simulation to see their behaviour. MarcoArticle: 96643
Hi, Matt Clement schrieb: > SEL, ADD are asynchronous to the clock. ADD is set by the user with a dip > switch to allow multiplexing. The SEL signal comes from the source and > determines which multiplexed address the source wants to talk to. The SEL > and ADD signals are only read on a rising CLK edge so they become synced on I see no clocking of the inputs, only the output and state are clocked. This leads to race conditions, regardless of your speedgrade, the function of your circuit is nondeterministic. Lets asume SEL is really stabel compared to CLK, ADD is really asynchronous. If ADD changes "near" a rising edge of CLK (take care of IO-delay and the delay of the clocknet) you may see the following cases: 1. New value for STATE based on new value for ADD, new value for LED based on old value for ADD (or vice versa) 2. New value for STATE and LED based on some bits of old ADD and some bits of new value for ADD 3. mixture of 1 and 2. You should clock every input at least once before using it, especially when using parallel inputs to avoid this problem occuring due to asynchronity. But even when clocking a parallel input you may face the problem that a change from 000 to 111 in your input results in a register content of 011. So you should think about synchronising mechanisms for the paralell input bye ThomasArticle: 96644
Michael Hennebry wrote: > This would have to happen automaticlly if the decision to go from > cosine to hyperbolic cotangent happened automatically. > It might not be preplannable if one does not necessarily know > what other sets of canned functions are currently connected. > This is an example of why one might want sub-millisecond > place and route times. Yep ... dynamic linking/loading of library modules is both powerful and important for fpga computers, just as it has been for traditional computers. Dynamic linking for an fpga is essentially a very fast place and route directly to the fpga. That is NOT todays ISE PAR and bitgen tools. > > Loading an entire bit stream is very time intensive ... loading a few > > collums is a LOT faster. > > There are tools that will allow loading a few columns. There are tools that do it, but not with offically documented interfaces independent of par/bitgen that open source developers can use. Some of these tools, like the JHDL place and route functions which do a load and go, as well as the ADB wire data base and router that was integrated into JHDLBits are ment to be open source, and were done in cooperation with Xilinx, but mix NDA access and publicly documented access to the technology. In theory those interfaces can be reverse engineered independent of the Xilinx EULA NDA and just used, but there is a grey area that in doing so and using the Xilinx tools, the open source developers are also needful of not accidentally violating the EULA NDA terms. There is plenty of room for Xilinx to litigate to force the open source teams to abandon that access, unless Xilinx just documents the interfaces used by JHDL and JHDLBits (and other similar projects like VPR for Virtex). It might mean getting a commitment from FSF, or other open source advocate, to back any possible litigation so an open source team can freely document the interfaces used by JHDL, JHDLBits, and similar projects inspite of Xilinx's willingness to litigate. When you look at where the sales are for Xilinx for the last 5 years, reconfigurable computing isn't even on the map. People have been talking about it for more than a decade, and it just hasn't been a serious market niche. I believe there is a huge chicken and the egg problem, which revolves around not having tool chains that specifically make it work as easily programming traditional ISA machines. No market, no good tools. No good tools, no market. Doing FpgaC with a good load and go back end that supports dynamic linking, and then building fpac centric libraries with established API's is a first step in breaking the chicken and egg problem. It's conceivable today to build high end FPGA machines which can break 10 petaflops using tools which produce highly parallel approaches for certain major simulation applications. It's actually not even that hard. The hard part, is not having tool chains which can factor the computationally intense kernels into both netlists and compact state machines or traditional ISA code and distribute the application across a few tens of thousand very large FPGA's, and a few thousand state machines or cpu cores. Preferably for some parallel dialicts of fortran, as well as C. I've actually pitched this several times last year as a straw man just to get the reaction and list of problems with building machines of this class. The SEU problem is high on the list, but easily managable for XC4V's with some novel packaging. The bleading edge problem .... IE nobody has done it, is certainly a problem for conservative data center types, along with some NIH issues. The biggest problem, is the lack of tools today which can scale large application netlists across 2,000-30,000 FPGAs to load and go, while handling the implict communications needs, which are tightly coupled to the architecture. For certain super computer sites, I believe the core work for their applications could be knocked off in as little as 10 man years, over less than a calendar year using some very strict KISS design and a well focused development team. It would take another couple years for the facility to completely mature by porting a traditional super computer software infrastructure to the hybrid architecture, and doing some extensive training about how to best use this resource. As super computer site projects go, a relatively small project. Since there are no huge FPGA machines, and no tools today, it's just an intellectual exercise to second guess what you can really do. Dreaming aside, it would be relatively straight forward today to write those math functions needed in any of the fpga C tools (Handel-C, Impulse C, or FpgaC) as traditional functions. There are existing ISA C functions for them, that would only take a few days to port to fpga's. I have a road map for FpgaC to port floating point applications to the compiler and target runtime environment, making it math friendly and efficient by mid to late summer anyway. Beside the pipelining and process features in the Feb 2006 beta-2 for FpgaC (nearly ready for release), there are a few other FpgaC special features we'll be adding for the next two betas, to better make FpgaC a good host language for math intensive highly parallel applications. Most of that can be done easily today, without direct compiler/linker support.Article: 96645
hi!
i am developing i2c master in FPGA. suppose ia m transmitting 1.
i have doubt whether data transition should be at mid edge of
scl when it is low or at the falling edge as in the below waveform.
scl -------------- ----------------------
| |
|
/ here
| / or |
|
------------------
----------------------------
|-------------------
| here |
SDA ----------------------
|------------------------------------
Article: 96646On Wed, 8 Feb 2006 07:18:46 +0100, "Jerome" <nospam@nospam.com> wrote: >Thanks Eric, >However concerning the 5V tolerance, i'm not sure it is necessary since the >D+ & D- level swing >stays in the 0V - 3.6 V range > >My first step will consist in measuring these levels with a scope Those levels are OK but in USB spec there is a tolerance to short to 5V requirement which is why it's mentioned. In a controlled environment you don't need 5V tolerance on the data inputs.Article: 96647
Hi, I have been trying to make an example work in the DK Design Suite but to no avail. Can anyone who has experience in DK help me? The example is listed under Celoxica\DK\Examples\VHDL\Examples2 and it is one of the example listed in the help file which teaches how to interface handel c with vhdl code. The example can be found by search "vhd" under the celoxica help. However after I compiled the example into an edf file, and try generate the .bit file under Xilinx 7.1 the following error message appears: ERROR:NgdBuild:604 - logical block 'B121_reg32x1k_test_hcc_39_main_registers' with type 'REG32X1K' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'REG32X1K' is not supported in target 'spartan2'. NGDBUILD Design Results Summary: Number of errors: 1 Number of warnings: 0 It seems as if the vhd file component REG32X1K isn't detected. One of the examples in the help file says To synthesize the VHDL, Verilog or EDIF integration examples, you must: 1.. Change the build configuration to EDIF, VHDL or Verilog as appropriate (Build>Set Active Configuration). 2.. For Verilog or VHDL examples, choose the HDL output style: select Project>Settings>Linker, and then chose an output style from the drop-down list. Choose the style that matches your RTL synthesis tool, or else choose Generic. 3.. For Verilog or VHDL examples, pass the DK-generated .v or .vhd files, the .v or .vhd example files (tt17446, reg32xlk or filter/wrapper) and the Handel-C support file (HandelC.v or HandelC.vhd) to your synthesis tool. If you are targeting a Xilinx platform you also need to pass the appropriate ROC file (xilroc.v or xilroc.vhd). 4.. Run place and route. However, I am unable to find any handelc.vhd or xilrox.vhd anywhere in the celoxica directory. Is there anything else I need to do to make this work? Thanks a lot.Article: 96648
> I see no clocking of the inputs, only the output and state are clocked. this is one solution - the source of the problem is a little deeper ... When you specify a timing constraint for you clock then the tools make sure that the delays between the flipflops are within the limit. Your input delay is still unspecified and the tools do not care about it! - you could specify input delays of your signal as a timing constraint and make sure that it is met ... - you could use input flipflops (this is easier) ... just register your input signals (with the same clock!) and make sure that those flipflops get placed at the IO block ... the delay from the pad to that first flipflop is fixed as there is only one possible and short route after that you should open your fpga editor and make sure that the input FFs are used (there may be some settings in your synthesis tool to make this happen) bye, MichaelArticle: 96649
Dolphin wrote: > Hello, > > I have the following system: > - A Spartan 3E 500 FPGA > - Some internal BRAM memory > - An external SPI flash > > The external SPI flash contains the instruction code. However I can't use > a bootloader because the internal BRAM memory is not big enough for all > the code. > We don't use an external memory because price is important for this design > (every $ counts). > > I would like to have the Microblaze fetching code from the SPI flash. The > problem is that I have to use the OPB SPI interface for this and this > interface is not a 'real' memory interface. If your 100MHz MicroBlaze fetches it's instruction directly from the Flash, this will require 64 clock cycles at 20MHz for each 32b instruction. This reduces the MicroBlaze instruction rate to about 330kHz. If the instruction cache is enabled then the speed should improve by 10-100 times, depending on code. Memory management is needed as the code exceeds the available memory. For a small application this is most simply done in software. For example, if your user interface is much larger than the application core, split it into a number of modules. Compile the user core and first level menu of the user interface into the base code memory area. Determine the free system code space. Compile the user interface modules to each fit into this space. On selecting an item on the configuration menu, copy the required overlay into the shared code memory area. > Has anyone had a similar problem? How did you solve it? I'm developing a processor which reads code 'phrases' from serial flash to improve performance further, without using a general cache. This is to target very small, or 'zero power' requirements. hth Jan Coombs. -- murray-microft ltd slidapro at <my-domain>
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