Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hey all, I was wondering how to write a software reset in C-code for the Xilinx Microblaze. Regards KarelArticle: 96601
Hi, why in ISE simulator (version 7.1 sp4) I'm only able to change input signal value on falling edges of the clock (both working with falling or rising edges of the clock within my process(clock) statement)? When graphically editing my tbw file I experienced I'm only able to work that way. ThanksArticle: 96602
Dolphin wrote: > I would like to have the Microblaze fetching code from the SPI flash. The > problem is that I have to use the OPB SPI interface for this and this > interface is not a 'real' memory interface. Even if you manage to hide that (behind a gazillion wait states) it's going to be painfully slow. You need to either implement pre-fetch and caching in BRAM, or more likely segment your code into various modules with a routine that loads and unloads them from BRAM as neeeded.Article: 96603
Hello I recently designed a basic serial in parallel out IO board that used an Altera MAX 7128slc84-10 chip. I was able to reliably get it to run as expected and everything was fine. I found that I could purchase the 7128slc84-15 chip for about half the price so I did, and now my same setup doesnt work. I recompiled the VHDL for the 15 speed grade chip without any problems and yet it does not run my program correctly. I have loaded a small test program on the 15 chip and it works fine and does what it should. My code is using an external clock to run the state machine so I dont understand why it makes any difference whether I use a -10 or a -15.. What should I look for to make this 15 grade chip run my code without problems?? Does a jump in speed make that big of a difference?Article: 96604
Hi, I'm trying to simulate my microblaze sw/hw using the virtual platfrom feature. The problem is that when i try to generate the VP I get the following message: ERROR:MDT - Error while running "make -f vpgen.make" Did any of you guys ever got it to work ? and if so can you expalin how ? Thanks, Mordehay.Article: 96605
<ALuPin@web.de> wrote in message news:1139308332.626061.130260@f14g2000cwb.googlegroups.com... WHY do Verilog users post in this newsgroup ? Rgds Andrés Why do responders keep the full cross-post list? - John_HArticle: 96606
"Matt Clement" <clement@nanotechsys.com> wrote in message news:%V3Gf.8650$Gg1.8100@trnddc03... > Hello > > I recently designed a basic serial in parallel out IO board that used an > Altera MAX 7128slc84-10 chip. I was able to reliably get it to run as > expected and everything was fine. I found that I could purchase the > 7128slc84-15 chip for about half the price so I did, and now my same setup > doesnt work. I recompiled the VHDL for the 15 speed grade chip without > any problems and yet it does not run my program correctly. I have loaded > a small test program on the 15 chip and it works fine and does what it > should. My code is using an external clock to run the state machine so I > dont understand why it makes any difference whether I use a -10 or > a -15.. > > What should I look for to make this 15 grade chip run my code without > problems?? Does a jump in speed make that big of a difference? Three questions: Did you respecify the -15 speed grade in the Quartus-II tool and do a complete recompile? How fast does the Quartus-II tool tell you your design can run? How fast is the clock you're providing?Article: 96607
Because the clock falling edge coincides with the "snap-to" setting? Usually, timing entry allows you to lock the edges to specified increments such as 10ns boundaries. "Marco" <marco@marylon.com> wrote in message news:1139327228.109518.199870@o13g2000cwo.googlegroups.com... > Hi, why in ISE simulator (version 7.1 sp4) I'm only able to change > input signal value on falling edges of the clock (both working with > falling or rising edges of the clock within my process(clock) > statement)? When graphically editing my tbw file I experienced I'm only > able to work that way. > Thanks >Article: 96608
I recently "upgraded" three of the systems here to use v8.1 of the XILINX ISE WebPack software, and its companion MXE simulator version, only to find that nothing at all works properly any longer. The schematic entry program, which was already thoroughly messed up in v7, doesn't seem to work correctly at all. Simulation of old, long-complete, projects is completely impossible, as is programming of the devices. I've also learned that XILINX no longer has phone support for such matters, and that the "web-based" model they've adopted for support takes much longer ( a week or so, when it used to take a day or two ) to raise quasi-human contact and begin to approach a solution. Further, the last three issues I've raised with their new support agency have resulted in no solution. Has anybody managed to get this thing to work properly? What have you RECENTLY experienced with support? Does this mean we have to abandon XILINX as a device vendor?Article: 96609
Hello John and thanks for the quick reply. 1. Yes I redefined the device to the -15 chip and recompiled the design in quartus-II. 2. after compiling the -15 it says internal clk fmax is 41.67Mhz and with it set as a -10 it says fmax is 51.02Mhz. 3. the external clock driving the state machine in the chip is only 5MHZ. "John_H" <johnhandwork@mail.com> wrote in message news:%84Gf.23953$wk5.16427@news02.roc.ny... > "Matt Clement" <clement@nanotechsys.com> wrote in message > news:%V3Gf.8650$Gg1.8100@trnddc03... >> Hello >> >> I recently designed a basic serial in parallel out IO board that used an >> Altera MAX 7128slc84-10 chip. I was able to reliably get it to run as >> expected and everything was fine. I found that I could purchase the >> 7128slc84-15 chip for about half the price so I did, and now my same >> setup doesnt work. I recompiled the VHDL for the 15 speed grade chip >> without any problems and yet it does not run my program correctly. I >> have loaded a small test program on the 15 chip and it works fine and >> does what it should. My code is using an external clock to run the state >> machine so I dont understand why it makes any difference whether I use >> a -10 or a -15.. >> >> What should I look for to make this 15 grade chip run my code without >> problems?? Does a jump in speed make that big of a difference? > > Three questions: > Did you respecify the -15 speed grade in the Quartus-II tool and do a > complete recompile? > How fast does the Quartus-II tool tell you your design can run? > How fast is the clock you're providing? >Article: 96610
Matt Clement wrote: (top posting fixed) > "John_H" <johnhandwork@mail.com> wrote in message > news:%84Gf.23953$wk5.16427@news02.roc.ny... > >>"Matt Clement" <clement@nanotechsys.com> wrote in message >>news:%V3Gf.8650$Gg1.8100@trnddc03... >> >>>Hello >>> >>>I recently designed a basic serial in parallel out IO board that used an >>>Altera MAX 7128slc84-10 chip. I was able to reliably get it to run as >>>expected and everything was fine. I found that I could purchase the >>>7128slc84-15 chip for about half the price so I did, and now my same >>>setup doesnt work. I recompiled the VHDL for the 15 speed grade chip >>>without any problems and yet it does not run my program correctly. I >>>have loaded a small test program on the 15 chip and it works fine and >>>does what it should. My code is using an external clock to run the state >>>machine so I dont understand why it makes any difference whether I use >>>a -10 or a -15.. >>> >>>What should I look for to make this 15 grade chip run my code without >>>problems?? Does a jump in speed make that big of a difference? >> >>Three questions: >> Did you respecify the -15 speed grade in the Quartus-II tool and do a >>complete recompile? >> How fast does the Quartus-II tool tell you your design can run? >> How fast is the clock you're providing? >> > > Hello John and thanks for the quick reply. > > 1. Yes I redefined the device to the -15 chip and recompiled the > design in quartus-II. > 2. after compiling the -15 it says internal clk fmax is 41.67Mhz > and with it set as a -10 it says fmax is 51.02Mhz. > 3. the external clock driving the state machine in the chip is only > 5MHZ. > As I read your post alarm bells started ringing, and I haven't been able to turn them off. The trigger was the phrase "run my program". It sounds like you are a software engineer without much experience with FPGA designs? You cannot think of that body of HDL code you've written as a 'program'. It's not. The 'D' in HDL stands for the 'description' of the logic that you want -- _not_ a 'program'. If you are clocking this thing at 5MHz and it fails to work, even though it thinks it can work at 42MHz, there is something that the tool is overlooking that you must help it with. You are probably violating a timing parameter that is not adequately described to your tool, and which you'll have to look at yourself. So here's some questions: What form of serial are you giving the thing? Is it synchronous? Could you be violating setup or hold requirements going from serial to parallel? Is your 5MHz clock your only clock (no 'strobe' inputs?) Did I leave something out? -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 96611
Matt Have you got any inputs that are not synchronous to your state machine, or you are not meeting setup and hold requirements? As well as clocking slower the set, hold and clock to output times will vary with speed grade as silicon batch variations. John Adair Enterpoint Ltd. - Soon to be the home of Hollybush1. The PC104Plus Spartan-3 Development Platform. http://www.enterpoint.co.uk "Matt Clement" <clement@nanotechsys.com> wrote in message news:Ox4Gf.137364$7l4.100383@trnddc05... > Hello John and thanks for the quick reply. > > 1. Yes I redefined the device to the -15 chip and recompiled the design > in quartus-II. > 2. after compiling the -15 it says internal clk fmax is 41.67Mhz and > with it set as a -10 it says fmax is 51.02Mhz. > 3. the external clock driving the state machine in the chip is only 5MHZ. > > > "John_H" <johnhandwork@mail.com> wrote in message > news:%84Gf.23953$wk5.16427@news02.roc.ny... >> "Matt Clement" <clement@nanotechsys.com> wrote in message >> news:%V3Gf.8650$Gg1.8100@trnddc03... >>> Hello >>> >>> I recently designed a basic serial in parallel out IO board that used an >>> Altera MAX 7128slc84-10 chip. I was able to reliably get it to run as >>> expected and everything was fine. I found that I could purchase the >>> 7128slc84-15 chip for about half the price so I did, and now my same >>> setup doesnt work. I recompiled the VHDL for the 15 speed grade chip >>> without any problems and yet it does not run my program correctly. I >>> have loaded a small test program on the 15 chip and it works fine and >>> does what it should. My code is using an external clock to run the state >>> machine so I dont understand why it makes any difference whether I use >>> a -10 or a -15.. >>> >>> What should I look for to make this 15 grade chip run my code without >>> problems?? Does a jump in speed make that big of a difference? >> >> Three questions: >> Did you respecify the -15 speed grade in the Quartus-II tool and do a >> complete recompile? >> How fast does the Quartus-II tool tell you your design can run? >> How fast is the clock you're providing? >> > >Article: 96612
Hi everyone, Ive got some questions about live insertion of S3 chips. I am designing an fpga module as well as a daughterboard that will receive the module. The main system contains an XC3S200 and is connected straight to headers on the board. Now the secondary board contains an XC9572XL cpld and connects to the XC3S200 directly through the headers. The main board as well as the daughter board contain their own power supply with shared ground. The way the boards are powered on and the order in which they are is totally arbitrary. The secondary board could be powered up and the main module not and it would be eventually plugged in or the main module could be on and vice versa. Would the procedures said above affect the S3 in terms of internal damages. AFAIK, there are clamp diodes on the IOs of the S3 that prevent their Vout/Vin voltage to go beyond their operating forward voltage + VccIO of the S3. Now, would this protect my chip if excessive voltage is applied to the IOs during an off state (no voltage is applied to my Vccint, Vccio, Vccaux of S3); that is, if the cpld is on and outputing 3.3V and my S3 is off... What will happen if also, my cpld is on and outputing 3.3V and my S3 is on and placing zeros on its outputs (in this case, i think a series resistor of 100ohm would take care of the excessive current). Thanks for any pointers JLAArticle: 96613
"Tim Wescott" <tim@seemywebsite.com> wrote in message news:746dnfeoHM1sRHXenZ2dnUVZ_tidnZ2d@web-ster.com... > Is your 5MHz clock your only clock (no 'strobe' inputs?) > To add to Tim's comments, have you gated this clock? Cheers, Syms.Article: 96614
All that you say about self-fluxing polyurethane wire and all the rest I have no problem with. However, to the best of my knowledge, Tefzel is not polyurethane: http://en.wikipedia.org/wiki/ETFE Pete HarrisonArticle: 96615
Symon wrote: > "Tim Wescott" <tim@seemywebsite.com> wrote in message > news:746dnfeoHM1sRHXenZ2dnUVZ_tidnZ2d@web-ster.com... > >>Is your 5MHz clock your only clock (no 'strobe' inputs?) >> > > To add to Tim's comments, have you gated this clock? > Cheers, Syms. > > Symon: Are you assuming a faster clock that could be used to gate the 5MHz one? Somehow I think that's Matt's _only_ clock. Matt: Have you met the rise and fall time specifications for the clock? I would expect this would cause more problems with a higher speed grade, but since the chips are binned it could just be that the lower speed grade parts have more skew which may or may not make them more sensitive to rise and fall times. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 96616
But note that the so-called "signed shift" only gives you a signed or arithmetic shift if it is used in a signed expression. In an unsigned expression, you get an unsigned or logical shift. It isn't really a "signed shift". It is a "shift using the signedness of the expression". It is what the ordinary shift operator should have been in the first place.Article: 96617
Hello everyone and many thanks for the replies.
I am a fairly "generic" guy so excuse my "generic" reference to the program.
I am an EE with specialization in digital logic design. The serial is a
basic bit bang serial 32 bit stream that relates to 32 inputs. I simply
read them in serially and then dump them parallel to 32 LED's. The clock
for the serial data is provided by the source system and its 5 Mhz. The
simulation of the "program" in Quartus verifies that it should be doing
exactly what I want (in theory..haha). It works fine with the -10 part but
when I swap with a compiled, programmed -15 it fails to function. I would
have thought the -15 would be faster but according to the compiler, it's
Fmax is slower. The simulation for the -15 also works fine. I spent the
better part of the morning scratching my head over this one.
here is the basic "program"
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CLONE34 IS
PORT
(clk : IN BIT;
SEL : IN BIT_VECTOR(7 DOWNTO 0);
ADD : IN BIT_VECTOR(5 DOWNTO 0);
DAT : INOUT BIT_VECTOR(1 DOWNTO 0);
LED1 : OUT BIT_VECTOR(31 DOWNTO 0));
END CLONE34;
ARCHITECTURE ONE OF CLONE34 IS
TYPE STATE_TYPE IS
(IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34);
SIGNAL STATE: STATE_TYPE;
BEGIN
PROCESS (clk, ADD)
VARIABLE DATA : BIT_VECTOR(35 DOWNTO 0);
BEGIN
IF (clk'EVENT AND clk = '1')THEN
DAT(0)<='0';
CASE STATE IS
WHEN IDLE =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(35):=SEL(1);
STATE<=S0;
ELSE
STATE<=IDLE;
END IF;
WHEN S0 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(34):=SEL(1);
STATE <= S1;
ELSE
STATE<=IDLE;
END IF;
WHEN S1 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(33):=SEL(1);
STATE <= S2;
ELSE
STATE<=IDLE;
END IF;
WHEN S2 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(32):=SEL(1);
STATE <= S3;
ELSE
STATE<=IDLE;
END IF;
WHEN S3 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(31):=SEL(1);
STATE <= S4;
ELSE
STATE<=IDLE;
END IF;
WHEN S4 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(30):=SEL(1);
STATE <= S5;
ELSE
STATE<=IDLE;
END IF;
WHEN S5 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(29):=SEL(1);
STATE <= S6;
ELSE
STATE<=IDLE;
END IF;
WHEN S6 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(28):=SEL(1);
STATE <= S7;
ELSE
STATE<=IDLE;
END IF;
WHEN S7 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(27):=SEL(1);
STATE <= S8;
ELSE
STATE<=IDLE;
END IF;
WHEN S8 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(26):=SEL(1);
STATE <= S9;
ELSE
STATE<=IDLE;
END IF;
WHEN S9 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(25):=SEL(1);
STATE <= S10;
ELSE
STATE<=IDLE;
END IF;
WHEN S10 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(24):=SEL(1);
STATE <= S11;
ELSE
STATE<=IDLE;
END IF;
WHEN S11 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(23):=SEL(1);
STATE <= S12;
ELSE
STATE<=IDLE;
END IF;
WHEN S12 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(22):=SEL(1);
STATE <= S13;
ELSE
STATE<=IDLE;
END IF;
WHEN S13 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(21):=SEL(1);
STATE <= S14;
ELSE
STATE<=IDLE;
END IF;
WHEN S14 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(20):=SEL(1);
STATE <= S15;
ELSE
STATE<=IDLE;
END IF;
WHEN S15 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(19):=SEL(1);
STATE <= S16;
ELSE
STATE<=IDLE;
END IF;
WHEN S16 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(18):=SEL(1);
STATE <= S17;
ELSE
STATE<=IDLE;
END IF;
WHEN S17 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(17):=SEL(1);
STATE <= S18;
ELSE
STATE<=IDLE;
END IF;
WHEN S18 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(16):=SEL(1);
STATE <= S19;
ELSE
STATE<=IDLE;
END IF;
WHEN S19 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(15):=SEL(1);
STATE <= S20;
ELSE
STATE<=IDLE;
END IF;
WHEN S20 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(14):=SEL(1);
STATE <= S21;
ELSE
STATE<=IDLE;
END IF;
WHEN S21 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(13):=SEL(1);
STATE <= S22;
ELSE
STATE<=IDLE;
END IF;
WHEN S22 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(12):=SEL(1);
STATE <= S23;
ELSE
STATE<=IDLE;
END IF;
WHEN S23 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(11):=SEL(1);
STATE <= S24;
ELSE
STATE<=IDLE;
END IF;
WHEN S24 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(10):=SEL(1);
STATE <= S25;
ELSE
STATE<=IDLE;
END IF;
WHEN S25 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(9):=SEL(1);
STATE <= S26;
ELSE
STATE<=IDLE;
END IF;
WHEN S26 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(8):=SEL(1);
STATE <= S27;
ELSE
STATE<=IDLE;
END IF;
WHEN S27 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(7):=SEL(1);
STATE <= S28;
ELSE
STATE<=IDLE;
END IF;
WHEN S28 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(6):=SEL(1);
STATE <= S29;
ELSE
STATE<=IDLE;
END IF;
WHEN S29 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(5):=SEL(1);
STATE <= S30;
ELSE
STATE<=IDLE;
END IF;
WHEN S30 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(4):=SEL(1);
STATE <= S31;
ELSE
STATE<=IDLE;
END IF;
WHEN S31 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(3):=SEL(1);
STATE <= S32;
ELSE
STATE<=IDLE;
END IF;
WHEN S32 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(2):=SEL(1);
STATE <= S33;
ELSE
STATE<=IDLE;
END IF;
WHEN S33 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(1):=SEL(1);
STATE <= S34;
ELSE
STATE<=IDLE;
END IF;
WHEN S34 =>
DAT(0)<='1';
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(0):=SEL(1);
STATE <= IDLE;
--THIS IS WHERE WE WOULD DO OUR PARITY CHECK FOR INCOMING DATA
--DATA(35,34,33,32) = PARITY4,3,2,1
--IF PARITY1=BLAH BLAH AND
-- PARITY2=BLAH BLAH AND
-- PARITY3=BLAH BLAH AND
-- PARITY4=BLAH BLAH THEN
LED1(31 downto 0)<=DATA(31 downto 0);
--END IF;
ELSE
STATE<=IDLE;
END IF;
END CASE;
ELSE
END IF;
END PROCESS;
END ONE;
"John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in
message news:1139333636.27736.0@lotis.uk.clara.net...
> Matt
>
> Have you got any inputs that are not synchronous to your state machine, or
> you are not meeting setup and hold requirements? As well as clocking
> slower the set, hold and clock to output times will vary with speed grade
> as silicon batch variations.
>
> John Adair
> Enterpoint Ltd. - Soon to be the home of Hollybush1. The PC104Plus
> Spartan-3 Development Platform.
> http://www.enterpoint.co.uk
>
>
> "Matt Clement" <clement@nanotechsys.com> wrote in message
> news:Ox4Gf.137364$7l4.100383@trnddc05...
>> Hello John and thanks for the quick reply.
>>
>> 1. Yes I redefined the device to the -15 chip and recompiled the design
>> in quartus-II.
>> 2. after compiling the -15 it says internal clk fmax is 41.67Mhz and
>> with it set as a -10 it says fmax is 51.02Mhz.
>> 3. the external clock driving the state machine in the chip is only
>> 5MHZ.
>>
>>
>> "John_H" <johnhandwork@mail.com> wrote in message
>> news:%84Gf.23953$wk5.16427@news02.roc.ny...
>>> "Matt Clement" <clement@nanotechsys.com> wrote in message
>>> news:%V3Gf.8650$Gg1.8100@trnddc03...
>>>> Hello
>>>>
>>>> I recently designed a basic serial in parallel out IO board that used
>>>> an Altera MAX 7128slc84-10 chip. I was able to reliably get it to run
>>>> as expected and everything was fine. I found that I could purchase the
>>>> 7128slc84-15 chip for about half the price so I did, and now my same
>>>> setup doesnt work. I recompiled the VHDL for the 15 speed grade chip
>>>> without any problems and yet it does not run my program correctly. I
>>>> have loaded a small test program on the 15 chip and it works fine and
>>>> does what it should. My code is using an external clock to run the
>>>> state machine so I dont understand why it makes any difference whether
>>>> I use a -10 or a -15..
>>>>
>>>> What should I look for to make this 15 grade chip run my code without
>>>> problems?? Does a jump in speed make that big of a difference?
>>>
>>> Three questions:
>>> Did you respecify the -15 speed grade in the Quartus-II tool and do a
>>> complete recompile?
>>> How fast does the Quartus-II tool tell you your design can run?
>>> How fast is the clock you're providing?
>>>
>>
>>
>
>
Article: 96618al99999 wrote: > Hi, > > Has anybody ever designed anything to decode and display GPS NMEA data > coming out in ascii form from a UART? > > Any ideas of where to start or how to go about decoding comma delimted > ascii strings? A micro controller is much better suited for this type of job Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 96619
Okay guys According to the datasheet the -15 is slower than the -10. The prop delay max for each is 10ns and 15ns thus the speed grades. So the slower speed by 5ns is causing it to fail on the slower chip.....hmmm. The setup and hold times for the system are around 100ns so I dont know why its causing so much trouble. Matt "Matt Clement" <clement@nanotechsys.com> wrote in message news:vw5Gf.9710$In4.2864@trnddc06... > Hello everyone and many thanks for the replies. > > I am a fairly "generic" guy so excuse my "generic" reference to the > program. I am an EE with specialization in digital logic design. The > serial is a basic bit bang serial 32 bit stream that relates to 32 > inputs. I simply read them in serially and then dump them parallel to 32 > LED's. The clock for the serial data is provided by the source system and > its 5 Mhz. The simulation of the "program" in Quartus verifies that it > should be doing exactly what I want (in theory..haha). It works fine with > the -10 part but when I swap with a compiled, programmed -15 it fails to > function. I would have thought the -15 would be faster but according to > the compiler, it's Fmax is slower. The simulation for the -15 also works > fine. I spent the better part of the morning scratching my head over > this one. > > here is the basic "program" > > LIBRARY IEEE; > USE IEEE.STD_LOGIC_1164.ALL; > > > ENTITY CLONE34 IS > PORT > (clk : IN BIT; > SEL : IN BIT_VECTOR(7 DOWNTO 0); > ADD : IN BIT_VECTOR(5 DOWNTO 0); > DAT : INOUT BIT_VECTOR(1 DOWNTO 0); > LED1 : OUT BIT_VECTOR(31 DOWNTO 0)); > > END CLONE34; > > ARCHITECTURE ONE OF CLONE34 IS > TYPE STATE_TYPE IS > (IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34); > SIGNAL STATE: STATE_TYPE; > > BEGIN > > PROCESS (clk, ADD) > VARIABLE DATA : BIT_VECTOR(35 DOWNTO 0); > BEGIN > > IF (clk'EVENT AND clk = '1')THEN > > DAT(0)<='0'; > CASE STATE IS > WHEN IDLE => > > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(35):=SEL(1); > STATE<=S0; > > > ELSE > STATE<=IDLE; > > END IF; > > WHEN S0 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(34):=SEL(1); > STATE <= S1; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S1 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(33):=SEL(1); > > STATE <= S2; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S2 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(32):=SEL(1); > > STATE <= S3; > ELSE > STATE<=IDLE; > END IF; > WHEN S3 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(31):=SEL(1); > > STATE <= S4; > ELSE > STATE<=IDLE; > END IF; > WHEN S4 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(30):=SEL(1); > > STATE <= S5; > ELSE > STATE<=IDLE; > END IF; > WHEN S5 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(29):=SEL(1); > > STATE <= S6; > ELSE > STATE<=IDLE; > END IF; > > WHEN S6 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(28):=SEL(1); > > STATE <= S7; > ELSE > STATE<=IDLE; > END IF; > > WHEN S7 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(27):=SEL(1); > > STATE <= S8; > ELSE > STATE<=IDLE; > END IF; > WHEN S8 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(26):=SEL(1); > > STATE <= S9; > ELSE > STATE<=IDLE; > END IF; > > WHEN S9 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(25):=SEL(1); > > STATE <= S10; > ELSE > STATE<=IDLE; > END IF; > WHEN S10 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(24):=SEL(1); > > STATE <= S11; > ELSE > STATE<=IDLE; > END IF; > WHEN S11 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(23):=SEL(1); > > STATE <= S12; > ELSE > STATE<=IDLE; > END IF; > WHEN S12 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(22):=SEL(1); > > STATE <= S13; > ELSE > STATE<=IDLE; > END IF; > WHEN S13 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(21):=SEL(1); > > STATE <= S14; > ELSE > STATE<=IDLE; > END IF; > WHEN S14 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(20):=SEL(1); > > STATE <= S15; > ELSE > STATE<=IDLE; > END IF; > WHEN S15 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(19):=SEL(1); > > STATE <= S16; > ELSE > STATE<=IDLE; > END IF; > WHEN S16 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(18):=SEL(1); > > STATE <= S17; > ELSE > STATE<=IDLE; > END IF; > WHEN S17 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(17):=SEL(1); > > STATE <= S18; > ELSE > STATE<=IDLE; > END IF; > > WHEN S18 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(16):=SEL(1); > > STATE <= S19; > ELSE > STATE<=IDLE; > END IF; > WHEN S19 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(15):=SEL(1); > > STATE <= S20; > ELSE > STATE<=IDLE; > END IF; > > WHEN S20 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(14):=SEL(1); > > STATE <= S21; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S21 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(13):=SEL(1); > > STATE <= S22; > ELSE > STATE<=IDLE; > END IF; > > > > WHEN S22 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(12):=SEL(1); > > STATE <= S23; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S23 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(11):=SEL(1); > > STATE <= S24; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S24 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(10):=SEL(1); > > STATE <= S25; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S25 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(9):=SEL(1); > > STATE <= S26; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S26 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(8):=SEL(1); > > STATE <= S27; > ELSE > STATE<=IDLE; > END IF; > > > > WHEN S27 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(7):=SEL(1); > > STATE <= S28; > ELSE > STATE<=IDLE; > END IF; > > > > WHEN S28 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(6):=SEL(1); > > STATE <= S29; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S29 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(5):=SEL(1); > > STATE <= S30; > ELSE > STATE<=IDLE; > END IF; > > > > WHEN S30 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(4):=SEL(1); > > STATE <= S31; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S31 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(3):=SEL(1); > > STATE <= S32; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S32 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(2):=SEL(1); > > STATE <= S33; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S33 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(1):=SEL(1); > > STATE <= S34; > > ELSE > STATE<=IDLE; > END IF; > > WHEN S34 => > DAT(0)<='1'; > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(0):=SEL(1); > > STATE <= IDLE; > > --THIS IS WHERE WE WOULD DO OUR PARITY CHECK FOR INCOMING DATA > --DATA(35,34,33,32) = PARITY4,3,2,1 > --IF PARITY1=BLAH BLAH AND > -- PARITY2=BLAH BLAH AND > -- PARITY3=BLAH BLAH AND > -- PARITY4=BLAH BLAH THEN > > LED1(31 downto 0)<=DATA(31 downto 0); > > --END IF; > > > ELSE > STATE<=IDLE; > > > END IF; > END CASE; > ELSE > > > END IF; > END PROCESS; > END ONE; > > > > > > > "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote > in message news:1139333636.27736.0@lotis.uk.clara.net... >> Matt >> >> Have you got any inputs that are not synchronous to your state machine, >> or you are not meeting setup and hold requirements? As well as clocking >> slower the set, hold and clock to output times will vary with speed grade >> as silicon batch variations. >> >> John Adair >> Enterpoint Ltd. - Soon to be the home of Hollybush1. The PC104Plus >> Spartan-3 Development Platform. >> http://www.enterpoint.co.uk >> >> >> "Matt Clement" <clement@nanotechsys.com> wrote in message >> news:Ox4Gf.137364$7l4.100383@trnddc05... >>> Hello John and thanks for the quick reply. >>> >>> 1. Yes I redefined the device to the -15 chip and recompiled the design >>> in quartus-II. >>> 2. after compiling the -15 it says internal clk fmax is 41.67Mhz and >>> with it set as a -10 it says fmax is 51.02Mhz. >>> 3. the external clock driving the state machine in the chip is only >>> 5MHZ. >>> >>> >>> "John_H" <johnhandwork@mail.com> wrote in message >>> news:%84Gf.23953$wk5.16427@news02.roc.ny... >>>> "Matt Clement" <clement@nanotechsys.com> wrote in message >>>> news:%V3Gf.8650$Gg1.8100@trnddc03... >>>>> Hello >>>>> >>>>> I recently designed a basic serial in parallel out IO board that used >>>>> an Altera MAX 7128slc84-10 chip. I was able to reliably get it to run >>>>> as expected and everything was fine. I found that I could purchase >>>>> the 7128slc84-15 chip for about half the price so I did, and now my >>>>> same setup doesnt work. I recompiled the VHDL for the 15 speed grade >>>>> chip without any problems and yet it does not run my program >>>>> correctly. I have loaded a small test program on the 15 chip and it >>>>> works fine and does what it should. My code is using an external clock >>>>> to run the state machine so I dont understand why it makes any >>>>> difference whether I use a -10 or a -15.. >>>>> >>>>> What should I look for to make this 15 grade chip run my code without >>>>> problems?? Does a jump in speed make that big of a difference? >>>> >>>> Three questions: >>>> Did you respecify the -15 speed grade in the Quartus-II tool and do a >>>> complete recompile? >>>> How fast does the Quartus-II tool tell you your design can run? >>>> How fast is the clock you're providing? >>>> >>> >>> >> >> > >Article: 96620
Thanks, fpga_toys. I'm still a bit fuzzy on the subject. Please keep reading and let me know what I get wrong. fpga_toys@yahoo.com wrote: > Michael Hennebry wrote: > > I've recently read some articles stating > > that a realy fast place and route algorithm > > for fpgas would be a good thing. > > In this case, "really fast" means sub-second > > or even sub-millisecond. > > For what kind of applications would one > > need such fast "compile" times? > > Compile time is a completely different issue. In using an FPGA as > a processor (for netlists) the practice of dynamic linking becomes > just as useful for FPGA's as it is for processors. Consider that your > operating system is loaded with hundreds/thousands of dll's and .so > objects for libraries and small modules. It's actually more useful, as > the amount of "memory" (AKA LUT's) in an FPGA is smaller, a LOT > smaller, so the practice of swapping/paging in smaller netlist seqments > will be a necessary tool to avoid completely reloading an entire FPGA > image in the form of a freash bitstream. If one has an fpga set up to do interesting things with cosines and wants to move on to doing those same interesting things with hyperbolic cotangents one can declare the cosine LUTs unassigned and place and route LUTs for the hyperbolic cotangent and connections to the rest of the fgpa leaving the assigned LUTs with their previous assignment. This would have to happen automaticlly if the decision to go from cosine to hyperbolic cotangent happened automatically. It might not be preplannable if one does not necessarily know what other sets of canned functions are currently connected. This is an example of why one might want sub-millisecond place and route times. > How many times do you compile a program? ... How many times do > you execute/dynamically link an object to run it? Link and go times > are much more important than compile times, except maybe for > very large programs that a programmer is debugging. My example above corresponds to a link and go. > Loading an entire bit stream is very time intensive ... loading a few > collums is a LOT faster. There are tools that will allow loading a few columns.Article: 96621
"Tim Wescott" <tim@seemywebsite.com> wrote in message news:Ur6dnY0U0o5Hf3XenZ2dnUVZ_sWdnZ2d@web-ster.com... > Symon wrote: > >> "Tim Wescott" <tim@seemywebsite.com> wrote in message >> news:746dnfeoHM1sRHXenZ2dnUVZ_tidnZ2d@web-ster.com... >> >>>Is your 5MHz clock your only clock (no 'strobe' inputs?) >>> >> >> To add to Tim's comments, have you gated this clock? >> Cheers, Syms. > Symon: > > Are you assuming a faster clock that could be used to gate the 5MHz one? > Somehow I think that's Matt's _only_ clock. > Hi Tim, I've seen people drive a state machine with a clock, then use the output of this state machine to gate the clock for other bits of circuitry. To make it slower or to save power. Right. Yuk. Sounds like Matt's not doing that, good for him! Cheers, Syms.Article: 96622
Hello Symon No i am not gating the clock....at least not on purpose. The clock for the system comes from an external source and is at 5Mhz. I use it to transition the state machine. The compiler says my slowest delay still lets me run at around 50Mhz so that should be okay. I noticed that I am checking the address in each state when I could probably just check it before the case statement and get the same effect?? Thanks Matt "Symon" <symon_brewer@hotmail.com> wrote in message news:43e8fa42$0$15790$14726298@news.sunsite.dk... > "Tim Wescott" <tim@seemywebsite.com> wrote in message > news:Ur6dnY0U0o5Hf3XenZ2dnUVZ_sWdnZ2d@web-ster.com... >> Symon wrote: >> >>> "Tim Wescott" <tim@seemywebsite.com> wrote in message >>> news:746dnfeoHM1sRHXenZ2dnUVZ_tidnZ2d@web-ster.com... >>> >>>>Is your 5MHz clock your only clock (no 'strobe' inputs?) >>>> >>> >>> To add to Tim's comments, have you gated this clock? >>> Cheers, Syms. >> Symon: >> >> Are you assuming a faster clock that could be used to gate the 5MHz one? >> Somehow I think that's Matt's _only_ clock. >> > Hi Tim, > I've seen people drive a state machine with a clock, then use the output > of this state machine to gate the clock for other bits of circuitry. To > make it slower or to save power. Right. Yuk. Sounds like Matt's not doing > that, good for him! > Cheers, Syms. >Article: 96623
"Matt Clement" <clement@nanotechsys.com> wrote in message news:nH5Gf.9713$In4.1274@trnddc06... >> >> ENTITY CLONE34 IS >> PORT >> (clk : IN BIT; >> SEL : IN BIT_VECTOR(7 DOWNTO 0); >> ADD : IN BIT_VECTOR(5 DOWNTO 0); >> DAT : INOUT BIT_VECTOR(1 DOWNTO 0); >> LED1 : OUT BIT_VECTOR(31 DOWNTO 0)); >> Hey Matt, Are SEL, ADD, DAT synchronous to the clk? And, if so, do they meet the setup and hold requirements for the rising edge of the clock? Cheers, Syms.Article: 96624
Hello Symon SEL, ADD are asynchronous to the clock. ADD is set by the user with a dip switch to allow multiplexing. The SEL signal comes from the source and determines which multiplexed address the source wants to talk to. The SEL and ADD signals are only read on a rising CLK edge so they become synced on the destination side. DAT is not used for anything in the design and is left unconnected for now. Matt "Symon" <symon_brewer@hotmail.com> wrote in message news:43e8fb50$0$15792$14726298@news.sunsite.dk... > "Matt Clement" <clement@nanotechsys.com> wrote in message > news:nH5Gf.9713$In4.1274@trnddc06... >>> >>> ENTITY CLONE34 IS >>> PORT >>> (clk : IN BIT; >>> SEL : IN BIT_VECTOR(7 DOWNTO 0); >>> ADD : IN BIT_VECTOR(5 DOWNTO 0); >>> DAT : INOUT BIT_VECTOR(1 DOWNTO 0); >>> LED1 : OUT BIT_VECTOR(31 DOWNTO 0)); >>> > Hey Matt, > Are SEL, ADD, DAT synchronous to the clk? And, if so, do they meet the > setup and hold requirements for the rising edge of the clock? > Cheers, Syms. >
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z