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Xilinx Multi-Channel SDRAM Memory controller has 4 XCL ports. Microblaze > uses 2 port. > Now I should develop a XCL Master interface and connect it to one of the 2 > free ports. Marco, I need to the the same thing. Let's keep in touch one each other! Besides... if your english is a problem... are you Italian ? I am. I'll have a MB connected to OPB, using 2 XCL ports for cache; MCH_SDRAM_OPB, some UARTs, all on OPB. Then I need to develop two XCL "masters" to read/write high speed data from the remaining two XCL channels. Can we help one each other ?Article: 95951
Hi Marco, Maybe your 'scope and probe measurement combination is the limiting factor? Can you tell us what setup you have? Are you using a FET probe? Cheers, Syms. "Marco" <marco@marylon.com> wrote in message news:1138357376.575109.268200@g44g2000cwa.googlegroups.com... > Antti, I attached an oscilloscope on the 2 pins I use to read the same > signal. The first pin is set to FAST, the other one to SLOW, but their > rise and fall bahaviour is identical, I can overlap the 2 traces on the > screen, so I think I'm wrong somewhere, even if on the .pad_txt file > they appear to be correctly set. > Marco >Article: 95952
Antti wrote: > > the default IOBANK VCC is different in different devices so if you use 3.3V > standard in an bank that has any IO not set to 3.3 (eg left defualt) then > the defaults (on S3) will yield to 2.5 and causes PAR to fail. > > in designs for modern Xilinx FPGAs S3/V4 it is recommended (my > recommendation) to specify IOSTANDARD for ALL USED pins (located or not) > only then you are sure that there will be no conflicts during PAR. > > Antti Another related item worth noting: you used to be able to put HDL pin attributes in the top level code to avoid UCF errors on unused pins; however, version 7.1sp4 of XST/ISE coughs up an error on this construct because the unused input defaults back to 2.5V banking, even though you told it otherwise! I posted some example code and notes over here: http://groups.google.com/group/comp.arch.fpga/msg/afce49b66c1989aa http://groups.google.com/group/comp.arch.fpga/msg/8955e7209e0c3929 > > There is a 7.1iSP4 bug with assigning IOSTANDARDs and LOCS >using HDL attributes. Unused LOC'd inputs drop their IOSTANDARD >definitions and default back to LVCMOS25, causing banking errors. > BrianArticle: 95953
"Pete Hudson" <pete.hudson@baesystems.com> wrote in message news:1138358605.349842.85640@z14g2000cwz.googlegroups.com... >I have been presented with a c program to implement on an fpga. > I am investigating the possible processes/tools I could employ rather > than a straight rewrite in VHDL. > > Current candidates are: > > Impulse C > Handel-C > Xilinx System Generator > > The algorithm is littered with sin cos sqrt & divides. So I expect that > I require some of the xilinx IP cores that come with my ISE tool. > (That's why XSG is getting a look in) > > Q. How do I implement this algorithm's cos functions (for example) in > Impulse C so that it is represented in the resultant HW? > Hi Pete, There's a guy here on CAF who's something to do with FpgaC. http://fpgac.sourceforge.net/ Perhaps you could ask him to help implement the COS function, he seems to be at a loose end! ;-) Back in the real world, I think you're gonna have to code this in an HDL. I suggest doing some research on CORDIC algorithms. Alternatively, For SIN/COS you might consider the Sunderland algorithm and the sine-phase difference algorithm. For square roots, I like this:- http://lib.tkk.fi/Diss/2005/isbn9512275279/article3.pdf HTH. Cheers, Syms.Article: 95954
I'm using a Tektronix TDS5054 and, after better tuning it all, I find rise times to be (fast-slow): 1.6ns and 1.9ns (drive=16, IOSTANDARD=LVCMOS33) 1.4ns and 1.8ns (drive=24, IOSTANDARD=LVCOMS33) 9ns and 6ns (drive=2, IOSTANDARD=LVCOMS33), yes 9-6, not 6-9 Are these (mainly the first and the second) reasonable? Thanks, MarcoArticle: 95955
Grey Beard wrote: > I'm quite new to this area..I'm completeing a bachelor in > electronics..As a part of my project i'm to create a sdram controller > for xilinx 11 pro(ff1152) based memec board...Although memory managent > is available as a ref design..We are not using the power processor > inside?Can anyone give me some directions on this one?i'd be grateful.. > Search this group for the thread "Xilinx ML402 DRAM control" --- Joe SamsonArticle: 95956
Marco, What's the probe's impedance? Also, the Tektronix TDS5054 appears to be a 500MHz bandwidth 'scope. This bandwidth limitation will be having an effect on your measurements. Cheers, Syms. "Marco" <marco@marylon.com> wrote in message news:1138365416.594454.310730@g14g2000cwa.googlegroups.com... > I'm using a Tektronix TDS5054 and, after better tuning it all, I find > rise times to be (fast-slow): > 1.6ns and 1.9ns (drive=16, IOSTANDARD=LVCMOS33) > 1.4ns and 1.8ns (drive=24, IOSTANDARD=LVCOMS33) > 9ns and 6ns (drive=2, IOSTANDARD=LVCOMS33), yes 9-6, not 6-9 > Are these (mainly the first and the second) reasonable? > Thanks, Marco >Article: 95957
They're 11.1pF and 10MOhm, also 500Mhz bandwith. MarcoArticle: 95958
Brian, thanks for the links, I also work with ISE 7.1SP4 MarcoArticle: 95959
Hi Marco, So, for a cap V = Q / C. Let's say we want 3V rise, C = 11pF, we can drive 24mA, so 3 = 24mA * t / 11pF , where t is time. t = 3 * 11pF / 24mA = 1.375 ns. You can see the probe's capacitance is limiting the rise time you're measuring. 24mA takes 1.4 nS to charge the 'scope probe's capacitance. I think you need a faster scope and a FET probe, maybe 2GHz and a probe capacitance of 1-2pF. Or ask Xilinx for some data? HTH, Syms. "Marco" <marco@marylon.com> wrote in message news:1138366454.747563.55520@g49g2000cwa.googlegroups.com... > They're 11.1pF and 10MOhm, also 500Mhz bandwith. > Marco >Article: 95960
Symon, thanks, do agree with what you wrote, it's straight and simple. ThanksArticle: 95961
"Larry Doolittle" <ldoolitt@localhost.localdomain> schrieb im Newsbeitrag news:slrndti8og.2a7.ldoolitt@localhost.localdomain... > On 2006-01-26, Antti Lukats <antti@openchip.org> wrote: >><fpga_toys@yahoo.com> schrieb im Newsbeitrag >> news:1138297173.649950.136370@g14g2000cwa.googlegroups.com... >>> So the question to Xilinx is, will Xilinx release the NDA restrictions >>> on XDL, and the associated library interfaces so that open source tools >>> can legally target ISE supported FPGAs? >>> >>> It's pretty clear that most of the regulars here, just assume that XDL >>> and the associated libraries, are an open interface, and think it's ok >>> to ignore the IP restrictions in the ISE license. The legaleze says >>> otherwise. >>> >>> So how about a clear definative legal statement about what are legal >>> ISE interfaces for open source development. >>> >> >> you are constantly talking about NDA restricted XDL documents, as if you >> have signed an NDA with Xilinx and received special documents under that >> NDA >> agreement, in wich case its better for you that read those NDA agreements >> (signed by you and Xilinx) over again. If you have not signed such >> agreements then stop talking about NDA in this context. > > The conservative assumption is that the EULA we all click when > we install ISE is a valid document, and it has NDA-like clauses. > The poster has clearly read that NDA very carefully. > If you live in a country where such agreements are non-binding, > let us know here. Then software developers in that country can > proceed without fear -- until Xilinx stops exporting chips and > software to that country for the same reason. > >> As of your Question to Xilinx - do not expect an reply as it totally >> unclear >> what you are actually asking as you have not defined that. > > It's clear to me. Are you being willfully disingenuous? > Well, maybe some clarification should be made of the phrase > "associated library interfaces". > >> In the form you >> asked your question it would deserve a "NO" as replay from any entity >> that >> has any understanding of legal matters. Xilinx can not say YES to your >> question. Well you probably know that yourself. So what are you trying to >> achive with your push? > > In the short run, maybe the regulars will admit that XDL can not > currently be considered an open interface. In the long run, maybe > we can pressure Xilinx to remove NDA restrictions on information > contained in XDL data files, to permit open source code to monkey > with FPGA internals (without fear of being JHDLBits-ized). Presumably > that means Xilinx's engineers and lawers have to have a serious > talk, since a Xilinx lawyer can hardly be expected to say "YES" > to a request he doesn't understand. > > Only after this is resolved, can the regulars here go back to > telling people who want to make bitstreams with open source > software to use XDL instead. > > - Larry Larry you are mixing up things. the EULA is not NDA, and there is no sign off of an NDA required to obtain acces to XDL, at least I am 100% that I have not signed any NDA with Xilinx or any other FPGA company. mr fpga_toys asked for in such form that answering YES would have mean for Xilinx as an commitment to open source almost everything, hence my comment that only answer is no. and you are also messing up 'creation of bitstream' and XDL - XDL files and NCD files contain exactly NULL information about the actual bitstream format. So it doesnt matter what is the license of the use of XDL it is not sufficent to create bitststreams anyway. if it did not come clear: XDL (and NCD as well) do not have any information about the bitstream (eg location of bits in the configuration memory of the FPGA). -- Antti Lukats http://www.xilant.comArticle: 95962
Dominik Froehlich wrote: > hi, > > for some devices xilinx ise offers an option to convert internal > tristate buffers to equivalent logic. however, i cannot find any > information how this works in detail. > > i understand that all tristate buffers driving one signal can be > replaced by a multiplexer or equivalent logic. the problem is how the > selector logic is derived from the original enable signals. if multiple > enables are active concurrently, is there a sort of prioritization? > > why is the conversion restricted to specific devices? > > any hint, or even conference papers, manuals, etc. are very welcome. > > thank you in advance. > > dominik The data sheet for the tristate emulators in the earliest families that got rid of tristates described the situation beautifully; I would expect the synthesis to do the same but I can't guarantee 100%: When no enables are active, result is logic 1. When a single enable is active, the result is the signal controlled by that enable. When more than one enable is active, the result is logic zero if *any* of the inputs are a zero, otherwise 1.... Effectively it becomes an AND function of the enabled inputs. But it's never good design practice to have tristates with multiple sources; that was a good way to put a crach in the old XC4000 parts if I recall those days long gone correctly. I've done multiple enabled sources myself with good results where the hardware emulation was described in the datasheet so very well but wouldn't have done it without that backup info.Article: 95963
Hello out there, here's still anyone who uses this !! over the last years I used Foundation 4.1, Top-Level is schematic. Now I have to modify an existing design (target is SpartanXL), but all Modules generated by LogiBlox fails in Logic-Simulation (Warning 9204 ..block pin for terminal..). As I found out, the generated xxx.ASX-files have all busses expanded, older yyy.ASX-files have busses ! I think, there must be a switch for the LogiBlox-Export-to-Sim to expand busses or not, and my system forgot that ! Can anybody tell me, how to re-configure my system, w/o reinstalling the whole package ? Thx MartinArticle: 95964
Hi Look at xilinx site xapp134 good luck Jerzy GburArticle: 95965
Yaju Nagaonkar wrote: > Ok. It works now. I cleaned up all the solder from the pin connections > and I disconnected a pull-up on the PROG_B pin. The pull up was tied to > 2.5V(VCCAUX) vias 4.7K. > It was a simple mistake which I should have fixed on my own. Basically > I need to learn to solder things neatly. > > I have already looked at the website which earlier JPdull has > mentioned. > I will move on to the other signals, names CCLK and DIN. Again, since > my micro-controller (5v) is driving these signals, I will be using > series resistors (300ohm) to limit the current to these pins. > why not powering the atmel at 3.3V ? speed ? Aurash > > Thanks everyone. >Article: 95966
Hi On a Virtex-II Pro I'm attempting to write a very simple TCP/IP server application running on the PPC. The goal is that when a client connects to the server it will wait until the correct command from the client tells it to send data, so far successful. The problem is that I want the server to send data streaming until the client tells it to stop, and for some reason the client won't send the correct ACK to any data packet but the first one. The acknumber is not updated correctly. I suspect that I am doing something wrong in my server application. I am able to send consecutive data packets if (and only if) every packet is acknowledged by manually sending a packet from the client. The server only accepts one client at the time, and the connection is kept alive until the client disconnects it (Yes, I have added that feature to the TCP state machine of the XilNet library). Does anyone have similar experience with the XilNet lib? Is it possible to send streaming data using it? I will send the source code to anyone interested in giving it a quick look. -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 95967
<eom>Article: 95968
Hi, does anybody know when EDK 8.1 will be ready? I'm also trying to buy the licence of Chipscope 8.1 from Avnet, but I had no answer yet??? Also.... how many people in this newsgoup are happy with the support from Avnet? I'm very unhappy .....:-( Thanks , FrancescoArticle: 95969
Antti Lukats wrote: > the EULA is not NDA, and there is no sign off of an NDA required to obtain > acces to XDL, > at least I am 100% that I have not signed any NDA with Xilinx or any other > FPGA company. Actually it is. One of several specific examples is the restriction on discussing benchmarking.Article: 95970
EDK 8.1 is available from late last week to existing customers by the download mechanism. I expect the CD/DVD version would be long before it is delivered. Chipscope 8.1 has been out for a free weeks. John Adair Enterpoint Ltd. - Home of MINI-CAN. The FPGA Development Board supporting PCI and CAN Bus.. http://www.enterpoint.co.uk "Francesco" <francesco.poderico@trendcomms.com> wrote in message news:1138375263.981246.63390@f14g2000cwb.googlegroups.com... > Hi, > does anybody know when EDK 8.1 will be ready? > I'm also trying to buy the licence of Chipscope 8.1 from Avnet, but I > had no answer yet??? > Also.... how many people in this newsgoup are happy with the support > from Avnet? > I'm very unhappy .....:-( > > Thanks , > Francesco >Article: 95971
fpga_toys@yahoo.com wrote: > Antti Lukats wrote: > > the EULA is not NDA, and there is no sign off of an NDA required to obtain > > acces to XDL, > > at least I am 100% that I have not signed any NDA with Xilinx or any other > > FPGA company. > > Actually it is. One of several specific examples is the restriction on > discussing benchmarking. The NDA embedded in the EULA is actually something of a monster, as it's triggered by Xilinx claiming both trade secret and proprietary interest, and then doesn't grant much, if any rights of disclosure to the user that agrees to the EULA. In every business agreement, you need to sit down and look at each clause, and sort them into rights retained by party U, rights retained by party X, and shared rights. In this case, party X claims pretty broad rights, and grants little, if any, other than just using the software to U. The EULA agreement is THE binding document, what ever you find inside that may say something else, isn't necessarily released from the more restrictive agreement. Before you put your business or home on the line, see counsel.Article: 95972
fpga_t...@yahoo.com wrote: > The EULA agreement is THE binding document, what ever you find inside > that may say something else, isn't necessarily released from the more > restrictive agreement. > > Before you put your business or home on the line, see counsel. One of several examples of this, is that you will find files that claim copyright on the inside. That they claim copyright, does not release them to the domain that say a book at the bookstore would have ... all the information inside the copyrighted documents is still locked by the NDA that is part of the EULA, and the copyright doesn't free them from the NDA. Nothing in the binding NDA that is part of the EULA frees any of the information you may find inside. Only when the same information is found in a legal public source, such as the public sections of Xilinx web site, is that information then free of the NDA in the EULA. Claims to the contrary do not override the EULA NDA. You need a written release which specifically releases you from the EULA NDA terms before you are free to use the information outside the strict terms of normal use of the software. I'm not a lawyer, please see counsel if you are thinking about listening to others advice here from people that are not willing to provide you a written release from Xilinx.Article: 95973
Antonio Pasini wrote: >>The accesses on the xcl bus is only read cachemiss cacheline fills and >>write through address/data. It's not a general bus for doing a fetch of a >>whole matrix. > > > Göran, > > I also have the same need: using multiport OPB sdram controller (better yet, > the mch-ddr-opb, if it works) to connect OPB and two high bandwidth > peripheral (ccd and vga controller). > > Can you give some pointer to relevant docs about XCL protocol ? > Documentation is _very_ scarce on this subject. > > An example with MB for S3/S3E would really jumpstart my design. I would also > pay some support fee for that! > > > > > > There is a small section in MicroBlaze reference guide on the XCL signals. There is also some timing diagrams on how the MCH based memory controller connects and uses the XCL bus. Unfortunately there is no document solely about the XCL bus. To connect the XCL buses is easy in XPS. Just use XPS base system builder for a simple system using MicroBlaze and the mch_opb_sdram controller. Göran BilskiArticle: 95974
Marco T. wrote: > "Göran Bilski" <goran.bilski@xilinx.com> wrote in message > news:drbaoh$nsr4@cliff.xsj.xilinx.com... > >>Marco T. wrote: >> >>>Hallo, >>>I would insert multichannel opb sdram controller into a project. >>> >>>I would use xcl bus to access read/write datas into a integer matrix. >>> >>>I would know if every time I would perform read/write operations into a >>>element of the matrix I need to: >>> >>>1) disable data cache >>>2) init cache with address of matrix element >>>3) enable cache >>> >>>Is it correct? >>> >>>Following that the system copy the region of sdram into bram cache to >>>perform operations on it? >>> >>>Many Thanks >>>Marco >> >>Hi Marco, >> >>If your matrix is stored in the sdram, you don't need to disable the cache >>to read/write the contents of the matrix. >> >>The accesses on the xcl bus is only read cachemiss cacheline fills and >>write through address/data. It's not a general bus for doing a fetch of a >>whole matrix. >> >>Göran Bilski > > > > I have connected to opb some peripheral which have high throughput. > I would use xcl channel to avoid a bottleneck into opb bus. > > So, if I have understood, cache is a transparent bus. > To read or write into cached sdam I don't need "special" functions, only > perform normal operations like a=b, then the system verify if the location > of a is into cached sdram. If yes, the system uses xcl chnnel. > > Is it correct? > > Yes, If caches are enabled and the memory access is to a cacheable region it will happen automatically. Göran Bilski
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