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I had the same issue. The IBUFDS_LVDS_25_DT is shown in the library package but XST doesn't recognize it. I ended up doing what you did. Chuck "Roger" <enquiries@rwconcepts.co.uk> wrote in message news:nLxBf.109663$7p5.53403@newsfe4-win.ntli.net... > Brian, > > Thanks, this was really useful. > > I'm using version 7.1 of ISE and yes, I have the unisim library lines in > the code. > > I used the generic ... IOSTANDARD = LVDS_25_DT on an IBUFDS as you > suggested and it worked! I don't know why and probably never will but it > allows me to progress with the design now. Thanks again. > > Roger. >Article: 95626
I've run into a weird error. I've been successfully calling Modelsim from the ISE gui for the functional sim for weeks. I've finally done a P&R and when I tried to simulate the design ISE generated a testbench.tdo file that has the wrong UUT. It is not the top module in my hierarchy. The modulename_timsim.vhd and sdf files seen correct. I went in and edited the .tdo file to put the correct The modulename_timsim.vhd and sdf files and Modelsim started up and simulated correctly. I tried deleting the .tdo file and regenerating the timesim.vhd file again but to no avail. It just occurred to me as I was writing this that I'll have to look at the hierarchy of the timesim.vhd file it generated. Does anyone know how ISE generates the .tdo file. Where is it getting the wrong top level module from? Thanks CTWArticle: 95627
\quote Do you really mean KHz and not MHz? If this is not a typo I would suggest using a much faster clock to run an FSM that samples the 640KHz clock and uses edge detection (XOR on two stages of flip-flop) to enable data transfer. If you're really talking MHz, modern FPGA's have ways to deal with this at the I/O buffer (double-data-rate flip-flops). Generally multi-edge flip-flops are not synthesizable, but if the part has them, they can be instantiated. i.e. you can't just write: always @ (posedge clk or negedge clk) ... and expect the synthesis tool to generate useful RTL. \quote Now we are using FPGA for verification while at the end this circuit will be implemented by asic tech, so the system clock is fixed at 640Khz. I am not sure whether always @(posedge clk or negedge clk) is synthesizable.Article: 95628
Thanks a lot for replying. \quote There is also a simple circuit that XOR differentiates the clock, thus generating a clock pulse at both the rising and the falling edge. (See, among others, at "Six Easy Pieces" in TechXclusives) \quote I have found the circuit and thanks for information. I am checking the stability of this circuit. If this circuit is reliable, I think this may be a good idea.Article: 95629
Hi all, I need some advice on how to treat the "equivalent gate count" issue. I have to make a presentation on something soon, where FPGAs are the initial foundation of the project, and I anticipate having to provide some correlation between "slices" and "gates" as an estimate to the capacity of current-generation FPGAs. Ideally I would provide a slice and logic area estimate for the specific design, but the design is not nearly complete enough to provide such reliable estimates. For now, I have to arm-wave it. I don't need it to be vendor-neutral though, I can be Xilinx specific. Any suggestions anyone? -intArticle: 95630
On Mon, 23 Jan 2006 09:43:02 +0100, "Frank Schreiber" <frankschr@googlemail.com> wrote:
>Dear all,
>I am using Virtex 4 from Xillinx, and I really missed the clock for LVDS.
>So, should I transfer data to LVDS each time posedge of the clock.
>The clock should be LVDS clock, LTTL clock or any clock is possible.
>Many thanks
>Frank
I don't understand you Frank! Multiple times others have
explained to you that if you don't give sufficient information,
it is IMPOSSIBLE to answer your questions.
Give the following information, and maybe you can be helped:
1) Which exact Xilinx part number are you using.
2) What EXACT device (part number) are you connecting it to
3) How many wires total have you connected between these chips,
(LVDS should be 2 wires per signal, 8 data + clock would total
to 18 wires)
4) Bonus info would be the manufacturer of the board (or if it
is your own design, some more details of the design and the
purpose), the clock rate you are trying to use, whether the
data is single or double data rate.
Philip Freidin
Fliptronics
Article: 95631Mike wrote: > "SioL" <Sio_spam_L@same.net> wrote in message > news:OI7Af.165$76.101141@news.siol.net... >> "Lanarcam" <lanarcam1@yahoo.fr> wrote in message >> news:1137771805.545861.31220@g49g2000cwa.googlegroups.com... >>> >>> Bryan Hackney wrote: >>>> And, um, what has Africa ever contributed to the world? >>> >>> No idea? >> >> Homo Sapiens? >> >> Supposedly the first man or woman came from there. > > My first thought too. > > Thank God they didn't patent. Can you imagine how much the royalty > payments would be? > > (And if we didn't pay, they'd terminate our license to produce!) > > -- Mike -- > > I think that the 20 year time limit ran out a long time ago. -- JosephKKArticle: 95632
"Simon Peacock" <simon$actrix.co.nz> wrote: > > "Lanarcam" <lanarcam1@yahoo.fr> wrote in message > news:1137776981.290724.299580@f14g2000cwb.googlegroups.com... >> >> Bryan Hackney wrote: >> > SioL wrote: >> > > "Lanarcam" <lanarcam1@yahoo.fr> wrote in message > news:1137771805.545861.31220@g49g2000cwa.googlegroups.com... >> > > >> > >>Bryan Hackney wrote: >> > >> >> > >>>And, um, what has Africa ever contributed to the world? >> > >> >> > >>No idea? >> > > >> > > >> > > Homo Sapiens? >> > > >> > > Supposedly the first man or woman came from there. >> > > >> > >> > That's not certain, but we do know where Newton, Galileo >> > and Chebyshev are from. >> >> And you know where the '0' comes from? >> Imagine a memory filled with only '1' ;-) >> > > From India of course :-) same with the numbers we now use :-) > > Simon > > Then why are they called Arabic numerals? -- JosephKKArticle: 95633
Roger wrote: > > Thanks, this was really useful. > Glad that worked. > I'm using version 7.1 of ISE And, now I know what to change when I switch to 7.1 ! I haven't updated from 6.3 yet at home to create a test case, but I've had problems with attributes not sticking to diff. buffers before ( especially the _DIFF_OUT variants ) > > I don't know why and probably never will but it allows me to > progress with the design now. > I think Xilinx is getting away from the named suffixes for the newer families, so perhaps they broke something in the tool flow. BrianArticle: 95634
Paul Burke wrote: > John Larkin wrote: >> >> >> In the sense that capitalism spreads wealth from the richest to the >> poorest parts of the world, it's profoundly liberal. > > It's neither liberal nor conservative. It's a market, it does what > markets do- which is optimise for the market. I could talk about selfish > memes, but only if I thought Mr. Aylward wasn't looking. > > When it is creating employment in areas with an employment problem, good > (in my opinion). When it's transferring employment away from me, bad (in > my opinion). > > Paul Burke Market shmarket, read up on the definition of a market. Fair (including reasonably complete) and equal disclosure of information relating to the contemplated purchase is required. You do not find that very much in America. The correct adjective is Corporatism. Remember how everybody voted on OS properties(?) Nobody wanted their privacy protected, expected the thing to run for more than a few hours, gave a whistle about file system performance or integrity, expected their machine to be doing their bidding instead of another's they just wanted the newest gizmo to work. When M$ tried moving into the server market let alone high availability servers they got several shocking earfulls over this. Unfortunately having to support a terribly badly designed legacy system they cannot fix their problems. -- JosephKKArticle: 95635
John Larkin wrote: > On Fri, 20 Jan 2006 12:13:22 -0500, Spehro Pefhany > <speffSNIP@interlogDOTyou.knowwhat> wrote: > > >>>Any country that admits as many immigrants as we do, will have a high >>>illiteracy rate. Besides, some countries just lie about it. Do you >>>really think Cuba's literacy rate is 99%? >>> >>>John >> >>Ten times the illiteracy of Iceland? It's possible, although the CIA >>only admits to similar literacy levels to the US (97%), which is far >>worse than what they say about France and Germany (99%). They also say >>99.8% for Poland and 99% for the UK. Cuba has sunk a lot of resources >>into literacy since the sixties, and have exported their training >>methods to greatly improve literacy in some of the poorer Mexican >>states. >> >> > > I don't think a 99% literacy rate is neurologically possible, much > less 99.9. > > John > > I suspect that 99% is about the limit, assuming something similar to the "normal" distribution for ability (as if it could be measured in a single number). Numbers above that should be questioned and 99.8% should be an indicator of serious infanticide rates. -- JosephKKArticle: 95636
Spehro Pefhany wrote: > On Fri, 20 Jan 2006 17:10:55 -0800, the renowned John Larkin > <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >> >>That's nothing. My computer screen, and all the programs I run, are >>covered with little picture buttons. You don't have to be literate to >>operate a word processor program! >> >>John > > More's the pity. Remember when "Desktop Publishing" was introduced? It > took a while for all the templates and so on to be introduced so that > people were not shooting themselves in the foot with the new tools. > > > > Best regards, > Spehro Pefhany Sure as hell do. It was one of the nice coup's scored by the Apple Corp. Mac's. Damn, was that really 25 years ago? -- JosephKKArticle: 95637
"Simon Peacock" <simon$actrix.co.nz> wrote: > > "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in > message news:3p12t1tq1vqg98k7uf8o53e709irleahj6@4ax.com... >> On 20 Jan 2006 05:44:00 -0800, "Noway2" <no_spam_me2@hotmail.com> >> wrote: >> >> >> The current US administration seems to be >> >> obsessed with investing in military adventures, while places like >> >> India > have >> >> decided to invest in educating their people - which investment do you > think >> >> will pay off better in 20 years? It's all a matter of priorities. >> > >> >It is no secrete that the US, both the mass populace and the government >> >administrations put far too little emphasis on education and this is >> >causing a declining society. >> >> How is US society declining? Incomes, health, longevity, education >> levels have been increasing steadily for 200 years, even while we have >> admitted tens of millions of immigrants. >> >> >There is no way that as a society that >> >the people will be able to compete with anybody when they have the >> >highest illiteracy rate of the industrialized world. >> >> Any country that admits as many immigrants as we do, will have a high >> illiteracy rate. Besides, some countries just lie about it. Do you >> really think Cuba's literacy rate is 99%? >> >> John >> > One of the problems is the level of literacy.. can you read a university > level book or Doctor Sues.. both are levels of literacy (if at the > extreme) > > Simon > > Interesting issue, a portion us here can even write at the university level. -- JosephKKArticle: 95638
Unless you compare two related FPGA devices, gate count will be rather meaningless, since it is interpreted differently by the ASICand FPGA communities. I would elaborate on: Flip-flop count, I/O count (including required standards including bidirectional LVDS,) gigabit serial I/O. on-chip memory (width and depth), multipliers/accumulators, potential need for an on-chip microcontroller. Those six items should quantify almost any design. Peter Alfke, XilinxArticle: 95639
Roberto Waltman wrote: > Joerg wrote: >>So, a university degree is worthless and only some bureaucrats get to >>decide who will have a job and who doesn't? IMHO, if someone has a >>degree from a university that shall be enough of a qualification. What >>difference would some license make? > > I do not know if licensing/certification is > the answer, but I wish there was a way to weed > out the type of "professionals" that seem to > be appearing more and more often in the > newsgroups I frequent, with posts along the > lines of: > > Hi group!! I'm a surgeon and will > be performing open chest surgery > on one of my patients tomorrow. > I have a few questions: > What is an hemorrhage, when do > you use it? > What is a suture? > What is coagulation, > What is an antibiotic? > What is anesthesia, do you implant > it before or after the coagulation? > Where exactly is the heart? > Can you help me? Please email > the answer directly to the > operating room. > > Yes, I am exaggerating. > No, I am not exaggerating a lot. > > Roberto Waltman > > [ Please reply to the group, ] > [ return address is invalid. ] I have actually met MD's, here in America, that scared me that badly. I say has had already visited then twice the first time, it was also my last time. -- JosephKKArticle: 95640
The circuit is reliable, although the generated pulse width is determined by gate delays. But it is self-compensating, since the clock pulse will not end until the flip-flop has toggled. It's kind of clever, if I am allowed to say so... Peter AlfkeArticle: 95641
The circuit is reliable, although the generated pulse width is determined by gate delays. But it is self-compensating, since the clock pulse will not end until the flip-flop has toggled. It's kind of clever, if I am allowed to say so... Peter AlfkeArticle: 95642
Joerg wrote: > Hello Richard, > >> >> So just what does "a degree from a university" really mean? >> >> Yesterday I heard a news report that questioned whether or not average >> US college graduates were even literate -- their test criterion was >> related to reading product labels/instructions [I was driving at time so >> I was paying attention to other things ;] >> > > I don't know how it is today but in my days a masters degree meant that > you were very literate and had a rock solid knowledge base all the way > to Maxwell's equations. Else you would not hold that degree. IIRC only > about 17% of the year when I started made it. They had the "three > strikes rule". If you flunked an exam you could repeat once. Only one > exam could be attempted a third time and you had to request special > permission for that. Fail it again and you were out for good. Oh, and > that repeat exam came with the "exitement" of an aural where you were > grilled by the professor for a half hour or so. And no Xanax or Zoloft > or whatever in those days. > > That's very different from some multiple choice tests that ask you how > many appointees there are on a licensing board. > >> >> As to PE license, it's irrelevant to reality if not legality. >> I don't know how it is now. > > > Still is, in most states, due to the industry exemption. Take that away > and that state will slide down into the technological abyss. > > I have also had the "pleasure" to share your experiences WRT to young > grads. Universities still do not teach much practical engineering and > the kids today are not creative anymore in the ways we were. The demise > of Heathkit and those cool electronics surplus stores in town is an > indicator of that. Licensing is not going to make that situation any > better. Not by one iota. It would make it worse by taking older > engineers with real experience but non-ABET course work out of the work > force. Engineers who would then probably sue those agencies into oblivion. > > Regards, Joerg > > http://www.analogconsultants.com Well yes and no. Like most of the best of this group i was doing electronics by time is was 10, building kits and all that. By the time i was 12 i could successfully calculate bias for a single transistor amplifier. I mostly learned this from library books (college level at the time, 1960's) impressed the hell out of my father (BSEE about 1950). He didn't tell me for about thirty years. By the time i was 14 i designed a RIAA magnetic coil phonograph, standard tuner (1 volt in 10 kOhm (tube standard)) and line level auxiliary input, with tape deck loop through, stereo preamplifier with "Headphone" output capable of 1W into 8 Ohms, mostly based (surplus) on uA741 op-amps with three band Baxandal tone controls. After no more than three tries it met specifications. Not too bad for a 14 year old kid. -- JosephKKArticle: 95643
Peter Alfke wrote: > The circuit is reliable, although the generated pulse width is > determined by gate delays. But it is self-compensating, since the clock > pulse will not end until the flip-flop has toggled. It probably needs some care, to ensure CLK_min times are ok ? eg if you drive a large clock tree, it would be better to not use a local FF clk, and then buffer, but to buffer, and then FF.CLK from the CLK tree output, with optional additional delays, if you want even more margin. > It's kind of clever, if I am allowed to say so... Yes, I recall a similar [XOR-Q] clock scheme many, many years ago, on a circuit ( from HP?) for Biphase decode. -jgArticle: 95644
Hi,
I designed a simple adder using the add/import peripheral feature in
EDK. I removed the sum register in the write process, and add a
my_adder process to calculate the sum. Every time I run the test (a
sample software application), I get a 0 as the sum. I got both reg0 and
reg1 correct, but not the sum. Anyone has an idea what I've done wrong?
I can't figure if it's the code issue, or I am supposed to change some
setting in EDK. Thanks.
part of my application code:
MY_ADDER_mWriteReg(XPAR_MY_ADDER_0_BASEADDR, 0, 10);
MY_ADDER_mWriteReg(XPAR_MY_ADDER_0_BASEADDR, 0x4, 7);
a = MY_ADDER_mReadReg(XPAR_MY_ADDER_0_BASEADDR, 0);
b = MY_ADDER_mReadReg(XPAR_MY_ADDER_0_BASEADDR, 0x4);
for(i=0; i<100000; i++)
;
sum = MY_ADDER_mReadReg(XPAR_MY_ADDER_0_BASEADDR, 0x8);
VHDL CODE:
--USER logic implementation added here
MY_ADDER: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg2 <= (others => '0');
else
slv_reg2 <= slv_reg0 + slv_reg1;
end if;
end if;
end process MY_ADDER;
-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
else
case slv_reg_write_select is
when "100" => slv_reg0 <= Bus2IP_Data(0 to 31);
when "010" => slv_reg1 <= Bus2IP_Data(0 to 31);
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0,
slv_reg1, slv_reg2 ) is
begin
case slv_reg_read_select is
when "100" => slv_ip2bus_data <= slv_reg0;
when "010" => slv_ip2bus_data <= slv_reg1;
when "001" => slv_ip2bus_data <= slv_reg2;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
Article: 95645I changed the front end core given by amirix for dma functionality. For a dma transfer what is the destination address that I should specify? How can I get this address. I am sending data from the card to the host memory. NiteshArticle: 95646
Hi All, Iam new to xilinx platfrom. I was trying to port open source linux on Ml403 board. i tried to follow the instructions in the below link. http://www.klingauf.de/v2p/index.phtml i was getting errors when i was running bZimage. the .elf file was not getting created. Is there an alternative way of acheiving my goal. Kindly suggest. Thanks in advance. RameshArticle: 95647
On 24 Jan 2006 22:01:42 -0800, "Eric" <dasani8888@hotmail.com> wrote:
>Hi,
>
>I designed a simple adder using the add/import peripheral feature in
>EDK. I removed the sum register in the write process, and add a
>my_adder process to calculate the sum. Every time I run the test (a
>sample software application), I get a 0 as the sum. I got both reg0 and
>reg1 correct, but not the sum. Anyone has an idea what I've done wrong?
>I can't figure if it's the code issue, or I am supposed to change some
>setting in EDK. Thanks.
>
>part of my application code:
>
> MY_ADDER_mWriteReg(XPAR_MY_ADDER_0_BASEADDR, 0, 10);
> MY_ADDER_mWriteReg(XPAR_MY_ADDER_0_BASEADDR, 0x4, 7);
>
> a = MY_ADDER_mReadReg(XPAR_MY_ADDER_0_BASEADDR, 0);
> b = MY_ADDER_mReadReg(XPAR_MY_ADDER_0_BASEADDR, 0x4);
> for(i=0; i<100000; i++)
> ;
> sum = MY_ADDER_mReadReg(XPAR_MY_ADDER_0_BASEADDR, 0x8);
>
>
>VHDL CODE:
>
> --USER logic implementation added here
> MY_ADDER: process (Bus2IP_Clk) is
> begin
> if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
> if Bus2IP_Reset = '1' then
> slv_reg2 <= (others => '0');
> else
> slv_reg2 <= slv_reg0 + slv_reg1;
> end if;
> end if;
> end process MY_ADDER;
>
> -- implement slave model register(s)
> SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
> begin
>
> if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
> if Bus2IP_Reset = '1' then
> slv_reg0 <= (others => '0');
> slv_reg1 <= (others => '0');
> else
> case slv_reg_write_select is
> when "100" => slv_reg0 <= Bus2IP_Data(0 to 31);
> when "010" => slv_reg1 <= Bus2IP_Data(0 to 31);
> when others => null;
> end case;
> end if;
> end if;
>
> end process SLAVE_REG_WRITE_PROC;
>
> -- implement slave model register read mux
> SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0,
>slv_reg1, slv_reg2 ) is
> begin
>
> case slv_reg_read_select is
> when "100" => slv_ip2bus_data <= slv_reg0;
> when "010" => slv_ip2bus_data <= slv_reg1;
> when "001" => slv_ip2bus_data <= slv_reg2;
> when others => slv_ip2bus_data <= (others => '0');
> end case;
>
> end process SLAVE_REG_READ_PROC;
I would test if address 0x8 triggers slv_reg_read_select<="001", I
think there may be the error.
BTW, if you want to type less and be more clear, substitute all your
if clock'event and clock='1' then
with
if rising_edge(clock) then
Regards,
Zara
Article: 95648Hi, an ARM is a processor with its hardware structure yet defined and ready to be programmed (C/C++/assembly), while an FPGA is a chip with no structure defined. What you need to do with the latter is to write HDL code (VHDL or Verilog languages) that describes the hardware structure of your FPGA (programmable logic). In this way you can implement exactly what you're looking for, an optimized chip for your task, and, if you may need, you could also put an ARM architecture inside your logic. MarcoArticle: 95649
david wrote:
> I am usig xilkernel on microblaze spartan 3 board. I am getting an unusual
> error that is
>
> undefined reference to `xilkernel_main'
>
> when i write the code below
>
> int main (void) {
> print("-- Entering main() --\r\n");
> xilkernel_main();
> print("-- Exiting main() --\r\n");
> return 0;
> }
>
> Any idea what is wrong. I did configure input and output port (as RS232),
> i am using timer1 as the sytem timer for xilkernel. I have statically
> linked only two task using "software Platform Setting" in
> 'static_pthread_table' entry. There is no resource on this subject on
> xilinx website. Please help.
>
> David
>
>
Hello David,
I just ran into the same error the other day, and the reason I got the
error was that the parameter MYAPP_LFLAGS in the file myapp_compiler.opt
(in the __xps directory) wasn't set properly. It should be set to
-lxilkernel in order to include the kernel when linking the code. (The
same parameter should be set in the same way in the system_incl.make file)
Btw, I have had problems working with the Xilkernel in the XPS GUI. Not
until I edited the make- and opt- and mss-files manually and compiled
the applications in cygwin I was able to build the project properly.
Hopefully this is fixed in EDK 8.1...
--
-----------------------------------------------
Johan Bernspång, xjohbex@xfoix.se
Research engineer
Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems
www.foi.se
Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------
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