Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
You should check out the following: http://www.fpgaarcade.com/ I've downloaded a few files from there but haven't really done much with them yet. CTW "outsideedge" <sean_yzfr1@yahoo.co.uk> wrote in message news:1114382538.354225.4840@f14g2000cwb.googlegroups.com... > Hi guys, hope you can help! > I'm trying to create Space Invaders using video ROMs. I'm creating a > hardware schematic to be used on the XESS XS40 development board that > contains an embedded 8031 microcontroller and a Xilinx 4010 series > deivce. Im downloading it onto that board and running it using a C > program. If anyone can provide any tips/hints or web resources on > schmatic design or operation it will be greatly appreicated. > > Regards >Article: 83201
I have a few questions in the design of a connection from Xilinx Virtex-4 to DDR SDRAM 200-pin SO-DIMM module First is if pull-up (to Vtt) termination of clock lines (on the module end) is needed. These clocks are SSTL differential signals in pair and many datasheets show the cross 120 ohm termination on the module. It means they do not need Rt 50-ohm to Vtt termination as other SSTL signals (data, address and control) do. but I can not find explicit description or statement on this. Can anybody confirm it? Second question is how to configure the pins on Virtex-4. They are all SSTL2-II or DIFF_SSTL2_II. Do I need to set DCI? I am not sure. I tried Xilinx mig1.21. It gave me straight SSTL2-II/DIFF_SSTL2_II without DCI. Do I need Rt 50-ohm to Vtt termination near those FPGA pins? Thanks for your help in advance.Article: 83202
hey,
thanks..I think the displaly problem got solved..although now I'm
nervous since I didn't use a complicated algorithm and since I'm
using the bits 9 downto 2 (positive numbers only and are straight
binary) then I have a process that converts them to bcd..then to the
7 segment display. Now I'm working on simulating the ad7814..which
seemed pretty easy. but for the life of me I can't get it to
work..I'm just using a simple process (which you had mentioned
earlier also) to generate the timing diagram..this is what I'm doing
( obviously it's wrong ) before I interface it to the fpga. I ahve
to have the chip with FPGA working by wed :( Talk about
procrastinating..it seemed simple before I started working on it!!
:(
entity model7814 is
port(
CS: in std_logic:='Z';
SCLK: in std_logic :='0';
Dout: out std_logic
);
end model7814;
architecture Behavioral of model7814 is
CONSTANT N: integer :=16;
begin
process (CS,SCLK)
begin
if SCLK' event and SCLK= '0' then
if CS<='0' then
FOR K IN 0 to N loop
if K=0 then
Dout <= '0';
else
Dout<='1';
end if;
end loop;
else
Dout<='Z';
end if;
end if;
end process;
Article: 83203"Eric Smith" <eric@brouhaha.com> wrote in message news:qhhdhufwsb.fsf@ruckus.brouhaha.com... > Ziggy wrote: >> The S3 board does have a 1M option now, you see it in the shopping cart. > > Alex Gibson wrote: >> Says quarter 3 2005 >> >> Spartan3e starter kit >> http://www.xilinx.com/products/spartan3e/s3eboards.htm for US$149 >> ethernet , usb , 32MB sdram, XC3S500E-4FG320 >> maybe with an upgrade option ? > > Ziggy was talking about the S3 board, not the S3E board. The S3 > board is available from Digilent with the XC3S400 or XC3S1000 > in place of the usual XC3S200. I know that > It does not have Ethernet, USB, or SDRAM, though. It does have > static RAM. I have a S3 starter kit. The s3e looks quite good with the extra features saves buying the separate add-on modules. Better for those using soft cores The usb config is handy except some antivirus software interferes with Digilents adept software, only seems to happen on my laptop not desktop. Just another option for those who can't get the academic pricing on the v2pro board. S3e starter kit has showed up in the xilinx online store with a note saying target availability in July <http://www.xilinx.com/xlnx/xebiz/productview.jsp?sGlobalNavPick=PURCHASE&sSecondaryNavPick=Services&category=-1211456&iLanguageID=1&category=/Xilinx+Products/Design+Resources/Design+Starter+Kits/Spartan+3E+Starter+Kit> AlexArticle: 83204
"Alex Gibson" <news@alxx.net> wrote in message news:3d4m9vF6pquk4U1@individual.net... > > > Says quarter 3 2005 > > Spartan3e starter kit > http://www.xilinx.com/products/spartan3e/s3eboards.htm for US$149 > ethernet , usb , 32MB sdram, XC3S500E-4FG320 > maybe with an upgrade option ? > > Alex > > > Cool! Does it mean with this board, one can study firmware design with USB port and interface with a PC without extra hardware? USB has always been something I want to study. "Purchase the Spartan-3E FPGA Starter Kit and receive a complimentary CD Kit containing the evaluation version of EDK 6.3i. The EDK kit includes the Platform Studio tool suite, the MicroBlaze soft processor core license, as well as all the embedded IP and documentation that you need to start designing Spartan-3 embedded processing systems today. " Does the MB core license and other embedded IP have a time limit or not? BTW, what does the extension -E mean? I was aware all FPGAs in Xilinx have an E version.Article: 83205
I see, I will look into that "Print" option. As long as it is in text format, CF/LF characters are a minor issue. Can I still compress within 16702 before I copy that in floppy disk? Thank you. "Avrum" <avrum@REMOVEsympatico.ca> wrote in message news:BLbae.10164$9G.728358@news20.bellglobal.com... > If I remember, the way to do this is to "print" the results. Instead of > selecting a printer, save it to a file instead. This will "print" a text > file containing the data. I think the resulting file is more or less human > and machine readable - the data is all in proper columns, however, I think > it puts page headers every 70 or so lines - if you want to process the file > (say, with awk or perl), then you will have to make sure the program can > recognize the header lines as well as the blank lines. > > Also, there may be a problem with the carriage return/line feed sequences in > the file - the 16702 uses PC style CR/LF sequences - if you are working in > UNIX, then you will have to have a sed (or vi) script remove the extra > control character. > > Avrum > > "Acceed See" <invalicd@hotmail.com> wrote in message > news:4264c256$1@news.starhub.net.sg... > > I gather some file from this machine, but I was only able to save it in > > binary format. What I need is in plain text so that I can correlate with > > my simulator. Anyone can give a pointer? > > > > > > > > > >Article: 83206
In article <ReUae.17355$NU4.6274@attbi_s22>, Ziggy <Ziggy@TheCentre.com> wrote: >A new product from Digiliant... > >All i can say is oooo! > > > > * Virtex-2 Pro XC2VP30 FPGA with 30,816 Logic Cells, 136 18-bit >multipliers, 2,448Kb of block RAM, and two PowerPC Processors > * DDR SDRAM DIMM that can accept up to 2Gbytes of RAM > * 10/100 Ethernet port > * USB2 port > * Compact Flash card slot > * XSGA Video port > * Audio Codec > * SATA, and PS/2, RS-232 ports > * High and Low Speed expansion connectors with a large collection >of available expansion boards > > >http://www.digilentinc.com/info/XUPV2P.cfm > >300$ student price.... Now if i can convince them to give that price out >to us lowly hobbiests too... Very nice. But can it be used with the Webpack? If you have to buy the full ISE Foundation for it that would sort of negate the cost savings... Actually, why wouldn't webpack work? Does it not support the Virtex II parts? PhilArticle: 83207
outsideedge wrote: > Hi guys, hope you can help! I'm trying to create Space Invaders using > video ROMs. I'm creating a hardware schematic to be used on the XESS > XS40 development board that contains an embedded 8031 microcontroller > and a Xilinx 4010 series deivce. Im downloading it onto that board > and running it using a C program. If anyone can provide any > tips/hints or web resources on schmatic design or operation it will > be greatly appreicated. I'm not clear on what you mean!?! By 'create Space Invaders" do you mean that you're writing your own version of the game? And what do you mean by 'video ROMs'? Considering the original Space Invaders runs on an 8080 I'm assuming you're not attempting to emulate the original?!? As for hints/tips - I can tell you the original used a bitmapped display. Patterns for invaders/characters were stored in program ROM and drawn to the bitmapped display by program code. There was also a hardware shifter, mapped to a few I/O ports on the 8080, that the game used to generate bitmaps of characters shifted by <n> pixels. Regards, Regards, MarkArticle: 83208
I am not able to install the linux x86 version on cygwin. its giving
the error "./vhdlarch: 1: Syntax error: "(" unexpected" when I run
vhdlarch -help after gunzip.
Article: 83209rgebru wrote: > I started using the Analog devices AD7814 and I'm having trouble > understanding how to interface it to the Spartan 3 board. :( Does > anyone have any suggestions to get me started? I could REALLY use the > help!! Thanks!! > 1. Why don't you try and understand the code I sent ? It does (I think) all you want to do plus a little extra. It does respect the design rules (it's fully synchronous) It does employ good coding techniques. 2. Read and re-read (and adopt) : http://www.alse-fr.com/archive/VHDL_Coding_eng.pdf Your "simple" process is a collection of things "no to do". Wrong domain, wrong sensitivity list, wrong tristate inference ( via clocked process !).... If you do not start with the basics, you'll find hardware design disgustingly frustrating and a total loss of time. My opinion. Bert CuzeauArticle: 83210
Hi Marc, the SystemACE CF is not so bad, when it works, but trouble is easy to come :( http://wiki.openchip.org/index.php/SystemACE the different file size may be ok, as the .ACE contains the .BIT and possible .ELF files so the .BIT are some SVF are merged to create the mysterios secret .ACE file format. check that the FPGA startup clock is JTAG and that the JTAG chain configuratian is ok. hmm.. with some V4 boards I think there are special workarounds to "fix" the ACE files check the stuff that did come with the board if there are some batch files or special instructions. On our V4 board (V4LX25 from Memec) the SystemACE did never works and the board designer suggested that we return the board. I think the problem was related to V4LX25 ES JTAG errata. but all ML40x boards work from systemACE so thats not your issue. as of supplying the board without cable thats actually perfectly fine: we have here at least 6 cables (3 different types) that coud be used with ML40x boards, so shipping the board without cable is ok. if xilinx is out of stock with Cable IV then www.amontec.com the reconfigurable dongle can be programmed to be Cable III and it includes the 14 pin header and cable so you can use it with ML402 just ask that you need the xilinx adapter and cable when ordering I am sure amontec can ship immediatly antti PS the trouble with cables and systemACE (or similar solutions) is why http://www.hydraxc.com includes special processor that can configure from normal filesystem using standard xilinx .BIT files, just copy the .Bit to the mini SD card and insert the card. No cables. No conversion to some mysterious format. Verbose error reporting in case of configuration failures. Fail safe remote updates (by restoring last known configuration if new update doesnt work). "Marc Reinig" <Marco@newsgroups.nospam> schrieb im Newsbeitrag news:426d60e6$1@darkstar... > I have a 402 Virtex 4 board from Xilinx. I don't have one of the special > cables required to load it so I am trying to use the System Ace method and > adding my configuration as MyAce. I'll withhold my comments on why they > require a special cable but don't supply it with the board. > > I seem to be able to generate a MyAce.ace file ok, but it is 1,674 KB long > and I get an error when I select it. I notice that all the other working > .ace files are 1,686 KB long, so I assume I am doing something wrong. Any > idea what or any recommendations? I wanted to order a cable kit but they > were out of stock. Any other sources? > > Thanks in advance, > > Marco > ________________________ > Marc Reinig > UCO/Lick Observatory > Laboratory for Adaptive Optics > >Article: 83211
Hi Austin, what about the FX series? When are FX60 - FX140 going to ship? Regards, Simon Austin Lesea wrote: > Simon, > > > The Virtex-4 LX25, LX60, LX100, LX200, SX25, SX35, SX55, and FX12 FPGAs > are shipping today. Xilinx now has a total of 20 FPGAs shipping at 90nm > -- three times as many 90nm FPGAs as its nearest competitor. > > All there, all ready for you, > > AustinArticle: 83212
Has any one tried running 7.1 for linux on OS X or darwin or freebsd ? Even just commandline tools ? Trying to avoid having yet another computer(or dual boot) AlexArticle: 83213
"Phil Tomson" <ptkwt@aracnet.com> wrote in message news:d4kf7e08hg@enews2.newsguy.com... > > In article <ReUae.17355$NU4.6274@attbi_s22>, > Ziggy <Ziggy@TheCentre.com> wrote: >>A new product from Digiliant... >> >>All i can say is oooo! >> >> >> >> * Virtex-2 Pro XC2VP30 FPGA with 30,816 Logic Cells, 136 18-bit >>multipliers, 2,448Kb of block RAM, and two PowerPC Processors >> * DDR SDRAM DIMM that can accept up to 2Gbytes of RAM >> * 10/100 Ethernet port >> * USB2 port >> * Compact Flash card slot >> * XSGA Video port >> * Audio Codec >> * SATA, and PS/2, RS-232 ports >> * High and Low Speed expansion connectors with a large collection >>of available expansion boards >> >> >>http://www.digilentinc.com/info/XUPV2P.cfm >> >>300$ student price.... Now if i can convince them to give that price out >>to us lowly hobbiests too... > > > Very nice. But can it be used with the Webpack? If you have to buy the > full ISE Foundation for it that would sort of negate the cost savings... > > Actually, why wouldn't webpack work? Does it not support the Virtex II > parts? > > Phil No. From http://www.xilinx.com/xlnx/xebiz/designResources/contentContainer.jsp?key=webpack_faq ISE WebPACK supports the devices in the table below: FPGA Virtex™ Series Virtex-E: XCV50E - XCV300E Virtex-II: XC2V40 - XC2V250 Virtex-II Pro: XC2VP2 Virtex-4: LX: XC4VLX15, XC4VLX25 Spartan™ Series Spartan-II: ALL Spartan-IIE: XC2S50E - XC2S300E Spartan-3: XC3S50 - XC3S1500 Spartan-3E: XC3S100E - XC3S500E Spartan-3L: XC3S1000L, XC3S1500L CPLD CoolRunner-II CoolRunner-IIA CoolRunner XPLA3 All XC9500 / XL / XV Families All so unfortunately need ISE Foundation. Fine if you are at a uni as the uni can request that via Xilinx university program same with system generator and edk (and S3 starter kits) AlexArticle: 83214
Hi, what does have more advantages when trying to synchronize an incoming external datastream: 1. Synchronize the data bus with some (two or three) register stages and feed the sychronized data into a FIFO which is an additional synchronization stage (write clock of FIFO has a different frequency than the read clock) OR 2. Feed the data bus directly into the FIFO and synchronize the data coming out of the FIFO into some (two or three) register stages ? I am very thankful for any comments. Rgds AndréArticle: 83215
According to byteblaster/INSTALL (in linux/byteblaster.tar.gz):
" If you are using Quartus II 4.0 or later then you do not need a
kernel driver - Quartus will use the parport driver which is part of
the 2.4.x and 2.6.x series kernels."
I'm running QuartusII 4.2SP1 under RHEL-3 (2.6.x) . The permissions
seems fine:
ls -l /dev/parport0
crwxrwxrwx 1 root lp 99, 0 Sep 7 2004 /dev/parport0
I have a ByteBlasterII connected to the parport on the machine, but
when I do:
quartus_pgm --list
Info:
*******************************************************************
Info: Running Quartus II Programmer
Info: Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Full
Version
...
Info: Processing started: Tue Apr 26 10:54:37 2005
Info: Command: quartus_pgm --list
No JTAG hardware available
Info: Quartus II Programmer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Apr 26 10:54:37 2005
Info: Elapsed time: 00:00:00
Any clues?
Peter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Article: 83216"Simon Peacock" <nowhere@to.be.found> wrote in message news:<426b0f22@news2.actrix.gen.nz>... > I would suggest a dual processor with lots of dual port ram and 64 bit at > least. That way when the processor is busy place and routeing, you can be > doing the documentation in Word. > > So far I think the jury is out as to 32 / 64 bit code .. but I think 32 bit > is slightly faster until processors speed up It seems you speak about non-x86 MPUs. For AMD64/EM64T MPUs this is not the case. 32 bit code runs in 64 bit mode (OS) as fast as in 32 bit mode and recompiled code with a lot of calculations runs even faster in most cases with a good compiler (thanks to more registers etc.). > > Simon MatthiasArticle: 83217
Hi All I have read that the PLB bus can have a 1:1 ratio to the processor bus frequency. And when I was giving my initial design in the wizard, where I gave 300MHz for my PowerPC, (thats the maximum it shows !!), the maximum bus frequency it displayed is only 100MHz. What could be the reason. Does it mean that this 1:1 bus ratios between the PowerPC and the PLB is not always possible? I am using a Virtex2Pro board. 2VP7-FF672 with speed grade -6. !! Regards, JoeyArticle: 83218
Hello all, Can someone please answer the following questions? 1. I am using a VGA graphics core with 60Hz refresh rate and 640x480 pixels (24bit), requiring about 25MHz xtal. The FPGA development board comes equipped with that, the problem is how to provide a fast pixel access. The SDRAM connected has an access time of 15ns, if I could just come up with some method to update the SRAM contents very quickly, i can display moving graphics onto the monitor using FPGA? Are there any simple graphic chips which can do this job for custom display designs without using the processors? 2. The second question indirectly relates to the PCI, however, before that, can someone please tell me exactly how plug and play works? When the computer boots what steps are taken and how the system determine how many legal devices are connected to the pci. 3. The base address register, it is not hardwired but assigned on the fly? I have problems understanding the configuration step in the pci core. Any comments for a starter? Thanks in advance MakArticle: 83219
Hi all! I have a problem that someone here might have the answer to. I have a divider that takes inputs of 13 and 12 bits, and produces an output of 12 bits. I have a component to strip away the redundant bits from the divider, if the result of the division is, say an int value of 6, I don't want to use all 12 bits. This circuit is a part of an MPEG-4 device, a quantizer, so I want to compress as much as possible. My question is then, how do I declare the ports on the component that strips away the bits to output an std_logic_vector that is not fixed in size, but dynamic? This must be synthesizable. Guess there are many ways of doing this, and I hope someone has got an answer to me. Thanks, Dan NilsenArticle: 83220
"Duane Clark" <dclark@junkmail.com> wrote in message news:Oovae.5482$J12.3021@newssvr14.news.prodigy.com... > Unless later boards have corrected the design, there is a design error on > the Avnet boards. It turns out the when using DDR signals, the pins on the > Virtex2p are arranged in pairs that must share a common clock. On DDR > DIMMs, the DQS signals are special and require a different clock from the > other DIMM signals. However Avnet shared these pairs between the DQS and > DM signals. For example, they put DDR_DM0 on pin R22 and DDR_DQS0 on pin > P22. > > If you look at the Xilinx docs, these pins are named IO_L56P_7 and > IO_L56N_7. Notice that they have the same L number, and differ only in the > N/P designation. This indicates that these pins are a pair that must share > the same DDR clock. > > The solution that I used for this problem was to recognise that in my > application, the mask (DM) bits would never change during a data transfer. > So I let DM use the same clock as DQS, and setup the DM signals slightly > early and hold them slightly longer than needed. The Avnet ADS-XLX-V2-DEV4000 has the same design error: ERROR:Place:17 - The current designer locked placement of the IOBs ddr_dqs<7> and ddr_dm<7> makes this design unroutable due to a physical routing limitation. This device has a shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction means that these pairs of pins must be driven by the same signal or one of the signals will be unroutable. Before continuing with this design please unlock or move one of these IOBS to a new location. ...when trying to use the plb_ddr core with the board. The board documentation says to use the old XAPP200 DDR core which does not use the DQS signals in the same way, so I guess that might work too for the V2Pro. Thanks for the tip about the DM mask bits to get plb_ddr to work! Regards, HansArticle: 83221
Hi Jason, "jason.stubbs" wrote: > Austin, > > The online tool also requires details of the design that I dont have. > Can you guide me in what I have to enter to estimate the worse case? In terms of "PVT" - Process, Voltage & Temperature : In the WPT currently you can, for V4 FX devices, vary Vccint and the ambient temperature. That partially addresses the "V" & "T". On the "P" or process side here are a few guidelines : - if you are at worst case process and worst case voltage (1.3 V) you should use a factor of 2.5. - if you are at worst case process but at nominal voltage you should use a 2.0 factor. Brendan > > > Thanks > > JasonArticle: 83222
But you mentioned the two magic words ... Good and Compiler. :-) But I don't know for a fact if its faster or slower.. just initial comments ... the main difference seems to be clock speed.. and the 32 bit CPU's are currently faster ... "Dresdenboy" <Alpharomeo2k@gmx.de> wrote in message news:5fd302c8.0504260105.5c48d17d@posting.google.com... > "Simon Peacock" <nowhere@to.be.found> wrote in message news:<426b0f22@news2.actrix.gen.nz>... > > I would suggest a dual processor with lots of dual port ram and 64 bit at > > least. That way when the processor is busy place and routeing, you can be > > doing the documentation in Word. > > > > So far I think the jury is out as to 32 / 64 bit code .. but I think 32 bit > > is slightly faster until processors speed up > > It seems you speak about non-x86 MPUs. For AMD64/EM64T MPUs this is > not the case. 32 bit code runs in 64 bit mode (OS) as fast as in 32 > bit mode and recompiled code with a lot of calculations runs even > faster in most cases with a good compiler (thanks to more registers > etc.). > > > > > Simon > > MatthiasArticle: 83223
Hi, This board: http://www.altera.com/corporate/cust_successes/customer_showcase/csh-seventech_lp.html has similar characteristics, besides is available a Software Dev Kit to immediately develop your program in C++. My company, buy this board to develop gambling machine. Our company doesn't have an inside structure to develop hardware, but only software. Before we developed our software on PC platform. But the PC platform it's not good for an embedded use. Now with this board we succeed in realizing excellent products. On the web page of Seventech, you can also see a sample C++ code to realize a graphic animation with this board. With this board it is possible to realize graphic animations with very good performance and the cost, also for the companies, it is <300$, for an only piece. Paolo "Ziggy" <Ziggy@TheCentre.com> ha scritto nel messaggio news:ReUae.17355$NU4.6274@attbi_s22... >A new product from Digiliant... > > All i can say is oooo! > > > > * Virtex-2 Pro XC2VP30 FPGA with 30,816 Logic Cells, 136 18-bit > multipliers, 2,448Kb of block RAM, and two PowerPC Processors > * DDR SDRAM DIMM that can accept up to 2Gbytes of RAM > * 10/100 Ethernet port > * USB2 port > * Compact Flash card slot > * XSGA Video port > * Audio Codec > * SATA, and PS/2, RS-232 ports > * High and Low Speed expansion connectors with a large collection of > available expansion boards > > > http://www.digilentinc.com/info/XUPV2P.cfm > > 300$ student price.... Now if i can convince them to give that price out > to us lowly hobbiests too...Article: 83224
On Fri, 22 Apr 2005 18:48:29 +0200, Marco wrote: > I need to buy a new PC. What is the best processor for saving time during > synthesis projects? > > AMD Athlon 64 > Intel XEON > Intel Pentium 4 > > ?? > > Thanks > Marco An A64 with a 1M cache. The cache size is more important then clock speed and memory bandwidth. I did some benchmarking of common FPGA development task like simulation and Xilinx builds, http://www.polybus.com/linux_hardware/index.htm
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z