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On Wed, 27 Apr 2005 17:18:03 -0700, kevin wrote: > "Hope this helps." > > It absolutely does! Thanks guys. > > Kevin > Keep in mind that the output of this type of DDS will NOT produce a 50% duty cycle (which is something you asked for), except at frequencies whose period is an even number of counts of the master clock (i.e., Fmaster/2N). For other frequencies, the maximum deviation from 50% duty cycle is one master clock. For example, if you tried to go output 75 MHz, with a master clock of 160 MHz, you would have a series of 125 ns periods with an occasional high or low stretched out by an extra 62.5 ns to keep the average frequency on track. Still, in your case, if you multiply the 40 MHz up to 160 MHz (go higher if you can) then implement a 32-bit phase accumulator, you should be close enough to 50% duty cycle and have small enough frequency steps to make most people happy. One way to reduce the jitter a little is to use a DAC type of approach, and a little bit of analog circuitry. You would take, say the 4 most significant bits of the phase output, and feed them to a phase to amplitude lookup table, then feed the output of the lookup table to a series of outputs with well-chosen resistor values. The resistor values would be, for example, 200, 400, 800 and 1600, Ohms. Of course, those resistor values don't exist. So you would pick the closest ones you can. These resistors would then all be connected together. This common node, then, would be your analog output. You could buffer it with an op-amp, and feed the op-amp to a 11.2MHz low pass filter, and you would have a pretty good 9MHz - 11.2 MHz sine wave, all things considered. The sine wave could then go to a comparator, and the comparator output would have much lower jitter than you would if you didn't use any analog techniques. This 9-11 MHz digital signal would be the x16 signal, and you would create the base signal by dividing it down. Total external parts: 4 resistors, 1 package with two or four op-amps, one comparator, and a few capacitors. If you used a quad op-amp, you could make a really good low-pass filter, and really cut the jitter down. If this all sounds like too much complication and bother, well, it probably is, but then again, maybe it will appeal to you (or the customer.) Of course, you could also use a DAC instead of the four resistors. You could even use an 8-bit DAC which would really help cut down the jitter, but would force you to implement an 8-bit output phase to amplitude converter. And the ultimate would be to put an Analog Devices DDS on the board. Then you would use the FPGA to generate the 160 MHz clock, program the DDS, and divide down the frequency output of the DDS by 16. That is what I would do. --Mac > Ray Andraka wrote: >> kevin@firebolt.com wrote: >> >> >Please correct me if I'm wrong (probable), but aren't DSS's used > just >> >to create the numeric representation of a requested wave-shape. > Sorry >> >I didn't clarify in my original post, I only need to output a square >> >wave (0/1) over the standard FPGA I/O. As I would still be clocking >> >the DSS at 40 MHz, I wouldn't be able to get better >> >resolution/granularity for frequencies between 500 to 700 kHz that >> >would be able to be multiplied by 16 based on a 40 MHz clock Is > there >> >a way to make the DSS asynchronous? Sorry if I'm missing something >> >obvious. >> > >> >Kevin >> > >> > >> > >> Not quite. You just need the phase accumulator portion of a DDS. > the >> most significant bit out is your square wave output. The output will > >> have a jitter of at most +/- 1 period of you master clock. >> >> This is basically an accumulator to which you add a fixed increment > on >> each clock. A k bit accumulator with an increment value of N will >> overflow (ie lap) N times in 2^k clocks. For example, if the >> accumulator is 4 bits and it is incremented by 1, it takes 16 clocks > to >> overflow, so once in 16 clocks. If instead the increment value is 5 > it >> overflows 5 times in 16 clocks following this sequence: >> 0 >> 5 >> 10 >> 15 >> 4 >> 9 >> 14 >> 3 >> 8 >> 13 >> 2 >> 7 >> 12 >> 1 >> 6 >> 11 >> 0 >> >> Note that if you take only the MSB out, you get the equivalent of a >> sampled squarewave. >> >> Increasing the number of bits increases the frequency resolution. >> Increasing the master clock frequency reduces the maximum jitter. >> >> The output frequency is Fo= Fclk * N/(2^k). N is a 2's complement >> value, so if the msb is set, you get negative frequency (ie the > rotation >> is in the opposite direction). >> >> In the case of a classic DDS, some number of the MSBs from this phase > >> accumulator feed a phase to amplitude converter, which might be a > ROM, a >> cordic rotator, or some algorithmic hardware to convert the phase > angle >> (which is the fractional part of a revolution) to the desired > waveshape, >> which is typically sine and cosine. >> >> Hope this helps. >> >> -- >> --Ray Andraka, P.E. >> President, the Andraka Consulting Group, Inc. >> 401/884-7930 Fax 401/884-7950 >> email ray@andraka.com >> http://www.andraka.com >> >> "They that give up essential liberty to obtain a little >> temporary safety deserve neither liberty nor safety." >> -Benjamin Franklin, 1759Article: 83351
If Addrs_In is unused, then the references to spi_addrs will be pruned leaving spi_addrs unused. Mohammed A Khader wrote: > Hello, > > When synthezing the design with Synplify Pro 8.0 it gave the > follwoing Warning. > > CL209 Input port bit <4> of spi_addrs(4 downto 0) is unsed. > CL209 Input port bit <3> of spi_addrs(4 downto 0) is unsed. > CL209 Input port bit <2> of spi_addrs(4 downto 0) is unsed. > CL209 Input port bit <1> of spi_addrs(4 downto 0) is unsed. > > > I am sure that I am using the slice (4 downto 1) as an input to the > mux. > > I tried by assigning this slice to an intermediate wire (signal) and > then to the mux input . But again it is giving the same error. > > Following is the relevant piece of code.... > ntity Ctrl_Ram is > port( > Ctrl_Data_In : in WORD; > Ctrl_Addrs : in unsigned(3 downto 0); > Spi_Addrs : in unsigned(4 downto 0); > Ctrl_Wr : in std_logic; > > Intl_Rst : in std_logic; > Clk : in std_logic; > > Reset : in std_logic; > > Data32_Out : out DWORD; > Data16_Out : out WORD > ); > end entity Ctrl_Ram; > > Architecture arch of Ctrl_Ram is > begin > spi_addrs_intl <= Spi_Addrs(4 downto 1); > Addrs_Mux:process(Ctrl_Addrs,spi_addrs_intl,Intl_Rst) > begin > case Intl_Rst is > when '0' => Addrs_In <= spi_addrs_intl; > when '1' => Addrs_In <= Ctrl_Addrs; > > when others => Addrs_In <= (others =>'X'); > end case; > end process Addrs_Mux; > > > Thank you. > > -- Mohammed A Khader. >Article: 83352
Chip : virtex 2 (microblaze) multimedia board company : xilinx Question : On my system i have 2 environments ... Xilinx Platform Studio and second Project Navigator !! Why do we need 2 env. to interact with the chip ! What is the difference between XPS and Project navigator ... atleast 1 i knoe .. i can't compile c code and debug it using project navigator ( or may b i can..i haven't figured it out yet !! ) I think we can download the bit stream onto the fpga using both the env. hmmm .... thats all..am a bit confused about the 2 ! any help !Article: 83353
In article <SGMEc.2916$486.1576@newssvr25.news.prodigy.com>, license_rant_master <none@nowhere.net> wrote: >I am an ASIC engineer who frequently 'takes work home' with me. >Recently, I began using ssh to remotely login to our company's >servers to run some Verilog/VHDL simulations. Launching >sims (from the UNIX command line) is fairly easy and painless, >but any kind of interactive (GUI) operations are pitifully >slow over an WAN/internet connection. In the past, I >haven't needed to do much more than check on running jobs, >restart them, then logout. Now, I find the need to do some >interactive debugging work (waveform viewing, code editing, >etc.) There are free waveform viewers (gtkwave). Editing code seems like it could be done quite easily without using any vendor tools (gvim works great). > >Since I can't use the company's tools on *my* home machine, I >started investigating various low-cost Verilog simulators to run >under Windows. (I can't use Icarus because it fails to compile a >lot of our company's Verilog RTL.) submit bugs to the Icarus developers. > >Any comments? >What pisses me off the most, is those Cadence/Synopsys/Mentor >"travelling salesman." They come to our company-site, armed with >laptops and LCD-projectors -- then show off how a small x86-laptop >now runs jobs faster than a low-end Sun/IBM RISC workstation. >These EDAs need to be sued for false advertising. At a minimum, >someone needs to challenge their ridiculous license agreement >for products aimed at 'personal' use. > >For now, I've simply told my supervisor 'project schedule slip.' >And I've given up on doing real work at home (now mostly just >catching on documentation and inline RTL-comments.) > The main courses of action that come to mind: 1) setup things so that you do not need to use a GUI to debug (lots of assertions & printing of values - but make it easy to remove them from code before synthesis). If possible use open source waveform viewers like gtkwave. 2) help the open source tools to improve. Icarus for Verilog is already quite good, but if you're seeing problems you should report them. As I said above, submit bug reports. The only way you're going to get around restrictive licenses is to use applications which are not bound by restrictive licenses (open source). They may not always be ready for use at work, but they'll often be OK for work at home. PhilArticle: 83354
In article <40E4C9F9.38C71406@yahoo.com>, rickman <john@bluepal.net> wrote: >JJ wrote: >> >> Ever hear of VPN? > >I'm not sure what you are trying to suggest. If you mean he should run >the programs on an office machine using interface software from home, >that is what he wants to get away from. If you are talking about >checking out the license over the network, that is what is forbidden by >the license. > >What are you suggesting? > But with VPN the license is still checked out only on the machine at work. VPN only allows you to see your work desktop at home, so technically it's probably legal since the tool is not actually running on your home machine at all (your home machine only acts as a terminal). PhilArticle: 83355
"cas7406@yahoo.com" <cas7406@yahoo.com> wrote in message news:<1114549471.965608.217160@f14g2000cwb.googlegroups.com>... > Andre, > > You should be able to constraint the Tco for the DQ and DQS in the > input_setup/clock_to_output preference window. > Check the example at > $ispLEVER/ispcpld/examples/latticeEC/preferences_attributes/ddr/vhdl/ddr.syn > > and let me know. > > rgds, > > cristian Hi Cristian, I checked the example, and yet, the tCO is for the bits of DQ identical. But the example does not use the template from the IP Manager but the particular modules. ispLEVER5.0 is my hope :o) Rgds AndréArticle: 83356
Probably mentioned somewhere in this tread, but perhaps you can convince your company to convert one of the floating licenses to a dongle one? If you go down this road make sure the dongle is insured since the vendor might ask you to purchase the software again if you loose it. If the vendor is using Flexlm you might want to look into the lmborrow feature. I am not 100% sure how it works but it looks like you can take a license token away from the license server for a duration. Hans. www.ht-lab.com "license_rant_master" <none@nowhere.net> wrote in message news:SGMEc.2916$486.1576@newssvr25.news.prodigy.com... >I am an ASIC engineer who frequently 'takes work home' with me. > Recently, I began using ssh to remotely login to our company's > servers to run some Verilog/VHDL simulations. Launching > sims (from the UNIX command line) is fairly easy and painless, > but any kind of interactive (GUI) operations are pitifully > slow over an WAN/internet connection. In the past, I > haven't needed to do much more than check on running jobs, > restart them, then logout. Now, I find the need to do some > interactive debugging work (waveform viewing, code editing, > etc.) > > So I thought, ok, I'll just install Linux at home and check > out a license remotely from the company. The system > administrator told me "NO!" this is forbidden, due to the license > agreements of just about every EDA-tool vendor. According to the > language/legalese of the license-agreement, a license 'seat' > is tied to a physical location called 'site.' > > There are minor differences among the 'site-radius', but the > end-result is the same ... no executing the tool on hardware outside > of the radius: > > Cadence : 1 mile radius within licensed machine-node > (Sysadmin told me this...didn't double-check myself.) > > Synopsys: 5 mile radius within licensed machine-node > (couldn't find the agreement, but found this on Solvnet.) > > Model/Mentor: 800 meter (0.5mi) radius within licensed machine-node > (Download the user's manual for any Modelsim product.) > > ... > > At this point, I think, well alright, most of these EDA tools > are $100,000 USD and up, so it's reasonable for the vendor to impose these > terms. EDA companies don't want 1 company buying a huge site-wide (100+) > licenses, then randomly 'renting' them out over the internet. > > I mentally used this analogy to convince myself this is ok: > I buy broadband internet service for my household. > It's "unlimited" for my household -- not my neightborhood or someone > driving by on a WiFi laptop. Fair enough... > > Since I can't use the company's tools on *my* home machine, I > started investigating various low-cost Verilog simulators to run > under Windows. (I can't use Icarus because it fails to compile a > lot of our company's Verilog RTL.) > > /RANT ON > > 1) Modelsim/PE "Personal Edition" -- *exact* same license agreement > as their premiere Modelsim/SE. > > "Mentor Graphics > grants to you, subject to payment of appropriate license fees, a > nontransferable, nonexclusive license to use > Software solely: (a) in machine-readable, object-code form; (b) for your > internal business purposes; and (c) on > the computer hardware or at the site for which an applicable license fee > is paid, or as authorized by Mentor > Graphics. A site is restricted to a one-half mile (800 meter) radius." > > *RIDICULOUS* If I were a design-consultant, and my laptop were > my primary compute platform, how am I supposed to comply with a > 'site' radius? By their language, I can't run Modelsim > if I drive more than 0.5mi from my home-residence/business?!? > > 2) ok, so next I move on to Cadence's "Verilog Desktop" > > Wow, same story -- the language of their license agreement brings > me to the same conclusion. Install on laptop -- automatic > non-compliance with their agreement (unless you 'lock down' the > laptop with a 1-mile chain.) Funny how their salesman now use > x86-laptops for nearly *all* customer-site product demos?!? > > 3) I may investigate Verilogger Pro or Simucad, but I figure why bother. > I'll probably just end up getting angrier... > > ... > > /RANT OFF > > Any comments? > What pisses me off the most, is those Cadence/Synopsys/Mentor "travelling > salesman." They come to our company-site, armed with > laptops and LCD-projectors -- then show off how a small x86-laptop > now runs jobs faster than a low-end Sun/IBM RISC workstation. > These EDAs need to be sued for false advertising. At a minimum, > someone needs to challenge their ridiculous license agreement > for products aimed at 'personal' use. > > For now, I've simply told my supervisor 'project schedule slip.' > And I've given up on doing real work at home (now mostly just > catching on documentation and inline RTL-comments.) >Article: 83357
Peter Alfke wrote: > I remember that we shipped XC3000 and XC4000-type devices for down-hole > (oil exploratory drilling) applications, You have an excellent memory :-) > where they were used for week-long operation at 175 degr C. yes, several weeks if not months... When designing these applications we apply some derating factors (derived by the customer's own -costly- qualification process), but they are surprisingly "reasonable". Power consumption is indeed a big issue with such high ambient temp. This ruled out some derived 4k families. > .... but some plastic packages > behave strangely above 140 degrees. Our customer reports that they were surprised by the increase of quality of modern plastic packages (wrt to high temp behavior). The temperature elevation being progressive in such applications probably helps, but that's definitely not my domain of expertise. Bert CuzeauArticle: 83358
There are lots of things that sometimes you "can get away with" on MGT use. What you get away with depends on how fast your MGT is going to run. The decoupling strategy affects the power supply noise and has the effect of creating jitter within the MGT or output signals. In short it limits the maximum data rate you can achieve. Worth also saying is that some packages of Virtex2-Pro have capacitors built in if that is what you are using. We have bought both sizes of these parts from DIGI-KEY. There are in the US but delivery to UK is usually 2 days. If you run into issues getting them there email me on our Support email, listed on our website, and I can probably find a few for you. John Adair Enterpoint Ltd. - Home of MINI-CAN. The low cost Spartan3 CAN Bus Development Board. http://www.enterpoint.co.uk "Roger" <enquiries@rwconcepts.co.uk> wrote in message news:mrSbe.9072$WW5.3120@newsfe2-win.ntli.net... > The RIO User Guide (UG024) stipulates that the RIO supply pins need to be > filtered using a Ferrite bead and a capacitor. It's very specific about > the bead being either of 2 Murata parts and the capacitor being a 0.22uF > 0603 device. > > The ML300 board however doesn't adhere to the capacitor recommendations > and uses a larger device. How important is it to stick rigidly to the > User's Guide, does anyone have any relevant information on this? > > I'm having problems finding a supplier of the ferrite beads. Similar > question: is it really so important that I use either of the 2 parts > stated in the UG? > > TIA. > > Rog. >Article: 83359
In comp.arch.embedded Jason Zheng <xin.zheng@jpl.nasa.gov> wrote: > I'm trying to write a graphics demo program on an ML-300 board with > embedded PowerPC CPU and 128MB of RAM, no graphics acceleration chip. I > got the linux kernel running, and have been advised that regular X11 > will not run because it takes too much memory and I need to run some > other memory-extensive tasks on the background. If so, it'll be the *other* things that're killing you, not X11. X11 can feel like a memory hog if you have 16 MB or less. I've been using a 16 MB (later upgraded to a wopping 32 MB) Pentium-100 Linux box as my key X11 terminal for years. It ain't overwhelminly fast, but it works. Switching away from X11 to something else is not going to gain you enough memory to pay for the hassle. -- Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de) Even if all the snow were burnt, ashes would remain.Article: 83360
Hi newsgroup, in my last post "SYNC + FIFO" I talked about the sychronization method of an external data stream. Additional to the bus data I have some control signals coming from the USB transceiver which are also synchronous to the RXCLK which I use as the FIFO write clock (see last post). In order to respond directly to the control signals I get from the transceiver(for example: USB transceiver drives one control signal high to notify the FPGA to place the next data byte on the DATA[7..0] bus) I have to use the control signal from the pin in my state machine running with the RXCLK. What recommendations do you make when using such a signal from a pin with regard to placement, timing constraints etc. ? Thank you for your great help. Rgds AndréArticle: 83361
Roger, You are not required to use the 2 Murata ferrite beads that are mentioned in the user guide. What you should use are ones with similiar or better characteristics of low DC resistance (<0.7ohm) and high isolation (>600 ohm @ 100 MHz). TDK for instance has similiar versions and Murata has over versions that we don't mention such as the BLM18EG601SN (0.35 ohm @ DC, 600 ohm at 100 MHz). The use of the external capacitor is only required for the wirebond (FG) packages. The flipchip (FF) packages have this capacitors inside for Virtex-II Pro and Pro X. Please don't use the ML300 as an implementation guide for RocketIO it was developed very early in the life cycle of Virtex-II Pro and as a piece of hardware it is very expensive to revise it when new knowledge is learned. In contrast, the ML321, ML323 and ML325 boards are up to date with the user guide. Ed Roger wrote: > The RIO User Guide (UG024) stipulates that the RIO supply pins need to be > filtered using a Ferrite bead and a capacitor. It's very specific about the > bead being either of 2 Murata parts and the capacitor being a 0.22uF 0603 > device. > > The ML300 board however doesn't adhere to the capacitor recommendations and > uses a larger device. How important is it to stick rigidly to the User's > Guide, does anyone have any relevant information on this? > > I'm having problems finding a supplier of the ferrite beads. Similar > question: is it really so important that I use either of the 2 parts stated > in the UG? > > TIA. > > Rog. > >Article: 83362
ALuPin wrote: > Hi newsgroup, > > in my last post "SYNC + FIFO" I talked about the sychronization method > of an external data stream. > Additional to the bus data I have some control signals coming from > the USB transceiver which are also synchronous to the RXCLK which > I use as the FIFO write clock (see last post). > > In order to respond directly to the control signals I get from the > transceiver(for example: > USB transceiver drives one control signal high to notify the FPGA to > place the next data byte on the DATA[7..0] bus) > I have to use the control signal from the pin in my state machine > running > with the RXCLK. > > What recommendations do you make when using such a signal from a pin > with regard to placement, timing constraints etc. ? > > Thank you for your great help. > > Rgds > Andr=E9 If latency is not an issue, I would register the control signal at the IOB to make sure you don't have setup timing issues. Then add another delay stage (register) for the DATA[7..0] bus so you can use the control signal a cycle later. If you need to reduce latency into your FIFO, you need to create a timing spec in the ucf file for the control signal like: OFFSET =3D IN 7.2 ns BEFORE "RXCLK"; to make sure your state machine does not exceed the input setup time available. If you haven't assigned pins yet, I would suggest grouping the control pin near the data pins so your state machine can be placed easily near the control input.Article: 83363
Hi everyone !! Could anybody tell me how to change the On-Chip Memory clock frequency. I have the Power PC running at 300MHz and the OCM at 100MHz. What all I did to double the OCM frequency was that I added the CLK2X port of the Digital Clock Module (DCM) and connect it to the powerpc port BRAMDSOCMCLK and the dsocm port DSOCM_Clk. Did I do any mistake, or is it something more that I need to do here!! Well, I am using a Virtex II Pro device. I will add the relevant (changed) part of the MHS file here: BEGIN dcm_module PARAMETER INSTANCE = dcm_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLKFX_BUF = TRUE PARAMETER C_CLKFX_DIVIDE = 1 PARAMETER C_CLKFX_MULTIPLY = 3 PARAMETER C_CLKIN_PERIOD = 10.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_EXT_RESET_HIGH = 1 PORT CLKIN = dcm_clk_s PORT CLK0 = sys_clk_s PORT CLKFX = proc_clk_s PORT CLKFB = sys_clk_s PORT RST = net_gnd PORT LOCKED = dcm_0_lock PORT CLK2X = dcm_0_CLK2X ########## WHAT I ADDED!! END BEGIN dsocm_v10 PARAMETER INSTANCE = docm PARAMETER HW_VER = 2.00.a PARAMETER C_DSCNTLVALUE = 0x85 PORT DSOCM_Clk = dcm_0_CLK2X ### WHAT I CHANGED !! Before it was sys_clk_s PORT sys_rst = sys_bus_reset END BEGIN ppc405 PARAMETER INSTANCE = ppc405_0 PARAMETER HW_VER = 2.00.c BUS_INTERFACE JTAGPPC = jtagppc_0_0 BUS_INTERFACE DSOCM = docm BUS_INTERFACE IPLB = plb BUS_INTERFACE DPLB = plb PORT PLBCLK = sys_clk_s PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ PORT RSTC405RESETCHIP = RSTC405RESETCHIP PORT RSTC405RESETCORE = RSTC405RESETCORE PORT RSTC405RESETSYS = RSTC405RESETSYS PORT BRAMDSOCMCLK = dcm_0_CLK2X ##### WHAT I CHANGED !!Before it was sys_clk_s PORT CPMC405CLOCK = proc_clk_s END Somebody please help !!! Regards, JoeArticle: 83364
Hi In between, I forgot to mention something, I use VHDL. I have found something like, in Verilog, there is a file called global_params.v "Joey" <johnsons@kaiserslautern.de> schrieb im Newsbeitrag news:d4qs07$t5p$1@news.uni-kl.de... > Hi everyone !! > > Could anybody tell me how to change the On-Chip Memory clock frequency. I > have the Power PC running at 300MHz and the OCM at 100MHz. What all I did to > double the OCM frequency was that I added the CLK2X port of the Digital > Clock Module (DCM) and connect it to the powerpc port BRAMDSOCMCLK and the > dsocm port DSOCM_Clk. Did I do any mistake, or is it something more that I > need to do here!! > > Well, I am using a Virtex II Pro device. I will add the relevant (changed) > part of the MHS file here: > > BEGIN dcm_module > PARAMETER INSTANCE = dcm_0 > PARAMETER HW_VER = 1.00.a > PARAMETER C_CLK0_BUF = TRUE > PARAMETER C_CLKFX_BUF = TRUE > PARAMETER C_CLKFX_DIVIDE = 1 > PARAMETER C_CLKFX_MULTIPLY = 3 > PARAMETER C_CLKIN_PERIOD = 10.000000 > PARAMETER C_CLK_FEEDBACK = 1X > PARAMETER C_EXT_RESET_HIGH = 1 > PORT CLKIN = dcm_clk_s > PORT CLK0 = sys_clk_s > PORT CLKFX = proc_clk_s > PORT CLKFB = sys_clk_s > PORT RST = net_gnd > PORT LOCKED = dcm_0_lock > PORT CLK2X = dcm_0_CLK2X ########## WHAT I ADDED!! END > > BEGIN dsocm_v10 > PARAMETER INSTANCE = docm > PARAMETER HW_VER = 2.00.a > PARAMETER C_DSCNTLVALUE = 0x85 > PORT DSOCM_Clk = dcm_0_CLK2X ### WHAT I CHANGED !! Before it was sys_clk_s > PORT sys_rst = sys_bus_reset > END > > BEGIN ppc405 > PARAMETER INSTANCE = ppc405_0 > PARAMETER HW_VER = 2.00.c > BUS_INTERFACE JTAGPPC = jtagppc_0_0 > BUS_INTERFACE DSOCM = docm > BUS_INTERFACE IPLB = plb > BUS_INTERFACE DPLB = plb > PORT PLBCLK = sys_clk_s > PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ > PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ > PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ > PORT RSTC405RESETCHIP = RSTC405RESETCHIP > PORT RSTC405RESETCORE = RSTC405RESETCORE > PORT RSTC405RESETSYS = RSTC405RESETSYS > PORT BRAMDSOCMCLK = dcm_0_CLK2X ##### WHAT I CHANGED !!Before it was > sys_clk_s > PORT CPMC405CLOCK = proc_clk_s > END > > Somebody please help !!! > > Regards, > Joe > > >Article: 83365
Hello I was looking in Google, but I wasnt able to find the datasheet for the FSL interface of the Microblaze interface. Could someone perhaps email me the datasheet containing the timings for readings and writings? Thanks PhilippArticle: 83366
Hi,
I have my clk from the pad connected to an ibufg like this:
IBUFG_clk_main: IBUFG port map (
O => clk_main, -- Clock buffer output
I => clk -- Clock buffer input (connect directly to top-level
);
dcm1_1 : dcm1 port map (
CLKIN_IN => clk_main,
RST_IN => RESET,
CLK0_OUT => clk_int,
LOCKED_OUT => locked,
CLKDV_OUT => clk_8m,
CLKIN_IBUFG_OUT => open);
at the output of the IBUFG are 2 dcms. Durin NgdBuild I get these errors:
ERROR:NgdBuild:455 - logical net 'clk_main' has multiple driver(s):
pin O on block IBUFG_clk_main with type IBUFG,
pin PAD on block clk_main with type PAD
WARNING:NgdBuild:464 - input pad net 'clk_main' drives multiple clock
buffers
ERROR:NgdBuild:924 - input pad net 'clk_main' is driving non-buffer
primitives:
pin O on block IBUFG_clk_main with type IBUFG
What do I have to do?
Can somebody explain when and where I have to use an extra BUFG?
Thank You.
regards,
Benjamin
Article: 83367Hello, Does anyone know of any freeware formal verification tool for verilog. Thanks MORPHEUSArticle: 83368
i have been using the two cygwin installs without issue for a while now. didn't do anything special to get it to work.Article: 83369
hello all, I'm looking for a Flexray IP core: Commercial or OpenSource project Flexray is a time triggered bus that aims to be the backbone of in car networks (CAN, LIN, MOST...). I'm just trying to find some source to implement a Flexray controller in a FPGA (eg: Spartan II) for educational purpose, just waiting for commercial Flexray controllers to be produced. Does somebody have heard about that? Thanks.Article: 83370
flexray is heavy commerce only, you will not find anything if you are an educational user. so only chance is to make your own from ground zero antti "Mouarf" <mouarf@chezmoi.fr> schrieb im Newsbeitrag news:42710c5d$0$26340$626a14ce@news.free.fr... > hello all, > > I'm looking for a Flexray IP core: Commercial or OpenSource project > > Flexray is a time triggered bus that aims to be the backbone of in car > networks (CAN, LIN, MOST...). > > I'm just trying to find some source to implement a Flexray controller in a > FPGA (eg: Spartan II) for educational purpose, just waiting for commercial > Flexray controllers to be produced. > > > Does somebody have heard about that? > > Thanks. > >Article: 83371
mansoor.naseer@gmail.com wrote: > 2. The second question indirectly relates to the PCI, however, before > that, can someone please tell me exactly how plug and play works? When > the computer boots what steps are taken and how the system determine > how many legal devices are connected to the pci. This is too big a subject for a newsgroup posting. You should pick up the Mindshare PCI book. When you've finished reading that telephone book, you'll have a good idea what goes on. > 3. The base address register, it is not hardwired but assigned on the > fly? I have problems understanding the configuration step in the pci > core. Any comments for a starter? First, buy that book. :) Second, the base address register is assigned by the host during enumeration. The host reads each BAR, which you must preload with a mask that indicates the size of the required space. This mask is simply 1s in the significant bits, so for example setting the BAR to 0xFFFF0000 would request a 64k space (the four LSBs indicate the type of space/etc). If the host decides it can support that BAR, it writes a valid base address to the BAR (overwriting the mask). -aArticle: 83372
ok, I only hoped that some guys already started to build there own. I know that Bosch GmbH is selling such IP, but I'm sure it costs several millions of ? ! I've seen a company that sells a FPGA-based board with FlexRay www.tzm.de so they may sell their IP for lower cost... "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:d4r44s$h98$05$1@news.t-online.com... > flexray is heavy commerce only, you will not find anything if you are an > educational user. > so only chance is to make your own from ground zero > > antti > > "Mouarf" <mouarf@chezmoi.fr> schrieb im Newsbeitrag > news:42710c5d$0$26340$626a14ce@news.free.fr... >> hello all, >> >> I'm looking for a Flexray IP core: Commercial or OpenSource project >> >> Flexray is a time triggered bus that aims to be the backbone of in car >> networks (CAN, LIN, MOST...). >> >> I'm just trying to find some source to implement a Flexray controller in >> a >> FPGA (eg: Spartan II) for educational purpose, just waiting for >> commercial >> Flexray controllers to be produced. >> >> >> Does somebody have heard about that? >> >> Thanks. >> >> > >Article: 83373
FYI: I found that it was necessary to unzip the self-extracting exe file for webpack 7.1 and then run 'wine setup.exe'. If I tried to run 'wine WebPACK_71_fcfull_i.exe' wine would report an error about the exe not being a Win32 executable. So first run: 'unzip WebPACK_71_fcfull_i.exe' and then run 'wine setup.exe'. (thanks to Uwe Bonnes for pointing this out) Also I found a hint about the GUI in the Windows version of webpack 7.1 by doing that unzip: There is a dll file called libQt_Qt.dll that gets extracted. This seems to hint that the Windows ISE 7.1 GUI is based on Qt. If so, then why doesn't the Linux version seem to be Qt-based (they still seem to be using WindU)? Maybe this is an indicator that there will be a Qt based GUI for the Linux version soon (that would be a good thing). PhilArticle: 83374
Hi Pete, There were issues with multiple Cygwin installations long ago, but I think they were corrected in the Nios I 3.1/3.2 time-frame... as such I'm surprised to hear that you ran into trouble with Nios II - perhaps something else is going on? Just as a reference point, I personally use a generic Cygwin installation installed in a separate location from Altera's (which now goes into quartus/bin/cygwin)... in fact we (as Nios/SOPC developers at Altera) use a separate Cygwin installation extensively (on our desktop PCs as it provides a nice cross-platform development/build-system setup; so many people have this working. The one tip that comes to mind to ensure that wires don't get crossed. I can think of two things: environment variables, and cygwin1.dll (there are a number of versions of it and you want whatever shell you open up to be using the most recent one). I would carefully check that, when you open your Altera SDK shell, your environment variables & path do not point to your separate standalone Cygwin installation -- this is how things are on my setup. I also checked what my environment looks like with my standalone Cygwin installation, and to my surprise there were path entries pointing to the Altera installation of Cygwin. Everything functions normally, though. You might also try a quick registry scan to see if there are any relics from the past floating about. In my working setup, I started from a clean PC with nothing on it, and installed Quartus and then Cygwin separately. If this doesn't help feel free to send me an email offline and I'll send you a cut & paste of what my environment looks like. Jesse Kempa Altera Corp. jkempa at altera dot com
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