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Could you declare another "mask" slv that validates the divider result slv? Dan Nilsen wrote: > Hi all! > > I have a problem that someone here might have the answer to. I have a > divider that takes inputs of 13 and 12 bits, and produces an output of > 12 bits. I have a component to strip away the redundant bits from the > divider, if the result of the division is, say an int value of 6, I > don't want to use all 12 bits. This circuit is a part of an MPEG-4 > device, a quantizer, so I want to compress as much as possible. My > question is then, how do I declare the ports on the component that > strips away the bits to output an std_logic_vector that is not fixed > in size, but dynamic? This must be synthesizable. Guess there are many > ways of doing this, and I hope someone has got an answer to me. > > Thanks, > > Dan NilsenArticle: 83401
What exactly is this problem solving? I assume that any use of Matlab implies DSP at more mundane precision levels ie single precision. You haven't mentioned what performance requirement you have, how many doubles FP ops/sec. It looks like if you could do this at all in an FPGA you will be needing a big one or will settle for many cycles. If its low I might have said MicroBlaze with a single precision FPU. You could design your own FPU free of the complexities of IEEE, when I 1st leart FP, it was tought as something straight forward, now its all magic. You could perhaps use block floating point, or use differnet number systems. regards johnjakson at usa dot comArticle: 83402
I am using VirtexE to communication with an ADI's chip. The interface include, write, read, Data, and Address. I wish FPGA communication with the chip on FPGA main clock, which is up to 65MHz. I used a synchronized signal gated with the Clock to generate the write, read signal. Data and Address signal are synchronized. The problem is: 1) write/read signal often generate one more period than what I needed. although I could overcome it by adjust control signal's edge sensitivity, but it maybe reappear when I resynthesize the design. The reason is time delay of 2 inputs(one is clock, one is control signal) of the LUT4 vary greatly. Can I limit delay difference of the 2 inputs to an acceptable level? if it is, How could I do? 2) the timing of address, data and write/read is inconsistent with the timing required by ADI. I could delay some signal by add buffers or invertors. But I am afraid if it is work well if I add this modular to the top design. Is there any better way? if I generate the w/r signal synchronized with the clock, the problem may do not exist. But I should drive the clock twice high, I don't know if VirtexE can work well on 125MHz. Thank you for your advice.Article: 83403
Hi, What do these MAP errors mean: WARNING:MapLib - Property RLOC on wrsel7 not supported for simple gates ignoring. WARNING:MapLib - Property MACRONAME on wrsel7 not supported for simple gates ignoring. This is happening on some LUTs but not all. I'm confused, and it messes up my RPMs. How do I convince the mapper to place the damn LUTs? -JimArticle: 83404
johnp wrote: > Bryan - > > Maybe I'm jaded since I'm a consultant, but a lot of engineers just > don't > understand subtle issues like clock domain crossing. I've had to clean > up so many bugs in this area that I can't count them all. Just when > you think > you've seen every way to send signals between clock domains > incorrectly, > a new way is invented. We are a Design house plus we train about 300 engineers per year, and I have exactly the _same_ experience a Bryan. And what I see in the newsgroup doesn't tell me that every engineer writing VHDL does it with a clear understanding of these issues and of their solutions. I can only say for France, but here, the language and Electronic Design is very poorly taught even in the most prestigious Engineering schools (they don't even teach what Static Timing Analysis is !). We train lots of young engineers, and they have all the same feedback and stories. In our consulting business we sometimes do kind of "PostMortem" on designs that fail miserably, and the issues end up having a very basic cause. Sort of 80-20 here too : 80% of the failures have a very low complexity reason and could be avoided by simple rules. The reason of failures (respins) in Asic design as reported year after year by Synopsys seem to say as much (with better figures, since beginners are not allowed here). Another point I see is personal satisfaction. It's rewarding to create a complex working system in a small FPGA in a few days or weeks. It's no so satisfying to laboriously recreate an inferior version of something done by others and freely available. That's why, in our Educational Kit, I try to set up fancy exercises and stay away from Trafic Light Controllers. I think it's more fun to drive a thermometer chip, an LCD,or read a Smart Card, or create a UART, and not much more complex. Bert CuzeauArticle: 83405
On Thu, 28 Apr 2005 08:51:00 -0700, dwesterg@gmail.com wrote: > i have been using the two cygwin installs without issue for a while > now. didn't do anything special to get it to work. I've got something in the region of thirty different programs on my pc with their own copy of cygwin1.dll of various vintages, including two cygwin trees (a "normal" cygwin tree, and a Quartus / Nios II tree). I also have a couple of cygwin services (such as a ssh demon) running on my w2k box at all times. All in all, it is surprisingly successful, although occasionally a program will complain about incorrect cygwn1.dll versions. The solution is simply to start it again - in most cases, that works. I believe cygwin have recently made some effort to deal with their own not insignificant contribution to windows dll-hell. The latest version (from just a few days ago) specifically addresses compatibility problems with different versions.Article: 83406
As a student that is about to enter the workforce in the US, I find that I am lacking many of the skills that were mentioned in this thread. I know what clock domain crossing is and I know that you can do it with an asynch fifo, but I wouldn't know where to begin in designing one. This kind of thing is simply not taught in school. Static timing analysis is also not taught. Honestly strong VHDL isn't taught either (and Verilog is not taught at all). So my question to all of those seasoned gurus out there is where did you learn things like clock domain crossing and static timing analysis? Did you folks learn these things the hard way (screwing up and having to pay for it)? Did you take a course? Did you guess your way through it? I would love to learn these things, but frankly, I don't have a clue where to start. You may be asking why a person like me could even think of entering into a marketplace without those skills, but I do have my other qualities and my university has a very strong analog circuits program. Also I have taught myself Verilog and have learned a lot of state machine things and synthesis things. Hopefully those in the know can provide information for all of those students out there like me that don't know about advanced topics and don't have a resource for learning them and don't know where to begin looking for a resource. And my input into this thread. I would say that the Xilinx built in async FIFOs are going to be faster than hand designed. The reason is simply that they have dedicated logic. If they are well tested (and I'm willing to believe they are) and they're faster, then it's hard to argue for spinning your own. The knowledge may be important (and I think it is), but if there's a faster, already tested implementation that is free, my pocket book and my time card are telling me that's the way to go. Thanks for the input, ArlenArticle: 83407
Hi John, Thanks for your feedfack. >What exactly is this problem solving? Using the FPGA to compute this function instead of CPU. > how many doubles FP ops/sec. There is no performance requirement for my concern, as long as the function is evaluate from the FPGA instead of CPU. > It looks like if you could do this at all in an FPGA you will be needing a big one or will settle for many cycles. Size of logic gates that it consumed is also not a matter. > MicroBlaze with a single precision FPU Thanks for given this information, but I don't know to implement this onto a FPGA, what is the best way that I can get start with designing this FPU? > You could perhaps use block floating point, or use differnet number systems. But normally the floating point IP block doesn't have trigonometric function Kindest regards, StanleyArticle: 83408
Hi Mike,
I assume when you say move around you mean taking it home? I just checked my
Modelsim license and the 800m clause applies to any license, nodelocked or
floating. However, I would say that as long as your Modelsim dongle is
nodelocked, insured and you work for the company that paid for the license
than I don't believe Mentor will complain about a license breach if you take
it home. I can be 100% sure though since I don't work for Mentor but I
assume they have more important things to do :-)
Regards,
Hans.
www.ht-lab.com
"MikeJ" <support@{nospam}fpgaarcade.com> wrote in message
news:1114724727.23483.0@despina.uk.clara.net...
>I have a company modelsim dongle, which I have always assumed I can move
> around and use on any machine the dongle is currently plugged into. By
> definition I can only be using it in one place at a time ...
>
> Surely this is allowed ??
>
> /MikeJ
>
> p.s. sorry I mailed you Hans, hit the wrong button :)
>
>
Article: 83409Thank you all for you help. I can make some more progress with my design now. Rog. "Roger" <enquiries@rwconcepts.co.uk> wrote in message news:mrSbe.9072$WW5.3120@newsfe2-win.ntli.net... > The RIO User Guide (UG024) stipulates that the RIO supply pins need to be > filtered using a Ferrite bead and a capacitor. It's very specific about > the bead being either of 2 Murata parts and the capacitor being a 0.22uF > 0603 device. > > The ML300 board however doesn't adhere to the capacitor recommendations > and uses a larger device. How important is it to stick rigidly to the > User's Guide, does anyone have any relevant information on this? > > I'm having problems finding a supplier of the ferrite beads. Similar > question: is it really so important that I use either of the 2 parts > stated in the UG? > > TIA. > > Rog. >Article: 83410
Hello, I'am trying to use Quartus II and NIOS II sdk for teaching and I'm facing a problem with the JTAG server service on the XP machines that are used by our students. Whenever a user logs in the JTAG server service systematically fails to launch automatically and reports an "error code 0". The only way to make sure the JTAG service is launched correctly is to log in as an administrator and launch it manually from the service dialog box, but of course as soon as the administrator logs off, the problem arise again. Since we use Quartus II in Digital Design classes, we obviously cannot afford to let the student work on machine as an administrator, and I am hence looking for some people who would have had similar problems. PS : strangely, we did no had such problems with Quartus II 3.xx, however since we plan to use the nios II intensively, we need V4.1. Thank you in advance, Steven DerrienArticle: 83411
I have 2 signals that come from an lvds transmitter sources: lvds1p,
lvds1n.
I use an cyclone EP1C6. I want to put these signals on pins 124 and
123.
how can i make this and how a can use after that this signal in my
design
(transmitter -> lvds1p,lvds1n ->fpga:receive these signals -> how can
i group then in signal lvds and the use this final signal ????)
I use Quartus4.1
Thanks
Article: 83412Arlen - A good place to start learning about clock crossing and async fifos is by looking at app notes from companies like Xilinx. Simply realizing the problem exists and realizing it is important is a great first step. Issues in clock crossing are flip-flop metastability, passing busses of data between domains, and Req/Ack handshaking between domains. Metastability is discussed in many papers that you can look for on the web. Basically if you violate the setup/hold time on a flip-flop, it's going to be angry for a while, ie, potentially in a non 1/0 state. I t may hover at an inbetween voltage level, it many oscillate a bit, it may take longer to settle, etc. You r logic has to deal with this. Traditionally, a 2 stage flip-flop chain is considered good enough for this. This solution depends on clock and data rates! Passing data/address/counters between domains is trickier. Assume you send an 8 bit value between domains. Because of delays in the gates and in routing, each bit of the bus arrives at the target flip-flops at a **slightly** different time. Because of this difference, when the targe clock tries to grab the data, it may latch some old data and some new data. In a perfect world, all the incoming bits would arrive at the exact same time and the target flip-flops would grab ALL of either old or new data. In the real world, the target flip flops will grab SOME new data and some old. So, if you are passing fifo address pointers between domains, you have potential problems in getting correct values at each clock edge. Solution: look into Gray coded values to pass back and forth. Since only one bit of a gray counter changes at a time, there is no problem with the receiving flip flops. Sending Req/Ack handshake between domains is another area that can be trickier than one would like. There are efficient ways to do this, I'd suggest some Googling as part of your education. Thought experiments in this area of domain crossing are very educational. Clock crossing is one area where you MUST be paranoid. The problems in general are hard or impossible to simulate and hard to find in the real world. Since they are semi-random, you can spend a lot of effort tracking down a problem that only happens once an hour. I hope this helps! John PArticle: 83413
Hi,
since I am a beginner with fpgas and vhdl, I want to ask if some
fpga-veteran can give me some hints how to improve my coding-style.
Attached is my latest code (for controlling an LCD via LVDS), it works
in the simulator and is not yet tested on the chip.
regards,
Benjamin
-- lvds_tick is a clock at 7x pixel-clock (140 MHz)
-- lvds_clk is the clock for the lvds bus, same as pixel clock, but not
symmetric
-- like this for one pixel period: --___--
process (lvds_tick,screen_reset)
begin
if screen_reset='1' then
--load_lvds<='1';
lvds_div<=0;
elsif rising_edge(lvds_tick) then
if lvds_div = 0 then
lvds_clk <='1';
--load_lvds<='0';
elsif lvds_div = 2 then
lvds_clk<='0';
elsif lvds_div = 5 then
lvds_clk<='1';
elsif lvds_div = 6 then
lvds_div <= 0;
end if;
if lvds_div = 7 then
lvds_div <= 0;
--load_lvds<='1';
else
lvds_div <= lvds_div + 1;
end if;
end if;
end process;
-- this process generates the load impuls for the shift register below
process (lvds_tick,screen_reset)
begin
if screen_reset='1' then
load_lvds<='1';
elsif falling_edge(lvds_tick) then
if lvds_div = 7 then
load_lvds<='1';
else
load_lvds<='0';
end if;
end if;
end process;
-- generates serial data for one lvds-pair
lvds_1:process (lvds_tick)
begin
if load_lvds= '1' then
reg1 <= lvds1;
elsif rising_edge(lvds_tick) then
reg1 <= reg1((7-2) downto 0) & '0';
end if;
lvds_1_in <= reg1(7 - 1);
end process;
Article: 83414Jim George wrote: > Hi, > What do these MAP errors mean: > > WARNING:MapLib - Property RLOC on wrsel7 not supported for simple gates > ignoring. > WARNING:MapLib - Property MACRONAME on wrsel7 not supported for simple > gates ignoring. > > This is happening on some LUTs but not all. I'm confused, and it messes > up my RPMs. How do I convince the mapper to place the damn LUTs? > -Jim The problem with attaching RLOC to a gate, even if the gate is instantiated rather than inferred, is that the mapper will not necessarily keep the gate by itself in the final design. Usually several gates can be lumped into a single LUT. The tools might have allowed an RLOC constraint on gates that don't get grouped together, but unfortunately they don't. If you have a combinatorial function that needs to end up with a particular placement, the only way is to instantiate a LUT instead of gates or gate primitives. Instantiated flip-flops don't have this problem.Article: 83415
I am not going to tell you that designing an async FIFO is hard, I hope this doesn't affect your wizard status.Article: 83416
license_rant_master <none@nowhere.net> writes: > I am an ASIC engineer who frequently 'takes work home' with me. > Recently, I began using ssh to remotely login to our company's > servers to run some Verilog/VHDL simulations. Launching > sims (from the UNIX command line) is fairly easy and painless, > but any kind of interactive (GUI) operations are pitifully > slow over an WAN/internet connection. In the past, I > haven't needed to do much more than check on running jobs, > restart them, then logout. Now, I find the need to do some > interactive debugging work (waveform viewing, code editing, > etc.) Since you are using UNIX-based hosts, you might want to consider looking into NX (http://www.nomachine.com). I have used it for the exact same purpose for years (it wasn't actually called NX back then). For quite some time I had to use a connection going from the local office in Boston,MA to Milpitas,CA and back to Boston. No issues here. Hope that helps, MarcusArticle: 83417
"Bryan" <bryan@srccomp.com> wrote in message news:1114789139.100649.204350@l41g2000cwc.googlegroups.com... > I am not going to tell you that designing an async FIFO is hard, I hope > this doesn't affect your wizard status. Then face up to his challenge. If it isn't hard, you should be able to produce the reliable EMPTY-flag detection and show it works in a couple of hours.Article: 83418
I believe few reply miss the point in saying that for example you don't give complex design to new Eng and so on. Async FIFO can be part of a simple design even as simple as FIFO in Ethernet Receive Path of 10/100/1000 MAC (There are many more examples of course) where the difference in clock is due to ppm's but never the less it require the usage of Async FIFO (though once you understand how to design one in many of those cases you can do "short cuts" knowing the actual requirements). And to the one refer to PLL, last time I learned PLL was Analog devices and not digital unless you use DLL and such but even than DLL can only "somewhat" be done using FPGA logic as the delay element are not "fix" enough, so of course there is limit but to say to new Eng don't learn how to make Async FIFO just because to design the next Pentium might be too much for him is in my own opinion a bad judgment. Obviously each one will guide as he/she find fit but as I see it just as it is important to explains to new Eng the difference between the usage of = and <= AND show how even though he should use <= for FF he can still use = if he pay attention to the order and such the same go with FIFO, first you explain and teach and THAN you show him "shortcuts" which can include use of IP done by other. And by the way as for the simulation feedback there is no reason not to simulate Async FIFO, a bit more interesting than just one clock domain FIFO but again not as difficult as design the next mission to mars. One reason I believe some are "concern/afraid" is luck of simulation and therefore loss of too much time in the Lab and than concern that this will happen again. There is a saying in Asic world that what you didn't test will be the place where you will find your bug. Regretly in the FPGA world since mistake do not cost huge sum's to fix (even for metal fix) Eng tend to only check here and there and not do good coverage testing. Sure while in Asic you can spend easily 6 to 9 month testing in FPGA you are not going to spend this amount of time but never the less you should cover all major point and if the design is not too big there is no reason to cover all point. A good automatic testing using scripts logs memory etc can run and cover in few days A LOT of your design and save you days and weeks not to mention once you start building your test environment next time will be faster and faster and who knows you might stop be warring of teaching new Eng how to design Async FIFO and other BASIC Digital design components. And by the way talking about Xilinx and Metastable etc maybe since Xilinx have so many Eng you can finally come with FF's that can be associate to the second FF in the Synconizer so when we run post P&R simulation we don't need to either play with the sdf or change the FF to "home made FF" that can prevent X from passing. And yes due to Metastable you don't know if it will go "too fast" through and for that you can use $random to give different result when there is violation. Have fun and Enjoy the joy of Digital design.Article: 83419
Hi, how can I add internal signals to the wave output of modelsim? At the moment I have to add all the debug sinals to the port of my main entity. Another question is, if its possible to save the modelsim settings somehow? (wave repesentation as integer, scale, etc...) Do I have to close Modelsim everytime I resynthesize my uut? regards, BenjaminArticle: 83420
Berty, let me answer only one paragraph: You wrote "And by the way as for the simulation feedback there is no reason not to simulate Async FIFO, a bit more interesting than just one clock domain FIFO but again not as difficult as design the next mission to mars." It is much more difficult than a mission to mars, because a mission to mars can be done, and has been done. Simulating asynchronous clock-domain crossing cannot be done, because the number of timing conditions is, by definition, infinite. It is not my intent to scare anybody, but asynchronous design is tricky, and the worst-case conditions are best explored in your head, not by brute-force computer analysis. (As far as I know, even SPICE cannot analyze metastability...) Peter AlfkeArticle: 83421
I already have an async FIFO, but don't claim it takes wizardry to design one. That would be calling myself a wizard. Anyone that blows their own horn over FIFO design needs to come back down to earth.Article: 83422
Benjamin Menküc wrote:
> Hi,
>
> since I am a beginner with fpgas and vhdl, I want to ask if some
> fpga-veteran can give me some hints how to improve my coding-style.
>
> Attached is my latest code (for controlling an LCD via LVDS), it works
> in the simulator and is not yet tested on the chip.
>
> regards,
> Benjamin
>
> -- lvds_tick is a clock at 7x pixel-clock (140 MHz)
> -- lvds_clk is the clock for the lvds bus, same as pixel clock, but not
> symmetric
> -- like this for one pixel period: --___--
> process (lvds_tick,screen_reset)
> begin
> if screen_reset='1' then
> --load_lvds<='1';
> lvds_div<=0;
> elsif rising_edge(lvds_tick) then
> if lvds_div = 0 then
> lvds_clk <='1';
> --load_lvds<='0';
> elsif lvds_div = 2 then
> lvds_clk<='0';
> elsif lvds_div = 5 then
> lvds_clk<='1';
> elsif lvds_div = 6 then
> lvds_div <= 0;
> end if;
> if lvds_div = 7 then
> lvds_div <= 0;
> --load_lvds<='1';
> else
> lvds_div <= lvds_div + 1;
> end if;
> end if;
> end process;
>
> -- this process generates the load impuls for the shift register below
> process (lvds_tick,screen_reset)
> begin
> if screen_reset='1' then
> load_lvds<='1';
> elsif falling_edge(lvds_tick) then
> if lvds_div = 7 then
> load_lvds<='1';
> else
> load_lvds<='0';
> end if;
> end if;
> end process;
>
> -- generates serial data for one lvds-pair
> lvds_1:process (lvds_tick)
> begin
> if load_lvds= '1' then
> reg1 <= lvds1;
> elsif rising_edge(lvds_tick) then
> reg1 <= reg1((7-2) downto 0) & '0';
> end if;
> lvds_1_in <= reg1(7 - 1);
> end process;
I suggest you could start with :
http://www.alse-fr.com/English/Archive/VHDL_Coding_eng.pdf
Your processes have many errors mentioned in this document.
process 1 : missing reset on lvds_clk
process 2 : you use both edges of the clock ? (do you need this ?)
process 3 : wrong sensitivity list, maybe not synthesizable
depending on the target technology (asynchronous load),
lvds_1_in is clocked by both edges and negatively clock enabled
load_lvds ??
Bert Cuzeau
Article: 83423Benjamin Menküc wrote: > Hi, > > how can I add internal signals to the wave output of modelsim? > Add wave * (use -r for recursive if you like the mess or do trivial things) > At the moment I have to add all the debug sinals to the port of my main > entity. Use drag & drop, can do from a whole instance, very handy > > Another question is, if its possible to save the modelsim settings > somehow? (wave repesentation as integer, scale, etc...) Click on the save button ! (will create wave.do, editable etc) > > Do I have to close Modelsim everytime I resynthesize my uut? Synthesis has nothing to do with ModelSim if you do RTL sim. vcom does compile, restart -f suffient usually. > > regards, > Benjamin The simulator's (on-line) manual is probably a good starting point, maybe even faster than the newsgroup ;-)Article: 83424
ooops, forgot to sign. RTFM. Bert Cuzeau
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