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I'm getting an error during the translate portion of the implement
design section and I have no clue what it is about:
ERROR:NgdBuild:455 - logical net 'blt_blitter_o_memAddr<0>_cyo' has
multiple
drivers. The possible drivers causing this are:
pin G on block XST_GND with type GND,
pin PAD on block blt_blitter_o_memAddr<0>_cyo with type PAD
ERROR:NgdBuild:462 - input pad net 'blt_blitter_o_memAddr<0>_cyo'
drives
multiple buffers. Possible pins causing this are: :
pin I on block dll_rstpad with type IBUF,
pin I on block w_extCe_OBUF with type OBUF,
pin I on block w_fbce0_OBUF with type OBUF,
pin I on block w_fbce1_OBUF with type OBUF
ERROR:NgdBuild:466 - input pad net 'blt_blitter_o_memAddr<0>_cyo' has
illegal
connection. Possible pins causing this are:
pin G on block XST_GND with type GND,
pin DI on block blt_blitter_o_xAddr<5>cy with type MUXCY,
pin DI on block blt_blitter_o_xAddr<6>cy with type MUXCY,
pin DI on block tv_tvs_hcount_LPM_COUNTER_2__n0000<10>cy with type
MUXCY,
pin CI on block blt_blitter_o_memAddr<6>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<9>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<10>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<11>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<12>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<13>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<14>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<15>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<16>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<17>cy with type MUXCY,
pin CI on block blt_blitter__n0000<0>cy with type MUXCY,
pin DI on block blt_blitter__n0000<1>cy with type MUXCY,
pin DI on block blt_blitter__n0000<2>cy with type MUXCY,
pin DI on block blt_blitter__n0000<3>cy with type MUXCY,
pin DI on block blt_blitter__n0000<4>cy with type MUXCY,
pin DI on block blt_blitter__n0000<5>cy with type MUXCY
ERROR:NgdBuild:466 - input pad net 'blt_blitter_o_memAddr<0>_cyo' has
illegal
connection. Possible pins causing this are:
pin G on block XST_GND with type GND,
pin DI on block blt_blitter_o_xAddr<5>cy with type MUXCY,
pin DI on block blt_blitter_o_xAddr<6>cy with type MUXCY,
pin DI on block tv_tvs_hcount_LPM_COUNTER_2__n0000<10>cy with type
MUXCY,
pin CI on block blt_blitter_o_memAddr<6>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<9>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<10>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<11>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<12>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<13>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<14>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<15>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<16>cy with type MUXCY,
pin DI on block blt_blitter_o_memAddr<17>cy with type MUXCY,
pin CI on block blt_blitter__n0000<0>cy with type MUXCY,
pin DI on block blt_blitter__n0000<1>cy with type MUXCY,
pin DI on block blt_blitter__n0000<2>cy with type MUXCY,
pin DI on block blt_blitter__n0000<3>cy with type MUXCY,
pin DI on block blt_blitter__n0000<4>cy with type MUXCY,
pin DI on block blt_blitter__n0000<5>cy with type MUXCY
I've looked at the xilinx web reference, but I don't have multiple
drivers on this signal. The system passes simulation without any
warnings, so what might cause this?
I was getting this on other signals, but I changed how they were worded
at it went away. For example I had something like this
wire [7:0] gfxinput;
wire [3:0] xout;
wire [3:0] yout;
gfxmod gfx(
.input(gfxinput)
);
gfxgen gfxg(
.xout(xout),
.yout(yout)
);
assign gfxinput = {xout,yout};
and that would fail with gfxinput being the error node (gfxgen was
driving xout and yout and gfxmod takes them concatenated as input).
I got the error to go away (go to another net anyway) by changing the
code to this:
wire [3:0] xout;
wire [3:0] yout;
gfxmod gfx(
.input({xout,yout})
);
gfxgen gfxg(
.xout(xout),
.yout(yout)
);
Does this make sense to anybody? Has this happened to anybody else
before?
Thanks for the help,
Arlen
Article: 83101dave wrote: > Erik, where are the links for this starter kit please. On the Spartan-3E page, click on "Spartan-3E Starter Kit": http://xilinx.com/products/spartan3e/s3eboards.htm The page says it won't be available until Q3, so that could be anywhere form 5 weeks to 4 months from now.Article: 83102
Hi, I have just recently updated to ISE7.1. I used to be able to use playxsvf file just fine, but now when I use it, it doesn't work anymore. If I use it after the computer boot up, it said playxsvf501b has encountered an error and need to be closed. If I use IMPACT to find the cable, then disconnect cable, then use playxsvf502b, TCLK alternates every line and TDI and TDO changes. But it doesn't run infitely, it stops after 15 seconds. If it can't find the cable, it would run an infinitle loop according to one of the APPS notes that I read, but this time it stops after about 15 seconds, and go back to the command prompt. Has anyone run into the same problem or successfully use this utility??? Thanks, ALArticle: 83103
I am sorry, it does go into an infinite loop if you try to play an xsvf file that will program the chip. If you play an xsvf file that only read back IDCODE, it goes into that loop for about 3 seconds, then says SUCCESS-Completed XSVF execution, Execution Time - 0.280 seconds.Article: 83104
Lots of companies have 8051 compatible chips... the best known are Atmel, Dallas, Philips, Siemens. Does that mean these guys have to pay royalties to Intel? Or is the 8051 CPU public domain, which could explain why so many guys chose to use it? Thanks.Article: 83105
Duane Clark ha scritto: > The plb_ddr and opb_ddr are for single DDR chips, not a DIMM. So you > will need to modify them to handle multiple chips. This is actually not > that difficult; I have done it myself and have been using the design for > awhile. Hi Duane, first of all thank you very much for the complete and very helpful answer. I would never had any clue on how to proceed without your help. > The solution that I used for this problem was to recognise that in my > application, the mask (DM) bits would never change during a data > transfer. So I let DM use the same clock as DQS, and setup the DM > signals slightly early and hold them slightly longer than needed. Sorry I didn't understand well, have you modified it in the core, or is it just a software thing? >> In fact the UCF that came with the board support package lack of any >> reference to a DDR clock feedback pin, so although I can connect every >> other element, without that pin I can't correctly clock the memory... >> Unfortunately, I couldn't find any design that uses DDR in EDK, so I >> don't know if that pin exists (and it isn't mentioned on the bsp >> software) or if it really isn't possibile to use the xilinx cores with >> it. > > > You will need to simply route this feedback signal internally. Did you routed it with EDK or in the ddr_clock design? > That > means that the phase of the DCM might need to be adjusted in software. > And indeed, the DIMM test bitfile that Avnet provides does indeed > provide the ability to determine and set the optimum DCM phase. > > In practice, while I did implement the ability to alter the phase of the > relevant DCM (the "ddr_clock" in the Xilinx ddr_clocks reference > design), I no longer use that. I have the default startup "PHASE_SHIFT" > set to "33" and never change it (the other DCMs have a "0" phase). I > have used 128MB, 256MB, 512MB, and 1GB DIMMs on 2 different Avnet > boards, all without adjusting the phase, and all operate perfectly. So, just changing the PHASE_SHIFT parameter should be ok? Thank you very much again and sorry for the disturb!!!Article: 83106
ZioPino wrote:
> Duane Clark ha scritto:
>
>>The solution that I used for this problem was to recognize that in my
>>application, the mask (DM) bits would never change during a data
>>transfer. So I let DM use the same clock as DQS, and setup the DM
>>signals slightly early and hold them slightly longer than needed.
>
> Sorry I didn't understand well, have you modified it in the core, or is
> it just a software thing?
They will need to share the same physical clock, so you need to modify
it in the core. If you don't, you will get error messages, I think
during place and route.
>>>In fact the UCF that came with the board support package lack of any
>>>reference to a DDR clock feedback pin, so although I can connect every
>>>other element, without that pin I can't correctly clock the memory...
>>>Unfortunately, I couldn't find any design that uses DDR in EDK, so I
>>>don't know if that pin exists (and it isn't mentioned on the bsp
>>>software) or if it really isn't possible to use the xilinx cores with
>>>it.
>>
>>
>>You will need to simply route this feedback signal internally.
>
> Did you routed it with EDK or in the ddr_clock design?
I did it in the top level design, which in my case is outside of EDK (I
am using the so called "projnav" flow). What I did was to turn one of
the clock outputs into a bidirectional pin. That is, for the DIMM, there
are two differential clocks, so I have:
DDR_Clk_0 : inout std_logic;
DDR_Clk_L_0 : out std_logic;
DDR_Clk_1 : out std_logic;
DDR_Clk_L_1 : out std_logic;
See that one of them is now an "inout". For that one, I instantiated a
buffer:
ddr_clk_io : IOBUF
port map (
I => DDR_Clk_0_O,
IO => DDR_Clk_0,
O => DDR_Clk_0_I,
T => DDR_Clk_0_T
);
I tied the "T" pin to '0', and connected DDR_Clk_0_I to the feedback pin
of the DCM. This means the feedback at least takes into consideration
buf to pin and pin to buf delays. The only thing missing is board delay,
which is relatively small, and constant.
>>That
>>means that the phase of the DCM might need to be adjusted in software.
>>And indeed, the DIMM test bitfile that Avnet provides does indeed
>>provide the ability to determine and set the optimum DCM phase.
>>
>>In practice, while I did implement the ability to alter the phase of the
>>relevant DCM (the "ddr_clock" in the Xilinx ddr_clocks reference
>>design), I no longer use that. I have the default startup "PHASE_SHIFT"
>>set to "33" and never change it (the other DCMs have a "0" phase). I
>>have used 128MB, 256MB, 512MB, and 1GB DIMMs on 2 different Avnet
>>boards, all without adjusting the phase, and all operate perfectly.
>
>
> So, just changing the PHASE_SHIFT parameter should be ok?
Yep, and if you use the clock routing scheme I show above, just try "33"
and probably it will work fine.
Article: 83107I wrote a synthesizeable 4 tap FIR code in vhdl and synthesized it using Xilinx. I have an Xess XSV board with Virtex 800 fpga on it. I am new to FPGA programming. Can some one guide me what steps i have to take to implement my FIR on this board . I believe steps will be synthesize Implement generate bit file using xilinx ISE software But I used an example to implement a & segment LCD counter and i am confused about the functionality of ucf file and how to make one for my design i.e how i can configure inputs and outputs of my design so that i can send an input and see what is the response as an out put on the LCD Thanks, -NaumanArticle: 83108
Hi Gabor, Thanks for the reply. I'm actually having problems with the programming part. Especially displaying the 10bit 2's complement temperature readings on my 4 seven segment display. I'm trying to convert them into binary but for some reason it's not working very well. Do you have a suggestion of how I should read them in? I'm not using the negative temperature readings and I'm only interested in temperatures up to 90deg so I can displaly the actual temp on two displays and the temperature you want to set on the other 2 displays. thanks so much for your suggestions! RuthArticle: 83109
I will pay you a reasonable fee for a copy of the Xilinx ver. 6.2 EDK with manuals. Also, I am looking to purchase ChipScope. Thanks and Regards, TodArticle: 83110
hi there, i have been working on a PCI 5V DAQ card. there is a surprising fact that i have observed regarding the motherboard on which i am mounting the card. it is an old pentium-I 200MHz board containing both PCI and ISA slots (one of those legacy boards). when i mounted the card and checked power supplies, i found that 3.3V supply is simply not there. the PCI spex v2.2 defines 3.3V power supply fingers on the bus. hence i routed my board accordingly (it contains Spartan2 and platform flash mem which require 3.3V for Vcco). is this a generic case or what? has anybody seen/worked on such boards? doesnt this board violate PCI standards? now i will have to change the board. can anyone tell me what i should look for on the motherboard to ensure that it has both types of power supplies supported? TIA, ShreyasArticle: 83111
Hi,
I am write and read from a text file using vhdl. I am using quartus
4.0 to compile and simulate. when I compile the code below, it said
that the writeline, write functions are not synthesis, which is
correct. Then when I simulate using simulator tools, it does not work,
and nothing get written to the "test_1.txt".
Did anyone try to do this in Quartus before? and what is the problems
in my code?
Thank you in advance for ur time and effort,
John.
Library IEEE;
use ieee.std_logic_1164.all;
use std.textio.all;
entity test_1_wrrd is
generic(
Input_File : string := "test_1.txt"
);
port ( a : in std_logic;
-- clk : in std_logic;
b : out std_logic;
s : in std_logic
);
end entity test_1_wrrd;
architecture beh of test_1_wrrd is
begin
Process(a, s)
file p_file : text open write_mode is Input_File ;
Variable l : Line;
Begin
if s = '1' then
b <= '1';
Write ( l, "a");
Writeline ( p_file, l );
else
b <= '0';
end if;
End Process;
End beh;
Article: 83112ahhh... but Cyclone doesn't do bus lvds or have on chip terminators. But in reality.. if you are after blazing speeds and are thinking cheap.. think again.. have you seen the price of the dual core X86 processors ??? Simon "Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:1114259390.945933.295800@f14g2000cwb.googlegroups.com... > > If folks are looking for blazing speed, then I suggest they look at > > Virtex 4. The Spartan team is all about value (lowest cost). If you > > > have already targeted a Spartan 3, and are moving to 3E because of > the > > IO vs CLB cost benefits, then I am sure the FAE's and tools are there > to > > support you. > > I doubt many people who need a low-cost device can afford a V4... > > If you want value AND blazing speed, I'd suggest taking a look at > Altera's Cyclone/Cyclone II, which are 50-60% faster than Spartan-3 > (and thus 70-80% faster than Spartan-3E? Eek). But don't trust me. > Download our Quartus II Web Edition and give things a whirl. > > As for Austin's story that Xilinx is guard-banding the timing models by > a lot, I'm not sure why they need to do that. What is the cause for > the huge uncertainty? They should know the process well and thus have > good-quality transistor models and capacictance tables. And the > architecture really hasn't changed. Shouldn't a good (<10% error) > timing model be a piece of cake? > > See? No hiding behind a fake address for me -- I have no qualms > trolling as me. > > Paul Leventis > Altera Corp. >Article: 83113
I would suggest a dual processor with lots of dual port ram and 64 bit at least. That way when the processor is busy place and routeing, you can be doing the documentation in Word. So far I think the jury is out as to 32 / 64 bit code .. but I think 32 bit is slightly faster until processors speed up Simon "Marco" <marcotoschi_no_spam@email.it> wrote in message news:d4deaa$3ot$1@news.ngi.it... > I need to buy a new PC. What is the best processor for saving time during > synthesis projects? > > AMD Athlon 64 > Intel XEON > Intel Pentium 4 > > ?? > > Thanks > Marco > >Article: 83114
Thomas Womack wrote: > The clock cycles for commercial CAMs seem pretty long; I wonder > whether a solution that stored the data in the first part of each of a > large number of block RAMs, with a very simple counter for addresses > and a comparator, running at a much quicker internal clock, might get > better results. This feels as if it could be made a bandwidth > problem, and FPGAs lack not in bandwidth. For the (one) cam part I've seen - the latency was a number of clock cycles. I've wondered whether it could actually be doing something a little more complex like a binary tree type search. Still have to deal with don't-care type masks though, I suppose. JeremyArticle: 83115
Hi Group, I am looking for some rough estimate kind of numbers. The numbers don't really need to be precise, just guesses and estimates. Okay, here's what I need. What would the relative number of CLBs needed be for the following types of synthesized circuits (assuming the FPGA they were implemented on did NOT have any special components that would lessen the number of CLBs needed) 1. 32 bit integer adder 2. 32 bit integer multiplier 3. 32 bit integer divider 4. Double precision floating point adder (I know this one is expensive) 5. Double precision floating point multiplier 6. Double precision floating point divider 7. Double precision floating point square root I know there are different algorithms for some of these operations, some are parallel some are serial, just whichever you know would help. Rough guesses are all I need. If you want, just take whichever would be the lease, use that as a baseline of 1.0 for the relative sizes. Thanks everyone. -AKiriwasArticle: 83116
Before you start the design of a Content-Addressable memory you have to answer a few questions for yourself: Mow many entries? How fast do you need the answer? How many bits per word, and how many of them need to be searched ? (usually not all of them) What do you intend to do with multiple matches? And are all these decisions unchangable or variable? After you know what you want, you can explore various techniques, even in an FPGA. Peter Alfke, Xilinx ApplicationsArticle: 83117
Pick a VLSI book and read about clocking :-) This vaguely
mentions it:
http://courses.ece.uiuc.edu/ece425/lecture_files/lecture6.pdf
Article: 83118Moti Cohen wrote: > Hi all, > I would like to get into a CAM design for FPGA. > Does any of you know about where can I find material on this subject? I > will appreciate stuff like tutorials and reference designs (examples in > any HDL).. > > Thanks in advance, Moti. If you want a fairly small array of matches and possibly multiple matches with wildbits, follow the usual CAM papers, but if you want a really large dictionary for unique matches the only practical solution is hash tables or possibly n ary trees for some uses. For my cpu design I use an inverted page table for the MMU which really amounts to a hash table. IBM have used this forever and its now becoming more common due to huge address spaces >>32bits. This stuff is pretty well covered in any CS text, from Knuth in the 60s to every body else reinventing the same thing. In the CS world you can find quite a bit about hashing right next to random no generators, but for HW purposes they are misleading, they will tell you to go for tables that are prime no in size and use nice hash functions that often include modulo % with a prime no and maybe again for rehash. Then they also suggest link list chaining collisions. If you go back to before the CS folks got too clever, the hash literature was much more straighforward to do in HW. I won't go into it here, you will have to read up on all the issues and various workarounds. Before you even think about HW, study the problem in plain C with data sets similar to what you expect with sequences of similar reads/writes. Choose hash functions that are mostly based on xors, shifts, and possibly rnd table lookups. If you keep the entire memory table about 50% full/empty, the avg no of probes to get at data can be very small close to 1.7 or so but can also be variable. When you are comfortable with the C model and the FSM that goes with it, the HW version shouldn't be too difficult. johnjakson at usa dot comArticle: 83119
Duane Clark ha scritto: > They will need to share the same physical clock, so you need to modify > it in the core. If you don't, you will get error messages, I think > during place and route. Hi Duane, thank you very much again for all the infos, you've been very kind, and now I understood how I can proceed! I'll start to prepare the design and as soon I'll be back in the lab I'll try it on the board, and let you know if it all works. Thank you very much again!Article: 83120
How about take (or write) an HDL implementation and try to synthesize with the free Webpack? Works every time. akiriwas@gmail.com wrote: > Hi Group, > > I am looking for some rough estimate kind of numbers. The numbers > don't really need to be precise, just guesses and estimates. > > Okay, here's what I need. What would the relative number of CLBs > needed be for the following types of synthesized circuits (assuming the > FPGA they were implemented on did NOT have any special components that > would lessen the number of CLBs needed) > > 1. 32 bit integer adder > 2. 32 bit integer multiplier > 3. 32 bit integer divider > 4. Double precision floating point adder (I know this one is > expensive) > 5. Double precision floating point multiplier > 6. Double precision floating point divider > 7. Double precision floating point square root > > I know there are different algorithms for some of these operations, > some are parallel some are serial, just whichever you know would help. > Rough guesses are all I need. If you want, just take whichever would > be the lease, use that as a baseline of 1.0 for the relative sizes. > Thanks everyone. > > -AKiriwas >Article: 83121
Shreyas Kulkarni schrieb: > hi there, > > i have been working on a PCI 5V DAQ card. there is a surprising fact > that i have observed regarding the motherboard on which i am mounting > the card. it is an old pentium-I 200MHz board containing both PCI and > ISA slots (one of those legacy boards). when i mounted the card and > checked power supplies, i found that 3.3V supply is simply not there. > the PCI spex v2.2 defines 3.3V power supply fingers on the bus. hence i > routed my board accordingly (it contains Spartan2 and platform flash > mem which require 3.3V for Vcco). > > is this a generic case or what? has anybody seen/worked on such boards? > doesnt this board violate PCI standards? > > now i will have to change the board. can anyone tell me what i should > look for on the motherboard to ensure that it has both types of power > supplies supported? > > > TIA, > Shreyas > hi, I had the same problem with an older ASUS P2L97-S, i think with older pci specification the 3.3 V were optional. my board also had an AGP connector beside the PCI slots with 3.3V and I had to make a wiring between the AGP and the PCI Slots. I think all newer board are according to the PCI spex v2.2 and have the 3.3V at the PCI connectorsArticle: 83122
Could anybody confirm that the "Platform Cable USB" works (or not) with ISE 7.1 under Linux (preferably FC3) ? Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 83123
Hi,
i am a newbee to FPGA design and i wanted to know how to add simple
delay in my Spartan 3 XC3S200 FPGA. I have a 16 bit digital signal
which comes from an imaging device(CCD) which may, for example
represent the data on pixel 1. What i want to do is first send the
pixel number to the computer, and then send the 16 bit data for that
pixel to the computer.
The output on the computer may look like something below,
1 - pixel no. 1
1345 - data for pixel 1
2 - pixel no. 2
2431 - data for pixel 2
3
1325
So do i have to send out the pixel number , then have a delay and send
out the data for that pixel. Something like this??
out = pixel;
#100 out = data_in;
Thanks !!!!!!!!
Article: 83124The #sign delay is not synthesizable to the FPGA. But you still can implement a delay in different way. You can use a shift register or use a simple logic and a big counter that will send the input to the output once the counter reach a certain number. Note that in both cases, you must know in advance the speed of the clock before you can write the code to implement an accurate delay. Hendra Amir Intisar wrote: > Hi, > i am a newbee to FPGA design and i wanted to know how to add simple > delay in my Spartan 3 XC3S200 FPGA. I have a 16 bit digital signal > which comes from an imaging device(CCD) which may, for example > represent the data on pixel 1. What i want to do is first send the > pixel number to the computer, and then send the 16 bit data for that > pixel to the computer. > The output on the computer may look like something below, > > 1 - pixel no. 1 > 1345 - data for pixel 1 > > 2 - pixel no. 2 > 2431 - data for pixel 2 > > 3 > 1325 > > So do i have to send out the pixel number , then have a delay and send > out the data for that pixel. Something like this?? > > out = pixel; > #100 out = data_in; > > Thanks !!!!!!!!
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