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Mhhhh... there is a little trouble. This clock must drive an LCD which has a timing fixed between: 1,535508 Mhz and 1,344537 MHz. Do you have other ideas?Article: 80351
Marco wrote: > I have a spartan 3 starter kit board. > > I need to generate a clock of 1,5MHz. > > It has an analog oscillator at 50Mhz. > > What should I do? > > I thought to multiply 50Mhz for 3 then divide for 100, but in what way I can realize that? > > Now, as clock signal I have BUS2IP_CLK, from OPB BUS. > > In what way I can connect to analog oscillator? > > Many Thanks Marco What will you do with this clock? Just drive an output or have internal logic clocked with it? GöranArticle: 80352
could you acheive 100Mbps bandwidth ? junkmail@fastertechnology.com wrote: > ivan wrote: > > Hi, > > > > Did anybody work on OPB_EMAC xilinx core at 100mbps with PPC405.How > > did you develop drivers for that?Please let me know. > > Thanks & Regards, > > Ivan > > I have an Avnet development board with a V2P20 on it. It came with a > reference design that has Linux running on the PPC, and uses the > OBP_EMAC core to talk to a PHY on the development board. The demo > include a simple web sever, and it works. > > The Linux distribution came from www.denx.de and has an old version of > a driver for the Xilinx EMAC core. The driver was written by > MontaVista. > > There is a newer version of the driver available in the bitkeeper > repository for the PPC version of the kernel. Look at > www.klingauf.com/v2p/index.phtml for information on how to get the > kernel, and other good info. > Also check out www.penguinppc.org > > John McCaskillArticle: 80353
I am new to the FPGA and I want to learn by small experiments.
Can some FPGA experts tell me what is the easiest and least expensive way of
getting started ?
What eventually I want to implement (what I'm dreaming) are;
* Communicate with four RS232 devices (115200baud) simultaneously
* Control 16 parallel I/O lines
* Encode/decode multi channel Radio Control signals
http://www.mp.ttu.ee/risto/rc/electronics/radio/signal.htm
http://www.veetail.com/HowRCworks.shtml
http://www.mh.ttu.ee/risto/rc/electronics/pctorc.htm
http://adamone.rchomepage.com/guide1.htm
* Control high speed (5MHz sampling rate, 12-16bit resolution) Analog to
Digital converter to digitise high frequecy signals and being able to
transfer the digitised data to a PC via either USB3 and/or Firewire to
perform FFT
* Decode and count quadrature encoder signals
* Multi channel PID servo controller with PWM and/or analog outputs
Article: 80354
Hello everyone,
I able to use Modelsim mxe3 only as administrator and not as
local user. for mxe2 there were some files to deleted in WINDOWS
directory but such files i don't find for mxe3.
so, what are the changes needed to be made to make it work for all
users.
thanking you all in advance,
Regards,
J.Anil Kumar.
Article: 80355Well, because your required clock is so much slower than your oscillator... Count the 50MHz clock, and every 'n' ticks toggle a T-Flip-Flop. f = 50MHz T = 20ns f = 1.5MHz T = 666.6ns T/2 = 333.3ns counting 17 ticks of the 50Mhz takes 340ns, using this signal to toggle would give a 'clock' of frequency T/2 = 340ns, T = 680ns, f=1.47us Bang in your spec. I don't know your exact application however so this may be a poor way of implementing for you. Ben <Marco> wrote in message news:ee8c67f.1@webx.sUN8CHnE... > Mhhhh... there is a little trouble. > > This clock must drive an LCD which has a timing fixed between: 1,535508 Mhz and 1,344537 MHz. > > Do you have other ideas?Article: 80356
"greenplanet" <greenplanet@hotmail.com> wrote in news:1109908975.615102.295300@l41g2000cwc.googlegroups.com: > Dear all, > > This may sound stupid to ask, but I am very frustrating now as my > deadline is approaching. I want to make use of the VGA generator > example on www.xess.com. How could I write/read data to the specific > address of the SRAM? > I would have to have a SRAM controller that writes and reads data to > the SRAM? How should that be implemented in VHDL? What else do I > need? I am planning to hard code the data to SRAM. Thank you very > much!!! I assume you are actually referring to the SDRAM on the XSA Board and not the internal block SRAMs of the FPGA. The VGA generator design files archive (http://www.xess.com/projects/an-101204-vgagen.zip) already includes an example where the VGA generator is connected to the XESS SDRAM controller so it can display images stored in the SDRAM. You can use the GXSLOAD utility to download images to the SDRAM. And you can use the img2xes utility (http://www.xess.com/downloads/img2xes.zip) to convert commonly-used image files into a format that GXSLOAD can handle. -- ---------------------------------------------------------------- Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 80357
A Beaujean wrote: > > Although this is not directly related to the current SR latches > discussion, let me expose a problem that forced me to define a VHDL > equivalent of the good old 7474 flip-flop made with NAND gates and a > set of KEEP attributes on the signals. > > Although it may be questionable to do so, once you try to synthetize a > flip-flop with such an expression as "If Rising_Edge(Signal_In) Then > ...", where Signal_In is not supposed to be a general clock at all, > the synthesis tool generally reserves a global clock chain and buffer > for just that purpose. > > This may be a real problem if the number of times you want to do that > (because for instance you need to have a very quick reaction on the > rising edge of a signal) gets significant vs the number of available > GCLK nets and buffers. > > Pardon me if I am presently missing a very simple way to tell the tool > "Please do not use one of your GCLK resources", but I am not a very > frequent user of VHDL and had no chance to go to any advanced seminar > of any kind. > > A solution to that problem ? > > Please answer if you are aware of some. Take a look at CLOCK_BUFFER in the constraints guide. You can set the attribute CLOCK_BUFFER to "none" for a signal to prevent automatic insertion of global resources.Article: 80358
Huianx wrote: > I am new to the FPGA and I want to learn by small experiments. > > Can some FPGA experts tell me what is the easiest and least expensive way of > getting started ? > > What eventually I want to implement (what I'm dreaming) are; > * Communicate with four RS232 devices (115200baud) simultaneously > * Control 16 parallel I/O lines > * Encode/decode multi channel Radio Control signals > http://www.mp.ttu.ee/risto/rc/electronics/radio/signal.htm > http://www.veetail.com/HowRCworks.shtml > http://www.mh.ttu.ee/risto/rc/electronics/pctorc.htm > http://adamone.rchomepage.com/guide1.htm > * Control high speed (5MHz sampling rate, 12-16bit resolution) Analog to > Digital converter to digitise high frequecy signals and being able to > transfer the digitised data to a PC via either USB3 and/or Firewire to > perform FFT > * Decode and count quadrature encoder signals > * Multi channel PID servo controller with PWM and/or analog outputs At least the far aims are not too small. First you should decide whether you also wanted to have a CPU inside the FPGA. To start with I suggest to have one outside. That makes it much easier in terms of getting used to a new development environment and debugging the software. The usual way to get started is to get an evaluation kit of an FPGA from a standard manufacturer. They usually have a free development software. In case the CPU inside the FPGA should also be covered, then the Stratix or Cyclone NIOS kit from Altera comes to my mind. This goes for 495 $ or so with a one year license of the software. Other manufacturers probably have a similar offer. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 80359
After adding Ethernet core (full) to our ML310 design, (with an Intel development PHY board connected through spare GPIO pins on PM1), we are seeing intermittent sysACE / Compact Flash lockups in the vxWorks boot. Through many toils and snares, we have determined that when this lockup occurs, the actual hang is occurring on the line: while (XSysAce_Lock(AcePtr, XFALSE) != XST_SUCCESS); in the xsysaceblkadapter.c file in the function: "XSysAceBlkAdapter_Init(Xuint16 DeviceId, unsigned MaxPartitions)." It seems that disconnecting our Ethernet cable during the boot-up, makes the problem disappear--- and I have no earthly idea how Ethernet traffic/interrupts can affect sysACE controller. I'm guessing a timing/FPGA build issue, but have no clue where to start on finding/isolating/fixing the issue--if indeed it is in the FPGA place/route/timing arena. The comments in the xsys driver code, are puzzling to me. In particular, it says "This function blocks waiting on a lock from the System ACE controller. If a JTAG configuration is in process, this function will block until the configuration process is done." and in the comments for the XSysAce_Lock() function: "If the user requests a forced lock, the JTAG configuration controller will be put into a reset state in case it currently has a lock on the CompactFlash. This effectively aborts any operation the configuration controller had in progress and makes the configuration controller restart its process the next time it is able to get a lock. A lock must be granted to the user before attempting to read or write the CompactFlash device. Force is a boolean value that, when set to XTRUE, will force the MPU lock to occur in the System ACE. When set to XFALSE, the lock is requested and the device arbitrates between the MPU request and JTAG requests. Forcing the MPU lock resets the configuration controller, thus aborting any configuration operations in progress. return XST_SUCCESS if the lock was granted, or XST_DEVICE_BUSY if the lock was not granted because the configuration controller currently has access to the CompactFlash. If the lock is not granted to the MPU immediately, this function removes its request for a lock so that a lock is not later granted at a time when the application is (a) not ready for the lock, or (b) cannot be informed asynchronously about the granted lock since there is no such interrupt event." Now this leads me to the following questions: 1) why isn't the initialize function forcing a lock? Would something bad happen if it did? 2) I don't understand what will happen in the lock routine if force is true when it 'releases the reset'. Does this mean it'll try to re-configure the FPGA? 3) Should I put a timer/timeout around the while statement and if it times out, call it again with Force=TRUE? Has anyone else encountered problems like this? I admit is very peculiar and troubling that adding an Ethernet core is impacting the sysACE at all. Thanks, PaulArticle: 80360
Falk Brunner wrote: > > I dont think that Xilinx does intentionally slow down its IOs > by adding capacitance. I guess the control slew rate a little > bit more clever (using intentionally slower transistors) > I didn't claim that the I/O capacitance was the only thing slowing the LVCMOS outputs down. What I was attempting to point out was that high FPGA I/O capacitance can limit the performance for both inputs and outputs for high edge rate I/O standards. If driving a high-C FPGA input from a fast LVDS or ECL driver, proper analysis and verification needs to be undertaken to assess the impact of the FPGA Cin, which is much larger than you'd find in a dedicated ECL or LVDS receiver. ( Particularly in a multidrop situation, which is created whenever you need to probe the lines in system for verification purposes. ) For a demonstration of how high C affects a fast output standard, look at figure 26 of XAPP-622: in order to forward a 622 MHz clock, an AC coupling kludge is needed because the V2 LVDS outputs don't swing far enough to properly cross at 622 MHz ( 1.2 Gbps ). BrianArticle: 80361
Marco wrote:
> I need to perform an operation to calculate ram address.
Consider writing a synchronous process.
> I have created a RAM with core generator, and added to my project.
Consider inferring the ram from a code template.
>
> Using this command:
>
> address <= alfa + beta * gamma;
Consider using a counter or shifter to test your ram.
> When I make synthesis I receive an error message.
Consider running a simulation first.
> address what kind of type shuold be?
Consider unsigned.
-- Mike Treseler
Article: 80362
Marco wrote:
> signal abc std_logic_vector(3 downto 0);
> after, when I write:
> abc <= abc + 1;
> if abc was 000, now which is?
> 001 or 100 ????
"0000" until the end of the process
"0001" thereafter
assuming you are using a library that
covers "+" for std_logic_vector.
Run a simulation and see for yourself.
Consider using unsigned type and ieee.numeric_std
for the "+" operation.
-- Mike Treseler
Article: 80363
A Beaujean wrote:
> Although it may be questionable to do so, once you try to synthetize a
> flip-flop with such an expression as "If Rising_Edge(Signal_In) Then
> ...", where Signal_In is not supposed to be a general clock at all,
> the synthesis tool generally reserves a global clock chain and buffer
> for just that purpose.
> This may be a real problem if the number of times you want to do that
> (because for instance you need to have a very quick reaction on the
> rising edge of a signal) gets significant vs the number of available
> GCLK nets and buffers.
> A solution to that problem ?
Consider a synchronous design.
That uses just one GCLK net and provides
quick delivery to every flop in the design.
-- Mike Treseler
Article: 80364Marco <marcotoschi@email.it> wrote in message news:<ee8c67b.-1@webx.sUN8CHnE>... > I have a doubt. > > when I create a signal like this: > > signal abc std_logic_vector(3 downto 0); > > after, when I write: > > abc <= abc + 1; > > if abc was 000, now which is? > > 001 or 100 ???? > > Many Thanks Marco First, let me correct a small error. What you write would rather be with std_logic_vector(2 downto 0); Then, the result is most certainly 001. Done it hundreds of time. Check it with a simulator.Article: 80365
Brian, Yes, it was not designed for 622 Mbs (Virtex 2). The "kludge" as you call it, is not required for V4. Same pin C. So, yet again, pin C is not involved. Besides, if I have 2X the dV/dt, guess what happens when I drive 1/2 the pin C? Yes, math still works: I get exactly the same di/dt, which leads to the same reflection for both cases. As long as the receiver is terminated inside the chip, and the transmitter is also terminated (ie the LVDS standard), small reflections at the receiver are absobred by the transmitter, and SI is fine. In fact, simualting 1/2 C with 2X rise and fall times shows exactly the same reflections and issues as C and 1X rise and fall times ..... Non issue. Austin Brian Davis wrote: > Falk Brunner wrote: > >>I dont think that Xilinx does intentionally slow down its IOs >>by adding capacitance. I guess the control slew rate a little >>bit more clever (using intentionally slower transistors) >> > > I didn't claim that the I/O capacitance was the only thing > slowing the LVCMOS outputs down. > > What I was attempting to point out was that high FPGA > I/O capacitance can limit the performance for both inputs > and outputs for high edge rate I/O standards. > > If driving a high-C FPGA input from a fast LVDS or ECL > driver, proper analysis and verification needs to be undertaken > to assess the impact of the FPGA Cin, which is much larger than > you'd find in a dedicated ECL or LVDS receiver. > > ( Particularly in a multidrop situation, which is created whenever > you need to probe the lines in system for verification purposes. ) > > For a demonstration of how high C affects a fast output standard, > look at figure 26 of XAPP-622: in order to forward a 622 MHz clock, > an AC coupling kludge is needed because the V2 LVDS outputs don't > swing far enough to properly cross at 622 MHz ( 1.2 Gbps ). > > Brian >Article: 80366
What about Altium's Nexar (http://www.altium.com/nexar/evaluation/?vc=1612) ?Article: 80367
Thanks...Well, right now...everything is working with the whole PLL function being done inside the FPGA itself.....but then there is a jitter in the output.....and am not able to figure out the reason....Article: 80368
Take a look here http://www.fpga4fun.com/SerialInterface.html http://www.fpga4fun.com/RCServos.html http://www.fpga4fun.com/digitalscope.html http://www.fpga4fun.com/QuadratureDecoder.html Good luck! JeanArticle: 80369
You should start with an evaluation board for one of the low-cost FPGA lines. Xilinx offers the Spartan-3 family, with evaluation boards from Xilinx or the distributors. Many of them are below $ 150. For your internal microprocessor I recommend the Xilinx PicoBlaze. It is free (!), and it is simple, and allows you to do the control jobs you mentioned. No opeating system, no C compiler, but direct access to the hardware. It uses about 200 LUTs/flip-flops plus a BlockRAM. Real tiny, and real popular. Google it... Peter Alfke, Xilinx ApplicationsArticle: 80370
ivan wrote: > could you acheive 100Mbps bandwidth ? Using the Avnet board with the Avnet bitfile and Linux, the sustained bandwidth that I was able to achieve was less than 2MB/s. In addition to using the OPB_EMAC core instead of the PLB_EMAC core, the Avnet bitfile also runs Linux out of external SDRAM memory connected via the OPB bus. So I don't know which is the bottleneck, but I would guess the memory is probably the bigger factor. I will probably be doing some tests soon to try to find the source of the problem. > junkmail@fastertechnology.com wrote: > >>ivan wrote: >> >>>Hi, >>> >>>Did anybody work on OPB_EMAC xilinx core at 100mbps with PPC405.How >>>did you develop drivers for that?Please let me know. >>>Thanks & Regards, >>>Ivan >> >>I have an Avnet development board with a V2P20 on it. It came with a >>reference design that has Linux running on the PPC, and uses the >>OBP_EMAC core to talk to a PHY on the development board. The demo >>include a simple web sever, and it works. >> >>The Linux distribution came from www.denx.de and has an old version > > of > >>a driver for the Xilinx EMAC core. The driver was written by >>MontaVista. >> >>There is a newer version of the driver available in the bitkeeper >>repository for the PPC version of the kernel. Look at >>www.klingauf.com/v2p/index.phtml for information on how to get the >>kernel, and other good info. >>Also check out www.penguinppc.org >> >>John McCaskill > > -- My real email is akamail.com@dclark (or something like that).Article: 80371
Bob wrote: (snip) > His description of how most of the intra-package crosstalk is due to > magnetic coupling, and not merely the voltage deltas caused by di/dt through > a particular L nor capacitive coupling due to dv/dt, was quite a surprise. > The demonstration of the relative directions of the voltage swings (between > aggressor and victim) made this very clear and convincing. Well, L di/dt is magnetic, both self inductance and mutual inductance depend on the geometry of the system. -- glenArticle: 80372
Use the DCM to multiply your 50MHz to 150MHz and divide is a simple way. DCMs will also fractions but watch the input and output frequency limits. There is a tool in the ISE toolset "Architecture Wizard" that can help you define the DCM with little pain and will tell you the limits for what you want to do. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Marco" <marcotoschi@email.it> wrote in message news:ee8c67f.-1@webx.sUN8CHnE... > I have a spartan 3 starter kit board. > > I need to generate a clock of 1,5MHz. > > It has an analog oscillator at 50Mhz. > > What should I do? > > I thought to multiply 50Mhz for 3 then divide for 100, but in what way I can realize that? > > Now, as clock signal I have BUS2IP_CLK, from OPB BUS. > > In what way I can connect to analog oscillator? > > Many Thanks MarcoArticle: 80373
Eric Smith wrote: > hmurray@suespammers.org (Hal Murray) writes: >>I think older non-LDO type linear regulators are easier to work with. >>But they often don't go down to 1.2V. > Even LDOs that go to 1.2V are fairly uncommon. But 1.25V are extremly common. They call it "adjustable" ;-) Kolja SulimmaArticle: 80374
You may need to add libraries to your VHDL file. Either IEEE.STD_LOGIC_UNSIGNED or IEEE.STD_LOGIC_ARITH has the correct function for "+". I think multiple should be there too. Alternatively convert to integer type, do the necessary functions, and then convert back to std_logic. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk Marco" <marcotoschi@email.it> wrote in message news:ee8c68d.-1@webx.sUN8CHnE... > I need to perform an operation to calculate ram address. > > I have created a RAM with core generator, and added to my project. > > Using this command: > > address <= alfa + beta * gamma; > > When I make synthesis I receive an error message. > > address what kind of type shuold be? > > I have declared it as: std_logic vector. > > Is it correct? > > Many Thanks Marco
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