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First, So it's possible but no if you planning on just using plain C since the startup code (crt) that gcc uses can't handle this. A new startup sequence is needed. The startup code would read the constant and then save it at different addresses depending on the constant value (addr = base_addr + constant value). The constant value would also create different stack pointer addresses (r1 init value) so the MB doesn't use the same stack space. The other data pointers needs also to be separate. The final part of the startup sequence would jump to different PC addresses depending on the constant value. Göran TheMightyShaman wrote: > Göran Bilski <goran.bilski@xilinx.com> wrote in message news:<cv294c$bmv3@cliff.xsj.xilinx.com>... > >>Since both processors starts at address 0, they will start to execute the same >>initialization code. >>You need to use a FSL port with different constant signals for each MicroBlaze. >>The boot code would then read the FSL port to know which MicroBlaze it's. >>Using this it would jump to the right code section. > > > Dear Goran, sorry for the disturb, another question: how can you read > and differentiate the constant signals if when executing a reading > with mb_interface.h primitives on fsl the value on the FSL will be put > in a variable that is shader if you are working with a shared data > memory? The first processor that read will put its number in it and so > you can't jump to the proper code... > > Any suggestion? > > Thank you very much!Article: 80076
Hello Fayette, will be supported in EDK7.1. Coming next daysArticle: 80077
What's the party line on using SR's on Xilinx FPGAs (ie. two cross-coupled NAND gates, or some equivalent representation?) Can the timing analyser cope? The dev guide has a few hits on the words 'asynchronous' and 'feedback', but none of them are relevant. Thanks - RickArticle: 80078
Hi Goran, thanks for the clear and complete suggestions. It seems an interesting procedure but also not so easy to implement, I'll give it a try and see if I obtain results. Thank you very much and sorry for the disturb!Article: 80079
Richard Thompson wrote: > What's the party line on using SR's on Xilinx FPGAs (ie. two > cross-coupled NAND gates, or some equivalent representation?) Can the > timing analyser cope? > > The dev guide has a few hits on the words 'asynchronous' and > 'feedback', but none of them are relevant. > > Thanks - > > Rick Generally speaking you're asking for trouble when you try to make asynchronous sequential circuits using LUTs. You just can't force the tools to make the coverage terms for state transition. In most Xilinx parts you can use actual flip-flops to get SR's (see FDCP in the libraries guide).Article: 80080
greenplanet wrote: > Dear all, > > Thank you very much for your valuable response. For those who may want > to know, my thing is one of the slaves, and it has to communicate with > the master who has to talk to many other slaves (components that I > don't know what they are). I have to build the interface such that my > thing knows when and what to respond when the master talks. I hope I > could come out with something that works. =) I2C slaves can be very simple. Things to consider include your address, which must be different than other devices on the same bus. i.e. you need to know what the other slaves on the bus are so you can pick a "safe" address. As I recall Philips has a recommendation for classes of devices and ranges of addresses, but this is not part of the I2C bus specification. Another thing to consider is addressing mode, which is usually 7-bit for small devices but can be 10-bit. Using 10-bit addressing slows down your access. Most I2C slave devices have multiple internal registers accessed using "subaddress" protocol. Take a look at a datasheet for the 24LC02 from Microchip to see how this works. When I make I2C slaves in FPGA's I usually use this protocol and attach a small RAM to allow readback of register values. This can reduce the overall device usage over multiplexing the individual registers, but you'll still need a mux to deal with read-only registers or registers that can change value from some other path than I2C. Hope this helps, GaborArticle: 80081
No problem. I had to think a little on how to solve it. It's not a normal system. I wished I had time to try it out. My view of multiprocessing is more of distributed processing where each processor has it's own memory and the communication between are done with message passing using FSL. Very much like to old transputer concept. Göran Bilski TheMightyShaman wrote: > Hi Goran, thanks for the clear and complete suggestions. It seems an interesting procedure but also not so easy to implement, I'll give it a try and see if I obtain results. > > Thank you very much and sorry for the disturb!Article: 80082
Hi, I understand what you mean. However, I don't think it works in my case because I have a loop (it is a MAC). In order to start the next calculation, I need an answer to the previous one. I guess the only solution is faster logic. I thought that a virtex4 would be able to give us those kind of calculation speed... DaveArticle: 80083
On 1 Mar 2005 06:16:36 -0800, "Gabor" <gabor@alacron.com> wrote: >Generally speaking you're asking for trouble when you try to >make asynchronous sequential circuits using LUTs. You just >can't force the tools to make the coverage terms for state >transition. In most Xilinx parts you can use actual flip-flops >to get SR's (see FDCP in the libraries guide). Luckily, not an issue here - the standard cross-coupled NAND is already hazard-free (unless the mapper decides to reimplement it, which seems unlikely). My main concern is trce - do you know if the timing analyser will trace through the the S/R ports on an FDCP? I can't see anything obvious in the documentation. Presumably it won't be able to handle explicit cross-coupled gates, though. RickArticle: 80084
Hi Nigel, Thanks for your help. When is the Aurora module going to be available for the V4 FX series? I know that even V4 MGBT user manual has not been released yet... /MikhailArticle: 80085
Thanks Duane. /MikhailArticle: 80086
Not quite sure, Peter and I, as part of our job, read this newsgroup. We are tasked with clarifying issues, answering questions, and just being good engineering ambassadors. Xilinx also has a few others who have been encouraged to follow this group: e.g. Eric for PCI, Goran for MicroBlaze(tm), etc. Experts and Principals are encouraged to answer questions, and be helpful when they can. They are also asked to contact Peter if they have any questions about posting an answer. I know that Altera also has official responders to this group, similar to what we do, and has their own procedures. Yes, it is just good business practice to help customers. Austin *Note: Of course, the main reason for posting is that sitting the trot is uncomfortable.Article: 80087
"Camelot" <camelot@hightech-td.com> wrote in message news:10f20c13.0502251201.6ea63728@posting.google.com... > Hello to anyone! > > I'm designing SD host controller core and I have some question to > someone who known about it. I've made SD controller with 1 bit data > line and I want to make 4 bit data line interface with SD, but all > the same after sending to SD Card ACMD6, data received by 1 wire. > > I'm doing next: > > (wait for 90 clock) -> CMD0 -> CMD55 -> ACMD41 (with repeate) -> CMD2 > -> CMD3 -> -> CMD7 (with RCA) -> ACMD6 (4 bit) -> CMD17 > > One date line mode does work but 4 data line doesn't work. > > Any ideas? > > Thanks! What doesn't work? Do you get any data at all? One problem I had was with CRCs for 4 bit mode. CRC's are computed on individual data lines, I made the mistake of using the final 8 bytes of data as the CRC's, but the bits are more like individual serial lines with individual 16 bit CRCS at the end of the data. RufusArticle: 80088
Hi, I read a lot of stuffs on JTAG and SVF file, but I still can't figure out how to read back multiple memory spaces or multiple registers via JTAG. I used BSCAN_SPARTAN3 and USER1 Register, but that only allows you to read back one register. I need to read back at least 10 registers or memory spaces via JTAG. Is it possible to do this at all? Thanks, ALArticle: 80089
Hi..I am trying to load a rbt file into a AMD flash onboard. The vendor suggests us to generate the hex file of the rbt file and load it in the flash. In an example it was shown that the bits 0xAA995566 was loaded in this order 0x66AA9955. I am not able to understand why the LSB(yte) appeared as MSB(yte). Did anyone see this swapping before? Any suggestions?? (Unfortunately, we dont have a provision of loading any other formats using the tool support that we have.) Thank you!Article: 80090
Hi, So I edited the text version of the SVF file, then how do u download to the device though??? Thanks, ALArticle: 80091
Thanks for your responses. I guess one or more of the following assumptions that I am making about single port RAMs must be wrong: 1. single port RAMs are separate entities from common CLBs 2. single port RAMs contain all the necesary logic to implement read/write of 1 bit to any of 16 addresses. 3. synplify uses the FMAPs quantity to report only on common CLB LUTs. This why I can understand that Synplify says that 16 single port RAMs are needed. I can also understand that 1 LUT is being used for wirte enable. But, based on these assumptions, I still can't understand the extra 16 LUTs. Which of my assumptions are incorrect? Thanks again, RafaelArticle: 80092
gretzteam wrote: > I understand what you mean. However, I don't think it works in my case > because I have a loop (it is a MAC). In order to start the next > calculation, I need an answer to the previous one. I guess the only > solution is faster logic. I thought that a virtex4 would be able to > give us those kind of calculation speed... Unless the result from the accumulator goes as an input to the multiplier, it should pipeline just fine. Using the built in multipliers, it should be two or three stages. The answers will come out, one per clock cycle, two or three clocks later. -- glenArticle: 80093
> > www.perso.ens-lyon.fr/jeremie.detrey/FPLibrary/ > > i tried the routines in xilnx ise + modelsim...it worked fine. The link seems to be broken. MartinArticle: 80094
"Rich Webb" <bbew.ar@mapson.nozirev.ten> schrieb im Newsbeitrag news:dsg721l4jufpmbcni9v6874jmm211kr3qo@4ax.com... > >The microcontroller has read, write and address strobe signals. The problem > >is that the bus is asynchronous, which means that the FPGA might sample the > >signals when they are not in a defined logic state. This implies > >meta-stability problems if I remember my classes properly. What are the > >basic guidelines to handle such problems ? We handle this situation in this way. NO oversampling. Since there is no need to do so. A read acces to a register inside the FPGA is plain combinatorical, no problem here. A write access to a register is defacto a clocked process, so we use WR as a clock (on a global clock net) to load data into FPGA registers. For an address latch its similar, use ALE to clock the address into the latch/register. Here you dont need to wast a global clock net, local routing (low skew lines) do fine, since the latch is small (just a handfull of flipflops) > The FPGA will do many things in parallel. One of the things it will do > is a latch that's clocked by the appropriate edge from the AVR that is > independent of any logic that's changed by the FPGA's clock. After the > data is latched, it will set a "new data available" flag that's handled > by the FPGA's clocked logic. The right way to go. Dont forget to synchronize the flag using the classic 1/2 flipflop synchronizer. Regards FalkArticle: 80095
Thanks for all the benchmaks! Very interessting information! If I interpret the data correctly, two CPU result in the same simulation time, so they are of no benefit? That's a pity! BR, Chris Kim Enkovaara wrote: > Jason Zheng wrote: > >> 3. You are comparing state-of-the-art AMD workstations with mediocre >> Intel servers. It's like comparing oranges with apples. > > > I have some measurements with more current Xeon processors. Unfortunately > I had only one not so state of the art Opteron to measure. > > These results were published by me in one local Mentor Graphics conference > (these are only small part of the numbers). The simulations are done with > Modelsim for a ~8Mgate chip (+all memories). The numbers are simulation > time > in seconds. > > > RTL One CPU active > Sun V880 UIII/900 3531 > P4 Xeon 2.2/512k 2224 > P4 Xeon 2.4/512k 2087 > P4 Xeon 2.8/512k 1928 > P4 Xeon 3.06/512k 1634 > P4 Xeon 3.4EMT (32b) 1239 > AMD Opteron 848(32b) 1584 > > RTL Both CPUs active > Sun V880 UIII/900 3520 > P4 Xeon 2.2 2540 > P4 Xeon 2.4 2680 > P4 Xeon 2.8 2650 > P4 Xeon 3.06 2120 > P4 Xeon 3.4EMT (32bit) 1450 > AMD Opteron 848(32b) 1587 > > One thing that amazes me is that in Xeons even with RTL simulation the > performance > degrades very guickly. I guess with 4 processors Xeons degrade very > badly. In > Opterons there was no degradation to be seen. > > For the gate level simulations the results are almost identical, altough > the dataset > is 15-20x larger and simulation times for the same case are longer. Also > if 64b mode > was used Opteron became faster and Xeon EMT was little slower (very > small differences > compared to 32b mode tough). > > > --KimArticle: 80096
Richard Thompson wrote:
> Luckily, not an issue here - the standard cross-coupled NAND is
> already hazard-free (unless the mapper decides to reimplement it,
> which seems unlikely).
Hazard-free as long as the set and reset pulses
are well formed and far enough apart in time.
It's not difficult to make an oscillation
burst otherwise.
-- Mike Treseler
Article: 80097
Wow! You use REAL Latches. I never dared to used them. If it works
stable, my are sure of my deep repect.
I would have doubled (or quadroupled) the 24 MHz clock and synchonized
the write signal.
Cheers,
Chris
Pablo Bleyer Kocik wrote:
> Laurent Pinchart wrote:
>
>>As the bus is asynchronous, I suppose I'll have to over-sample the
>
> signals.
>
>>Could anyone direct me to some documentation about asynchronous bus
>>interfaces for FPGAs ? The FPGA main clock runs at 24MHz, and I'd
>
> like to
>
>>know if this will be enough (the clock can be doubled using a DLL if
>>needed).
>>
>>Thanks in advance for your help.
>>
>>Laurent Pinchart
>
>
> This is a latched interface example that worked for me using Xilinx
> FPGAs (Spartan II). Your design must be *extremely* careful about the
> ALE, nRD and nWR signals (both in your board and in the FPGA - perhaps
> buffering them adequately). I also registered carefully the internal
> outputs of my design that interacted with the interface.
>
> ---8<---
> /*
> AVR bus interface
>
> This module adapts the external AVR interface to the internal bus.
> It latches the incoming address and generates the write and reset
> signals.
> */
>
> /*
> +----+
> AH -->| |--> A
> AD <->| |--> DI
> ALE -->| |<-- DO
> nRD -->| |--> WE
> nWR -->| |--> RST
> CLK -->|> |
> +----+
>
> A: {AH, AD_address}
> DI[7:0]: AD_data input
> DO[7:0]: output to AD data
> WE: write strobe
> RST: reset (both nRD and nWR asserted)
> */
>
> module avr(
> CLK,
> AH, AD, ALE, nRD, nWR,
> A, DI, DO, WE, RST
> );
> parameter AH_size = 0;
>
> input CLK; // not used in this implementation
> input ALE, nRD, nWR;
> input [((AH_size>0) ? AH_size-1 : 0):0] AH; // if AH_size == 0, AH is
> unused
> inout [7:0] AD;
>
> output WE, RST;
> output [AH_size+7:0] A;
> output reg [7:0] DI;
> input [7:0] DO;
>
> reg [7:0] AL; // Address-low latch
>
> assign A = (AH_size>0) ? {AH, AL} : AL; // Full address
>
> wire nALE = ~ALE; // needed for XST to synthesize a latch for AL
> wire RD = !nRD && nWR;
> wire WR = !nWR && nRD;
>
> assign WE = !ALE && WR;
> assign AD = (!ALE && RD) ? DO : 'hz; // Memory read output drive
> control
>
> assign RST = !nRD && !nWR; // Reset signal generated by asserting nRD
> and nWR simultaneously
>
> always @(AD, nALE) if (!nALE) AL <= AD; // Address-low latch from AD
> bus
> always @(AD, WE) if (WE) DI <= AD;
>
> endmodule
> --->8---
>
> Although the Atmega128 datasheet states that the interface is
> asynchronous since there may be a skew between the external and
> internal clocks, I have used it successfully in a synchronous fashion
> feeding XTAL2 to a buffer (CKOPT set accordingly) and then to a FPGA
> clock pin. However, I did not test this setting extensively so I can't
> recommend it (read the quote below).
>
> Regards.
>
> --
> PabloBleyerKocik /
> pbleyer /"Ignorance simplifies ANY problem."
> @embedded.cl / - R. Lucke
>
Article: 80098..it doesn' work.. :-( do I have to put a particular setting in settings -> user libraries ? I' ve put (as adviced by the "dad" of the packages downloaded)the packages in the folder ieee and then I've already add them in the setting "file" in order (like a "Matrioska"!).. I don't know what to do now..however thank you very much for the help Cecilia <DerekSimmons@FrontierNet.net> ha scritto nel messaggio news:1109618033.481153.25270@g14g2000cwa.googlegroups.com... > It sounds like you are having the same frustrations I had when I first > started out. If I remember right it has do with the order the files are > compiled. > > If you go into QuartusII, open your project, goto the assignments menu, > select the settings menu item the settings dialog window should open. >>From the list on the left hand side select files. You should see a list > of your source files. > > First thing you should check for is if all your files are there and if > they are not then you need to add them. Second are they in the right > order? Many compiles will perform a pass to build a dependencies list. > Quartus doesn't, it expects you to put your files in the order they > need to be built. > > Hope this helps. > > Derek >Article: 80099
I've found it anyway...thank you! but with the Quartus II I've many problems to use this package... Cecilia Annovi "Martin Schoeberl" <martin.schoeberl@chello.at> ha scritto nel messaggio news:xJ1Vd.72929$2e4.70358@news.chello.at... > > >> www.perso.ens-lyon.fr/jeremie.detrey/FPLibrary/ >> >> i tried the routines in xilnx ise + modelsim...it worked fine. > > The link seems to be broken. > > Martin >
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Compare FPGA features and resources
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