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Messages from 79575

Article: 79575
Subject: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40 !
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Mon, 21 Feb 2005 10:27:18 GMT
Links: << >>  << T >>  << A >>
> finally I can announce it:
>
> http://www.eubus.net/hydraXC
>
> Reconfigurable "dream" - small and fully reconfigurable computing module.
>
> Designed to be as reconfigurable as possible, eg all of its
> intelligence is loaded at the boot time. The smart system
> management controller allows safe update of the OS image as
> well as the FPGA bitstream over any supported communication
> channel (LAN or serial or other). Of course the new hardware
> and OS can simply be copied to the removable media (miniSD)
> card, no JTAG cable (or any cable) required.
>

Hi Antti,

looks good. So I can now stop building my JopStick as your board
contains everthing (and more) what I need ;-)
However, for my application it's a little bit pricy.
A few questions: About USB and Ethernet: Are there only the PHYs
on the board and you have to implement it in the FPGA?
I can see only one connector - Is this USB or RJ45?

A schematic would be nice to get those questions answered. And
a picture from the back side.

Good work would be interesting to get JOP running on it,
Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/



Article: 79576
Subject: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40 !
From: "Antti Lukats" <antti@openchip.org>
Date: Mon, 21 Feb 2005 11:28:26 +0100
Links: << >>  << T >>  << A >>

"Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag
news:aIiSd.62024$2e4.11649@news.chello.at...
> > finally I can announce it:
> >
> > http://www.eubus.net/hydraXC
> >
> > Reconfigurable "dream" - small and fully reconfigurable computing
module.
> >
> > Designed to be as reconfigurable as possible, eg all of its
> > intelligence is loaded at the boot time. The smart system
> > management controller allows safe update of the OS image as
> > well as the FPGA bitstream over any supported communication
> > channel (LAN or serial or other). Of course the new hardware
> > and OS can simply be copied to the removable media (miniSD)
> > card, no JTAG cable (or any cable) required.
> >
>
> Hi Antti,
>
> looks good. So I can now stop building my JopStick as your board
> contains everthing (and more) what I need ;-)
> However, for my application it's a little bit pricy.
> A few questions: About USB and Ethernet: Are there only the PHYs
> on the board and you have to implement it in the FPGA?
> I can see only one connector - Is this USB or RJ45?
>
> A schematic would be nice to get those questions answered. And
> a picture from the back side.
>
> Good work would be interesting to get JOP running on it,
> Martin
> ----------------------------------------------
> JOP - a Java Processor core for FPGAs:
> http://www.jopdesign.com/

Hi Martin!

please dont  stop designing the JOPstick
- as you said different price categories and
the world is big enough for all of us :)

the connector on board is OTG mini AB
10/100 LAN requires external RJ45 with magnetics.

Antti

















Article: 79577
Subject: Re: does anyone have a c compiler for the picoblaze
From: hmurray@suespammers.org (Hal Murray)
Date: Mon, 21 Feb 2005 05:04:58 -0600
Links: << >>  << T >>  << A >>
>The problem with a C compiler for a picoblaze is its too small to be
>seriously useful.  The overhead in a complier is too large for such a tiny
>processor.

There are c compilers for PIC/Microchip and AVR/Atmel.
I think there is a gnu toolchain as well as one from
the manufacturers.

Sometimes you need assembler, say to make something fit
or so you can count cycles to get timings exactly right.

Other times, you have plenty of CPU cycles and enough memory
for the code.  Why not use c?  You don't suddenly get to use
printf.  You just write the same sort of code you were writing
in assembler in c.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 79578
Subject: Hardcopy Vs ASIC
From: digari@dacafe.com
Date: 21 Feb 2005 03:19:02 -0800
Links: << >>  << T >>  << A >>
I was going through the hard copy product from altera. Methodology
seems really promising. I just wonder where hard copy products stands
as compare to ASIC wrt performance, power, yield & Time to market


Article: 79579
Subject: Re: Is Altera Cyclone a good choice ?
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Mon, 21 Feb 2005 12:51:57 +0100
Links: << >>  << T >>  << A >>
"Michael Polovykh" <kefir@rissa.ru> writes:

> So you have a fridge. Put Cyclone into it during PLL work for 30minutes :)
> And tell us about this experiment - we are interested in it too :)

I dubt his fridge will go as low as -20 C.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 79580
Subject: Re: Is Altera Cyclone a good choice ?
From: "Michael Polovykh" <kefir@rissa.ru>
Date: Mon, 21 Feb 2005 16:03:02 +0300
Links: << >>  << T >>  << A >>

"Alex Freed" <alexf@mirrow.com> wrote in message 
news:RrydnSnopcJE4YXfRVn-hw@comcast.com...
>I have heared roumors that the PLL in Cyclone doesn't work below -20C if 
>the
> output frequency is higher than the input. There is some fine print in the
> datasheet to that effect.
>
> Now I have no way of knowing if that is true or not - I live in California
> :))
So you have a fridge. Put Cyclone into it during PLL work for 30minutes :)
And tell us about this experiment - we are interested in it too :)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
>
> "Alessandro Strazzero" <alessandro.strazzero@virgilio.it> wrote in message
> news:391fed46.0502180459.5ad267fb@posting.google.com...
>> Dear everybody,
>>
>> the goal of my post is to collect your opinions about the use of Altera
> Cyclone
>> devices in a rugged environment. I have to design a board which should
> control
>> a chopper based on GTOs. The environment is a railway vehicle and the
> following
>> are the conditions I have to consider:
>>
>> - extreme temperature range (-40C to +85C)
>> - strong mechanical vibrations
>> - long life duration (> 25 years)
>> - high degree of reliability
>> - very low frequency of maintenance
>>
>> From the point of view of the design I think Altera Cyclone is the best
> choise
>> for this kind of project beacuse its high flexibility. But I have some
> doubts
>> about its functionality in a rugged environment like above.
>>
>> Did you experience the use of Altera Cyclone in a rugged environment ?
>> What are your opinions about my choise ?
>>
>> Best Regards
>>
>> /Alessandro Strazzero
>
> 



Article: 79581
Subject: Re: Antti Lukats: all my past live projects to be published...
From: "Marc Randolph" <mrand@my-deja.com>
Date: 21 Feb 2005 05:37:45 -0800
Links: << >>  << T >>  << A >>
newman5382 wrote:
> >
> > This is probably the price to pay for such a cheap tool, so I
should not
> > really complain. Synplify will allow you to use inouts in sub
modules, but
> > it costs much more than XST.
>
> There is a school of thought that all off chip IO should be
> inferred/instantiated at the top level, and not in sub-modules.
>
> -Newman

Is there a good reason for this school of thought?

Using that concept, when I go to take that top level and create a 4x
version of it, I can't just create a new top level with a generate
statement.  Now I have to go edit a completely working design and
convert all the inouts to seperate in's and out's.  And if that
original block is still being used in the original design, I now have
two different versions of the exact same thing that I have to maintain.

Have fun,

   Marc


Article: 79582
Subject: cyclone's pll
From: GL <a@b.c>
Date: Mon, 21 Feb 2005 14:56:16 +0100
Links: << >>  << T >>  << A >>
Hi all,
I'm using a cyclone EP1C6 Q240 and want to instanciate a pll, but using 
the PLL2 (input are CLK2 and CLK3). My  problem is that with the design 
assistant, i can create a macro-function called altpll, but i can't 
choose the input i want (clk2, on pin 153 of EP1C6Q240 ).

how should i do ?

regards,

-- 
Ceci est une signature automatique de MesNews.
Site : http://www.mesnews.net


Article: 79583
Subject: Re: NIOS2 toolchain rebuild...
From: Jedi <me@aol.com>
Date: Mon, 21 Feb 2005 14:00:34 GMT
Links: << >>  << T >>  << A >>
Jon Beniston wrote:
> Jedi <me@aol.com> wrote in message news:<hgMMd.1754$zk.836@read3.inet.fi>...
> 
>>Anybody has an idea why the NIOSII 1.1 toolchain build fails
>>on Linux/BSD systems with:
>>
>>*** ld does not support target nios2-elf
>>*** see ld/configure.tgt for supported targets
>>make: *** [configure-ld] Error 1
>>
>>Somehow it looses "nios2-unknown-elf"...
>>
>>
>>It builds fine on Win2k under Cygwin...
> 
> 
> Have you used the same value for $prefix for both binutils and gcc? Is
> $prefix/bin in your path?
> 

Of course (o;

And building binutils doesn't require prefix/bin at all in this stage (o;


rick

Article: 79584
Subject: Re: Antti Lukats: all my past live projects to be published...
From: Kim Enkovaara <kim.enkovaara@tellabs.com>
Date: Mon, 21 Feb 2005 16:06:51 +0200
Links: << >>  << T >>  << A >>
Marc Randolph wrote:

> newman5382 wrote:

>>There is a school of thought that all off chip IO should be
>>inferred/instantiated at the top level, and not in sub-modules.
 >...
> 
> Is there a good reason for this school of thought?

Mainly ASICs are the reason. Many ASIC tools expect that the
topmost level is used for IO-ring, test structures, plls etc.
And that level instiates the real functional logic.

Also in that style it's easier to do technology indenepdent
designs. For example if the IO-pads need to instantiated manually
they are all in the same place, and only that code needs changes
if FPGA vendor is changed. As far as I know DDR style IO-pads
can't be inferred easily for example.

And for example in hierarchical ASIC design you can't easily move some cells
from the already laid out hard macro to the toplevel etc. So they should
be in the topmost level already, which is last one to be completed.

> Using that concept, when I go to take that top level and create a 4x
> version of it, I can't just create a new top level with a generate
> statement.  Now I have to go edit a completely working design and
> convert all the inouts to seperate in's and out's.  And if that
> original block is still being used in the original design, I now have
> two different versions of the exact same thing that I have to maintain.

You generate a new toplevel that instantiates 4 versions of the core logic
that has still the in and out ports separated. And then just recreate the
IO-drivers in the new 4x toplevel. So you have only one functional logic
block to maintain, and two different toplevel designs.

--Kim

Article: 79585
Subject: Re: does anyone have a c compiler for the picoblaze
From: "Gabor" <gabor@alacron.com>
Date: 21 Feb 2005 06:07:09 -0800
Links: << >>  << T >>  << A >>

ramy wrote:
> does anyone have a c compiler for the picoblaze?

See:

http://toolbox.xilinx.com/cgi-bin/forum?14@@/Embedded%20Processors/PicoBlaze%20Soft%20Processor

In the Xilinx Forums under embeded processors.  There is a beta
version offered in one of the threads.  I haven't tried it.


Article: 79586
Subject: Re: Antti Lukats: all my past live projects to be published...
From: "newman5382" <newman5382@yahoo.com>
Date: Mon, 21 Feb 2005 14:28:00 GMT
Links: << >>  << T >>  << A >>

"Marc Randolph" <mrand@my-deja.com> wrote in message 
news:1108993065.915981.200990@o13g2000cwo.googlegroups.com...
> newman5382 wrote:
>> >
>> > This is probably the price to pay for such a cheap tool, so I
> should not
>> > really complain. Synplify will allow you to use inouts in sub
> modules, but
>> > it costs much more than XST.
>>
>> There is a school of thought that all off chip IO should be
>> inferred/instantiated at the top level, and not in sub-modules.
>>
>> -Newman
>
> Is there a good reason for this school of thought?
>
> Using that concept, when I go to take that top level and create a 4x
> version of it, I can't just create a new top level with a generate
> statement.  Now I have to go edit a completely working design and
> convert all the inouts to seperate in's and out's.  And if that
> original block is still being used in the original design, I now have
> two different versions of the exact same thing that I have to maintain.
>
> Have fun,
>
>   Marc
>

I/O cells tend to be vendor specific.  Grouping vendor specific items into 
specific areas rather having them scattered through out a design would seem 
to be a good thing.  One reasonable place to collect the external I/O is at 
the top level.  One project that was prototyped as a Xilinx FPGA, but slated 
for ASIC conversion instantiated I/O at the top level so the I/O cells could 
be easily swapped out with the vendor's ASIC I/O with a minimum chance of 
error.  I have found that there are issues when you selectively flatten 
different sub modules when I/O are inferred within
 sub modules.  It used to be that in some ASIC designs, there are test 
structures that link all the IO cells together, if these cells are scattered 
through the hiearchy, it is more difficult to chain them together.  In 
addition, I guess there are designs that may or may not have external 
bidirect busses, and some with internal tristate busses.  I personally do 
not like to see inout in the sub hierarchy if there are no (evil) bidirect 
busses.

Do what you want to do.  If it makes sense to you, and you can justify it, 
go for it.  Skill is knowing how to do it.  Leadership is knowing what to do 
and why.

-Newman 



Article: 79587
Subject: Re: WYSIWYG option in xilinx webpack 6.3
From: "M.Randelzhofer" <techseller@gmx.de>
Date: Mon, 21 Feb 2005 15:53:47 +0100
Links: << >>  << T >>  << A >>
> The compiler producing 'wrong code' isnt effected by how much logic
> optimisation is performed I suggest you look elsewhere for the cause of
> your problems.
>

Maybe i'm dreaming...

This is the VHDL code with the interesting 4bit counter ptc:

  if (prc = 7) then
   hf2 <= '0' ;
   keyf2 <= '0' ;
   ptc <= (others => '0') ;
   if (ps2c_f = '1') then -- init hf2 during startbit
    hf2 <= '1' ;
   end if ;
  else
   if (ps2c_f = '1') then
    ptc <= ptc + 1 ;
    case ptc is
     when "0001" | "0010" =>
      if (sdat = '0') then
       hf2 <= '0' ;
      end if ;
     when "0000" | "0011" | "0100" | "0101" | "0110" | "0111" =>
      if (sdat = '1') then
       hf2 <= '0' ;
      end if ;
     when "1000" =>
       keyf2 <= hf2 ;
     when others =>
    end case ;
   end if ;
  end if ;

This translation is ok with not setting the wysiwyg flag:
FDCPE_ptc0 behaves exactly how it should.

FDCPE_ps2c_f: FDCPE port map (ps2c_f,ps2c_f_D,bsysclk,'0','0');
ps2c_f_D <= (NOT ed_ps2(0) AND ed_ps2(1));

FDCPE_ptc0: FDCPE port map (ptc(0),ptc_D(0),bsysclk,'0','0');
ptc_D(0) <= ((ptc(0) AND ps2c_f)
 OR (NOT ptc(0) AND NOT ps2c_f)
 OR (prc(0) AND prc(1) AND prc(2)));

FDCPE_ptc1: FDCPE port map (ptc(1),ptc_D(1),bsysclk,'0','0');
ptc_D(1) <= ((NOT ptc(0) AND NOT ptc(1))
 OR (NOT ptc(1) AND NOT ps2c_f)
 OR (ptc(0) AND ptc(1) AND ps2c_f)
 OR (prc(0) AND prc(1) AND prc(2)));

FTCPE_ptc2: FTCPE port map (ptc(2),ptc_T(2),bsysclk,'0','0');
ptc_T(2) <= ((ptc(0) AND ptc(1) AND NOT prc(0) AND ps2c_f)
 OR (ptc(0) AND ptc(1) AND NOT prc(1) AND ps2c_f)
 OR (ptc(0) AND ptc(1) AND NOT prc(2) AND ps2c_f)
 OR (ptc(2) AND prc(0) AND prc(1) AND prc(2)));

FTCPE_ptc3: FTCPE port map (ptc(3),ptc_T(3),bsysclk,'0','0');
ptc_T(3) <= ((prc(0) AND prc(1) AND ptc(3) AND prc(2))
 OR (ptc(0) AND ptc(1) AND ptc(2) AND NOT prc(0) AND ps2c_f)
 OR (ptc(0) AND ptc(1) AND ptc(2) AND NOT prc(1) AND ps2c_f)
 OR (ptc(0) AND ptc(1) AND ptc(2) AND NOT prc(2) AND ps2c_f));


This output is wrong, with the wysiwyg flag enabled:
The FTCPE_ptc0 flipflop has a completely unrelated signal on it.

FDCPE_ps2c_f: FDCPE port map (ps2c_f,ps2c_f_D,bsysclk,'0','0');
ps2c_f_D <= (NOT ed_ps2(0) AND ed_ps2(1));

FTCPE_ptc0: FTCPE port map (ptc(0),iff1(4).EXP,bsysclk,'0','0');

FDCPE_ptc1: FDCPE port map (ptc(1),ptc_D(1),bsysclk,'0','0');
ptc_D(1) <= ((NOT ptc(1) AND NOT ptc(0))
 OR (NOT ptc(1) AND NOT ps2c_f)
 OR (ptc(1) AND ptc(0) AND ps2c_f)
 OR (prc(2) AND prc(1) AND prc(0)));

FTCPE_ptc2: FTCPE port map (ptc(2),ptc_T(2),bsysclk,'0','0');
ptc_T(2) <= ((ptc(2) AND prc(2) AND prc(1) AND prc(0))
 OR (ptc(1) AND NOT prc(2) AND ptc(0) AND ps2c_f)
 OR (ptc(1) AND ptc(0) AND NOT prc(1) AND ps2c_f)
 OR (ptc(1) AND ptc(0) AND NOT prc(0) AND ps2c_f));

FTCPE_ptc3: FTCPE port map (ptc(3),ptc_T(3),bsysclk,'0','0');
ptc_T(3) <= ((ptc(3) AND prc(2) AND prc(1) AND prc(0))
 OR (ptc(2) AND ptc(1) AND NOT prc(2) AND ptc(0) AND ps2c_f)
 OR (ptc(2) AND ptc(1) AND ptc(0) AND NOT prc(1) AND ps2c_f)
 OR (ptc(2) AND ptc(1) AND ptc(0) AND NOT prc(0) AND ps2c_f));

Any hints ?

MIKE




Article: 79588
Subject: Re: BACK to FPGA
From: "Moti" <moti@terasync.net>
Date: 21 Feb 2005 07:06:50 -0800
Links: << >>  << T >>  << A >>
Hi Eliahu,
I recommend you to contact either MEMEC or IES in Iarael these two
companies represent Xlinx in Israel.

I recently worked with the SPARTAN3 - 3SxLC Board (a MEMEC board) I'm
sure that such a board will be sufficient for a start and it is not
expensive too (about 200 $). 

Regards, Moti.


Article: 79589
Subject: Re: Is Altera Cyclone a good choice ?
From: "Michael Polovykh" <kefir@rissa.ru>
Date: Mon, 21 Feb 2005 18:28:40 +0300
Links: << >>  << T >>  << A >>

"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message 
news:87zmxy871e.fsf@filestore.home.gustad.com...
> "Michael Polovykh" <kefir@rissa.ru> writes:
>
>> So you have a fridge. Put Cyclone into it during PLL work for 30minutes 
>> :)
>> And tell us about this experiment - we are interested in it too :)
>
> I dubt his fridge will go as low as -20 C.
My fridge can go down to -32C.
>
> Petter
> -- 
> A: Because it messes up the order in which people normally read text.
> Q: Why is top-posting such a bad thing?
> A: Top-posting.
> Q: What is the most annoying thing on usenet and in e-mail? 



Article: 79590
Subject: Re: PPC405 sleep?
From: "Bo" <bo@cephus.com>
Date: Mon, 21 Feb 2005 09:33:49 -0600
Links: << >>  << T >>  << A >>
We discovered the source of our 'cant wake up' problems late Friday.... 
unfortunately, I have not determined how, or even if, the problem can be or 
should be circumvented....

Here's the story of what was/is:


1)We put uP to sleep


2)An ext int happens.


3)The uP wakes up:

   3a)Stores the context, all regs, etc on his ISR context stack-- including 
MSR register.

   3b)We mod the TCR to re-enable timer interrupts

   3c)The ISR is serviced

   3d)The original context is restored.

4)Now, we're back asleep since orig context is restored.


So we're continuously being put back to sleep and our mods to the TCR/MSR 
are promptly overwritten by the ISR context restore at the interrupt exit. 
We tried modifying SRR1 in the ISR to clear the WE bit--but that doesn't 
work. It apparently uses the ISR stack context copy and then restores SRR1 
from the stack, then SRR1 to MSR upon rfi.

I'm looking at how to circumvent it in asm.  Your thoughts?

I understand some VHDL needs to be written for a full implementation of 
power management--but I'm not at all sure how it is all supposed to play 
together. I read about the sleep req and other signals--but I don't follow 
how this comes into play with the level of management I am currently trying 
to get working. The VHDL does make sense to me when you start actually 
physically changing clk freq or disabling clk into the 405 core.  An example 
from Xilinx is apparently too much to hope for... to my and my FAE's 
knowledge there are no CPM examples or std. CPM core--not even for their 
ML310 development boards, but I digress.

As an aside, I cannot seem to find an asm instruction that allows you to 
store the contents of a given register at a desired location (ie offset from 
stack context register R31). In other words, what instruction would I use to 
store contents of R20 at address specified by (R31 + offset)? And the doc 
from Xilinx does not have all instructions that the compiler is generating 
(like "lis").

Paul






Article: 79591
Subject: Re: PPC405 sleep?
From: "newman5382" <newman5382@yahoo.com>
Date: Mon, 21 Feb 2005 15:44:30 GMT
Links: << >>  << T >>  << A >>

"Bo" <bo@cephus.com> wrote in message 
news:Y9nSd.1103$i32.86@fe40.usenetserver.com...
> We discovered the source of our 'cant wake up' problems late Friday.... 
> unfortunately, I have not determined how, or even if, the problem can be 
> or should be circumvented....
>
> Here's the story of what was/is:
>
>
> 1)We put uP to sleep
>
>
> 2)An ext int happens.
>
>
> 3)The uP wakes up:
>
>   3a)Stores the context, all regs, etc on his ISR context stack--  
> including MSR register.
>
>   3b)We mod the TCR to re-enable timer interrupts
>
>   3c)The ISR is serviced
>
>   3d)The original context is restored.
>
> 4)Now, we're back asleep since orig context is restored.
>
>
> So we're continuously being put back to sleep and our mods to the TCR/MSR 
> are promptly overwritten by the ISR context restore at the interrupt exit. 
> We tried modifying SRR1 in the ISR to clear the WE bit--but that doesn't 
> work. It apparently uses the ISR stack context copy and then restores SRR1 
> from the stack, then SRR1 to MSR upon rfi.
>
> I'm looking at how to circumvent it in asm.  Your thoughts?
>
> I understand some VHDL needs to be written for a full implementation of 
> power management--but I'm not at all sure how it is all supposed to play 
> together. I read about the sleep req and other signals--but I don't follow 
> how this comes into play with the level of management I am currently 
> trying to get working. The VHDL does make sense to me when you start 
> actually physically changing clk freq or disabling clk into the 405 core. 
> An example from Xilinx is apparently too much to hope for... to my and my 
> FAE's knowledge there are no CPM examples or std. CPM core--not even for 
> their ML310 development boards, but I digress.
>
> As an aside, I cannot seem to find an asm instruction that allows you to 
> store the contents of a given register at a desired location (ie offset 
> from stack context register R31). In other words, what instruction would I 
> use to store contents of R20 at address specified by (R31 + offset)? And 
> the doc from Xilinx does not have all instructions that the compiler is 
> generating (like "lis").
>
> Paul

I don't pretend to completely comprehend what you found, but I think a "Nice 
Catch" is in order.

I saw in the ppc_ref_guide.pdf that

lis has an equivalent mnemonic addlis page 534.  The user is required to 
skip around this document to look up a simple thing, and it is quite 
annoying.

-Newman 



Article: 79592
Subject: Re: Sending information between VHDL modules from the top level module
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 21 Feb 2005 17:27:16 +0100
Links: << >>  << T >>  << A >>

"fpgawizz" <bhaskarstays@yahoo.com> schrieb im Newsbeitrag
news:e192d2d097602ff1328601522ffa3270@localhost.talkaboutelectronicequipment
.com...
> I have this issue where i have a top level module say A.vhd that has a
> state machine. I also have about 3 components - B.vhd, C.vhd and D.vhd
> which i am going to use to make up my top level vhd module. I have process
> statements in B,C and D and I want them to kick off at states 1,2 and 3
> which I have defined in my main module.
>
> so I have a 3 state FSM with states 1,2, and 3 in A.vhd and at state 1, I
> want the process in b.vhd to kick off and at state 2 i want the process in
> c.vhd to kick off and at state 3, I want the process in d.vhd to kick
> off.

Just use a signal and pass the data. Whats the point?

Regards
Falk




Article: 79593
Subject: Re: Issues with a batch of Virtex-II chips
From: "IgI" <igorsath@hotmail.com>
Date: Mon, 21 Feb 2005 17:30:42 +0100
Links: << >>  << T >>  << A >>
> Have you re-run timing analysis on the 5.3 design, but using the latest
> timing analyser and latest speed files?

No, because I don't think there's any timing issue here. The logic is
trivial and runs at low speed. We are using the same "clock generation"
module in several other designs, without any issues. We have products
running 24/7 for two years now without a single issue. As I stated before,
the problem appeared only with the selected chips.

But, I will test our new Virtex-II designs with the latest timing analyzer
and latest speed files as you suggested. It's a good idea for new designs.

> With 6.1, have you tried MPPR (multi-pass pacement and routing)?
> Sometimes modifying the placement (in FPGA editor) of failing paths and
> re-running "re-entrant routing" can fix problems, if there are only a
> small number of failing paths.

Yes, I have. I tried 6.1, 6.2 and 6.3. It's always the same story.
Placer/Router does a lousy job. Either the constraints can't be met or the
router can't connect all the nets. ISE 5.2 SP3 completes without any errors
and reports 7 logic levels for the constraint. On the other hand ISE 6.x
reports 16 logic levels for the same constraint.

In my experience (for the Virtex-II family) if the design takes less than
~90% of chip resources then the results of ISE 6.x are similar to the ISE
5.2 SP3, sometimes even better, but as soon as design takes more than 95% of
all chip resources then ISE 6.x gives up. Similarly I still use ISE 3.3 for
SpartanXL and Spartan2 designs, because ISE 4.2 or newer don't produce the
desired results. I know a lot depends on the synthesis tool (I'm using
synplicity)...

Thanks for you suggestions,
Igor Bizjak



Article: 79594
Subject: Re: cyclone's pll
From: "Gary Pace" <xxx@yyy.com>
Date: Mon, 21 Feb 2005 17:18:28 GMT
Links: << >>  << T >>  << A >>
The mega function created has a pin called input (or similar). You simply 
connect this to a device pin, and then assign the location you need for the 
CLKn pin.

"GL" <a@b.c> wrote in message news:mn.ab807d527b734006.23732@b.c...
> Hi all,
> I'm using a cyclone EP1C6 Q240 and want to instanciate a pll, but using 
> the PLL2 (input are CLK2 and CLK3). My  problem is that with the design 
> assistant, i can create a macro-function called altpll, but i can't choose 
> the input i want (clk2, on pin 153 of EP1C6Q240 ).
>
> how should i do ?
>
> regards,
>
> -- 
> Ceci est une signature automatique de MesNews.
> Site : http://www.mesnews.net
> 



Article: 79595
Subject: Re: Is Altera Cyclone a good choice ?
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Mon, 21 Feb 2005 18:36:28 +0100
Links: << >>  << T >>  << A >>
"Michael Polovykh" <kefir@rissa.ru> writes:

> "Petter Gustad" <newsmailcomp6@gustad.com> wrote in message 
> news:87zmxy871e.fsf@filestore.home.gustad.com...
>> "Michael Polovykh" <kefir@rissa.ru> writes:
>>
>>> So you have a fridge. Put Cyclone into it during PLL work for 30minutes 
>>> :)
>>> And tell us about this experiment - we are interested in it too :)
>>
>> I dubt his fridge will go as low as -20 C.
> My fridge can go down to -32C.

Impressive, my freezer wont even go that low. My fridge goes down to
+2 C. If I want -32 C I will have to put it outside - on an extreme
cold winter night...

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 79596
Subject: Re: Shift register example?
From: Christian Schneider <please_reply_to_the@newsgroup.net>
Date: Mon, 21 Feb 2005 20:19:20 +0100
Links: << >>  << T >>  << A >>
KCL wrote:
> 1) integer count : usually i use std_logic for all my signal and use 
> conversion function for arithmetic, so i have no problem of  wrap around,
That's right.

> 2) reset missing : does at startup all signal have a value unknow but equal 
> to '1' or '0' so after max 16cycles  cpt should back to 0 so there is a 16 
> cycle clock intial time that (depend of your application need but in most of 
> DSP) is not important I think.

I do not agree with you here: what is "XXXX" + 1 ? I had a lot of
simulations which did not start properly because of wrong initial
values.

Well in hardware all would work, but your simulation still differs in
behaviour. This is mainly because hardware does not have the "XXXX" 
value. Since we are here in the FPGA news group, all FPGAs I know of
initialize with zero, unless other values are set.

> Also for reset what is the best synchronous or asynchronous?? because 
> synchronous reset seems to need less ressource??

I have read a lot about resets in this newsgroup and I really do not
understand why so few people use the "reset on configuration": When
you download the bitstream everything has its default, so what else
do you want? You can just program it as asynchronous reset and the
tools do the rest (nearly).

> 3)not a shift register but i think this not a real shift register he wanted 
> :"parallel in serial out latching shift register" for me he asked for 
> serializator (sorry my english is so bad so I translate as I can)
> if i wanted to do a shift register i will have done:
> 
> 
> data_reg <= data_reg(14 downto 0) & data_in;
> data_out <= data_reg(0);

A shift register would have been much faster, and uses much less logic 
resources.

> Finally I just will add that still people not explain very well what they 
> wanted , we couldn't give them exactely what they want to do (and also that 
> they could search by themself , it 's not not too bad for brain activity)
> And excuse me for my "errors" but I just notice that only a french guy with 
> only 6month internship in VHDL developpement(and limited english 
> comprehension) take time to answer to his problem.

Yes you are right, the task is not completely mentioned.
I just wanted to correct the source code, sorry for the harsh tone.


Best regards,
Chris

Article: 79597
Subject: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 22 Feb 2005 09:03:21 +1300
Links: << >>  << T >>  << A >>
Martin Schoeberl wrote:
>>finally I can announce it:
>>
>>http://www.eubus.net/hydraXC
>>
>>Reconfigurable "dream" - small and fully reconfigurable computing module.
>>
>>Designed to be as reconfigurable as possible, eg all of its
>>intelligence is loaded at the boot time. The smart system
>>management controller allows safe update of the OS image as
>>well as the FPGA bitstream over any supported communication
>>channel (LAN or serial or other). Of course the new hardware
>>and OS can simply be copied to the removable media (miniSD)
>>card, no JTAG cable (or any cable) required.
>>
> 
> 
> Hi Antti,
> 
> looks good. So I can now stop building my JopStick as your board
> contains everthing (and more) what I need ;-)
> However, for my application it's a little bit pricy.

So where are the prices ?

Seems this would have a range of prices, as the FPGA changes,
so the smallest one would suit JOP ?

-jg


Article: 79598
Subject: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40 !
From: "Antti Lukats" <antti@openchip.org>
Date: Mon, 21 Feb 2005 21:23:22 +0100
Links: << >>  << T >>  << A >>
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag
news:421a3e83$1@clear.net.nz...
> Martin Schoeberl wrote:
> >>finally I can announce it:
> >>
> >>http://www.eubus.net/hydraXC
> >>
> >>Reconfigurable "dream" - small and fully reconfigurable computing
module.
> >>
> >>Designed to be as reconfigurable as possible, eg all of its
> >>intelligence is loaded at the boot time. The smart system
> >>management controller allows safe update of the OS image as
> >>well as the FPGA bitstream over any supported communication
> >>channel (LAN or serial or other). Of course the new hardware
> >>and OS can simply be copied to the removable media (miniSD)
> >>card, no JTAG cable (or any cable) required.
> >>
> >
> >
> > Hi Antti,
> >
> > looks good. So I can now stop building my JopStick as your board
> > contains everthing (and more) what I need ;-)
> > However, for my application it's a little bit pricy.
>
> So where are the prices ?
>
> Seems this would have a range of prices, as the FPGA changes,
> so the smallest one would suit JOP ?

the pricing is not fixed yet, basically the modules (2 PCB variants)
can be fitted with any S3 or V4 in FT256 or SF363 package
the S3 version is mainly targetted for S3-1000 but could also
be fitted with S3-200 for some applications.

As much as I know JOP should fit the smallest one..

MicroBlaze uClinux will be as primary default hardware
config and O/S, but other options will be offered as well
LEON3 as secondary and possible OpenRisc as 3rd in line

Sure it is also possible to have something completly different
hardware as well, there is actually no requirement to use any
softcore processor at all.

At boot the FPGA is loaded either from onboard flash or
from miniSD, after the configuration FPGA has full access
to all connected peripherals and resources, ie can continue
boot by loading OS image from onchip flash or from miniSD
card, after OS comes alive it can load secondary hardware
and probably second OS over LAN, then request reboot
from system management controller.

if the second configuration should be faulty the system
management controller restores known good configuration
that allows access again over network (or other communication
channel)

The limit of different hardware configurations is only limited
by the size of the miniSD card used, there is no fixed limit
as by systemace.

Antti



Article: 79599
Subject: Re: Antti Lukats: all my past live projects to be published...
From: "Erik Widding" <widding@birger.com>
Date: 21 Feb 2005 12:32:50 -0800
Links: << >>  << T >>  << A >>
> 1) for EDK the _I _O _T useage is required to be "EDK compliant" -
this
> issue has nothing todo with XST inout handling

Actually EDK can handle tristate buffers declared inside of a pcore.
The syntax for the MPD is as follows:

   PORT AD               = "" , DIR=inout, VEC=[31:0], 3STATE=FALSE,
IOB_STATE=BUF

This exists because some IP is very tightly bound to its IO pin type,
such as PCI or DDR SDRAM.  We requested this feature from Xilinx a few
years ago specifically so that we could use the PCI logicore netlist
inside of a wrapper in EDK, without hand editing the top level VHDL.


Regards,
Erik.

---
Erik Widding
President
Birger Engineering, Inc.

 (mail) 100 Boylston St #1070; Boston, MA 02116
(voice) 617.695.9233
  (fax) 617.695.9234
  (web) http://www.birger.com




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