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Fayette, You guessed correctly I did went through a lot with this one, I'm happy to hear that was helpful.. Moti.Article: 78126
Rudolf Usselmann wrote: > Hi ! > Impact is reporting some strange errors when attempting to > program a xc4vlx25. First I get "Error in status register > CRC bit is NOT 0", and than during verify I get 45-52 > mismatches, seems to be different from trial to trial. > Tried several boards, seems to be persistent ... > > Any ideas what might be causing that ? > > Oh, yes I am using Par. Cable 4, and ISI 6.3.03i. Howdy Rudi, Sorry I can't be of any help, except to say that, as the JTAG faq shows, you've got to keep trying. http://www.fpga-faq.com/FAQ_Pages/0001_JTAG_Config.htm Make sure the JTAG clock looks good at the via under the LX25. Bypass the data around other devices (if you have it going through them). Hold you nose just right. Wait for a full moon. I wish I were kidding. MarcArticle: 78127
I couldn't find the "what's new" in Xilinx's web. could anyone tell me? thanks^_^Article: 78128
Le 25/01/2005, Moti a supposé :
> There is an example for a bidim array declaration :
>
> type bidim_array is array (width-1 downto 1, width-1 downto 0) of
> std_logic;
> signal MEM : bidim_array;
>
> Moti.
yes, but i can't do something like
MEM(i) <= foo(width-1 downto 0) ;
quartus give me the following error :
"slice of object cannot be specified for object that has an array type
of more than one dimension"
and the help gives the following example :
ARCHITECTURE ex1 OF example IS
TYPE mem_cell IS ARRAY (0 to 1023, 0 to 31) of BIT;
SIGNAL mem_inst : mem_cell;
BEGIN
o(0) <= mem_inst(0,0);
o(1) <= mem_inst(0,1);
o(2) <= mem_inst(0,2);
o(3) <= mem_inst(0,3);
o(4) <= mem_inst(1,0);
o(5) <= mem_inst(1,1);
o(6) <= mem_inst(1,2);
o(7) <= mem_inst(1,3);
END ex1;
which is what you suggest, but is not very "simple".
In this case, i would like to do something like :
o(0 to 7) <= mem_inst(0 to 1, 0 to 3);
--
Ceci est une signature automatique de MesNews.
Site : http://www.mesnews.net
Article: 78129Hi, I am a french student and I am actually looking for small firm (not a huge and famous one like Thales or Sagem...) who make outsourcing design. Thank you for your answer. AlexisArticle: 78130
Yeah Ive tried that,it detects the static hazard,removes the static harard,which leaves the output stuck at '0' so it then removes the now redundant logic.Arrrrrrgh!!Article: 78131
Usually I write something like:
ARCHITECTURE ex1 OF example IS
TYPE mem_cell IS ARRAY (0 to 1023) of std_logic_vector(0 to 31) ;
SIGNAL mem_inst : mem_cell;
and then you could pick the value you want as:
o(0 to 7) <= mem_inst(0) (0 to 3) & mem_inst(1) (0 to 3);
or
using a for loop
for i in 0 to 1 loop
o(i to 4*i-1) <= mem_inst(i) (0 to 3);
end loop;
it should work
PS: tu es francais??
"GL" <a@b.c> a écrit dans le message de news:
mn.cb3f7d5196cb4083.23732@b.c...
> Le 25/01/2005, Moti a supposé :
>> There is an example for a bidim array declaration :
>>
>> type bidim_array is array (width-1 downto 1, width-1 downto 0) of
>> std_logic;
>> signal MEM : bidim_array;
>>
>> Moti.
>
> yes, but i can't do something like
> MEM(i) <= foo(width-1 downto 0) ;
> quartus give me the following error :
> "slice of object cannot be specified for object that has an array type of
> more than one dimension"
>
> and the help gives the following example :
>
> ARCHITECTURE ex1 OF example IS
> TYPE mem_cell IS ARRAY (0 to 1023, 0 to 31) of BIT;
> SIGNAL mem_inst : mem_cell;
> BEGIN
> o(0) <= mem_inst(0,0);
> o(1) <= mem_inst(0,1);
> o(2) <= mem_inst(0,2);
> o(3) <= mem_inst(0,3);
> o(4) <= mem_inst(1,0);
> o(5) <= mem_inst(1,1);
> o(6) <= mem_inst(1,2);
> o(7) <= mem_inst(1,3);
> END ex1;
>
> which is what you suggest, but is not very "simple".
> In this case, i would like to do something like :
>
> o(0 to 7) <= mem_inst(0 to 1, 0 to 3);
>
> --
> Ceci est une signature automatique de MesNews.
> Site : http://www.mesnews.net
>
Article: 78132ROTFL hold yor nose! Yes that seems to be the only thing todo if iMpact and xilinx cables have download problems. We just had a Platfrom Flash that had increasing failure rate on programming using xilinx Cable III until it did not program at all, giving erase errors. Changin to Cable IV did fix the Erase error. Beats me. Well I also have seen boards that can not be programmed at all with Cable IV but program without any problems using 5 wires to LPT port. I think mr Usselman is using a LX25 Board from Memec so he cant change much on the board, it is supposed to work! So yes, the nose trick is the only one left! I wish i would know how to hold my nose properly, too much rain is coming in :( anttiArticle: 78133
kcl a couché sur son écran : > Usually I write something like: > > ARCHITECTURE ex1 OF example IS > TYPE mem_cell IS ARRAY (0 to 1023) of std_logic_vector(0 to 31) ; > SIGNAL mem_inst : mem_cell; > > and then you could pick the value you want as: > > o(0 to 7) <= mem_inst(0) (0 to 3) & mem_inst(1) (0 to 3); > or > using a for loop > > for i in 0 to 1 loop > o(i to 4*i-1) <= mem_inst(i) (0 to 3); > end loop; > > it should work > > PS: tu es francais?? yes... why ? > > "GL" <a@b.c> a écrit dans le message de news: > mn.cb3f7d5196cb4083.23732@b.c... >> Le 25/01/2005, Moti a supposé : >>> There is an example for a bidim array declaration : >>> >>> type bidim_array is array (width-1 downto 1, width-1 downto 0) of >>> std_logic; >>> signal MEM : bidim_array; >>> >>> Moti. >> >> yes, but i can't do something like >> MEM(i) <= foo(width-1 downto 0) ; >> quartus give me the following error : >> "slice of object cannot be specified for object that has an array type of >> more than one dimension" >> >> and the help gives the following example : >> >> ARCHITECTURE ex1 OF example IS >> TYPE mem_cell IS ARRAY (0 to 1023, 0 to 31) of BIT; >> SIGNAL mem_inst : mem_cell; >> BEGIN >> o(0) <= mem_inst(0,0); >> o(1) <= mem_inst(0,1); >> o(2) <= mem_inst(0,2); >> o(3) <= mem_inst(0,3); >> o(4) <= mem_inst(1,0); >> o(5) <= mem_inst(1,1); >> o(6) <= mem_inst(1,2); >> o(7) <= mem_inst(1,3); >> END ex1; >> >> which is what you suggest, but is not very "simple". >> In this case, i would like to do something like : >> >> o(0 to 7) <= mem_inst(0 to 1, 0 to 3); >> >> -- Ceci est une signature automatique de MesNews. >> Site : http://www.mesnews.net >> -- Ceci est une signature automatique de MesNews. Site : http://www.mesnews.netArticle: 78134
Il se trouve que kcl a formulé : > Usually I write something like: > > ARCHITECTURE ex1 OF example IS > TYPE mem_cell IS ARRAY (0 to 1023) of std_logic_vector(0 to 31) ; > SIGNAL mem_inst : mem_cell; > > and then you could pick the value you want as: > > o(0 to 7) <= mem_inst(0) (0 to 3) & mem_inst(1) (0 to 3); > or > using a for loop > > for i in 0 to 1 loop > o(i to 4*i-1) <= mem_inst(i) (0 to 3); > end loop; but i should create a new type for any array of different size ... -- Ceci est une signature automatique de MesNews. Site : http://www.mesnews.netArticle: 78135
Antti Lukats wrote: > ROTFL > > hold yor nose! Yes that seems to be the only thing todo if iMpact and > xilinx cables have download problems. We just had a Platfrom Flash that > had increasing failure rate on programming using xilinx Cable III until it > did not program at all, giving erase errors. Changin to Cable IV did fix > the Erase error. Beats me. Well I also have seen boards that can not be > programmed at all with Cable IV but program without any problems using 5 > wires to LPT port. > > I think mr Usselman is using a LX25 Board from Memec so he cant change > much on the board, it is supposed to work! > > So yes, the nose trick is the only one left! I wish i would know how to > hold my nose properly, too much rain is coming in :( > > antti Yes I am using the Memec Insight Virtex 4 LX25 boards, Just got three of them today. I kind of assumed that the boards coming from Memec-Insight are professionally designed and reliable. Thats why we for out the big bucks for these boards. Of course I placed an inquiry with them as well, just wanted to see who is faster, the net or Memec ... will post an update as soon as I have a solution ... Cheers, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 78136
"logjam" <grant@cmosxray.com> wrote in message news:1106636385.929865.295480@c13g2000cwb.googlegroups.com... > I'd like to see those schematics, if you wouldn't mind. > Something that Eagle can open? I suspect Eagle cannot read Orcad files. I could print to pdf if I find out how to re-install distiller on my PC. Meanwhile I might be able to send you screen grabs. Where should I email them? > If you would like, you can post your work on a web board I started doing so here: http://homepage.ntlworld.com/kryten_droid/AppleMac/apple_mac_logic.htm It has links to some PAL application notes about interfacing the 68K, I think they will be very informative. I am squeezing the multi-MB pdf files into 4-bit greyscale PNG files unitron2 is done, am downloading unitron1 right now. > I bought an 18 channel logic analyzer Nice. > Mac 512k motherboards off eBay for $9 I'm buying an ST motherboard soon, as a reference. My local professional supplier (RS) still sell the PLCC68 68HC000 but in tubes of 18. Maybe it isn't obsolete as I thought? Works out about £11 each for the 16 MHz, or £6 for the 8 MHz chips. > Tuesday I will be decapsulating/delidding/decapping the chips and > photographing them with my digital camera. Perhaps you could borrow one of those USB camera microscopes for the job. > the same on the silicon layer as they do on the datasheet. At some point you will have to recreate the logic equations, and will have to figure out how the 68K works. I'd read the app notes first and you may be able to make a good start. I would want to at least put the six PAL into one CPLD. Maybe the IWM can fit in a modern CPLD too. CUPL is a bit primitive, I'll have a go converting the app notes to VHDL, and compile them using Xilinx ISE. Cheers, K.Article: 78137
"logjam" <grant@cmosxray.com> wrote in message news:1106644343.308244.62580@f14g2000cwb.googlegroups.com... > The issue with the IWM is confusing. I'm not sure how the Plus roms > would handle not having the IWM or 5380 SCSI chip. > I can not find any 5380 chips on the market. Zilog has a Z53C80 that > is in Life-Time production, but they have no stock and neither do any > of their distributors. The 5380 could probably be duplicated with 2 or > 3 75 MHz PICs. > I have no idea what a FPGA is See http://www.howell1964.freeserve.co.uk/logic/index_logic.htm > Maybe we could make a 5380 in an FPGA SCSI is dead. Do an IDE interface instead. Floppies are disappearing from modern machines. Do an SD card interface instead. > There was the suggestion of putting the whole plus into a single FPGA. Nah! :-) I find VHDL easier to read than CUPL. See http://www.howell1964.freeserve.co.uk/logic/polymorph_project.htm for what can be done. > After I get a better understanding of the computer and possibly some > experience with FPGAs from the project... >Article: 78138
>From what I have understood from the Xilinx Documentationa XAPP058, is that the uP simulates the JTAG ports to configure the FPGA. Also I am checked the XAPP502, where it discusses the slave serial and select MAP method of configuring. Do the above methods require the use of Xilinx Cables or parallel cables? I am guessing there is no size limit on the Flash PROM which I can use for the FPGA? I would like to be able to use the microprocessor to do the whole conguration process. ThanksArticle: 78139
">> >> PS: tu es francais?? > > yes... why ? > Parceque c'est plus facile de s'expliquer en francais ;) except if you prefer english or if there is a rule that specify that all post must be in english PS: Sinon je vois pas d'autre facon que de creer un nouveau type à chaque fois (attention je dis pas que ca existe pas mais juste que je connais ps d'autre facon de faire) Tu fais du vhdl pas du C :)Article: 78140
Hi, I have an Optical encoder on a system. I want to double / triple..... etc the incoming pulses. I want to include an ADPLL in a Altera FPGA, Currently the design is in verilog. Does anybody have any code and an example how to use it. The Freq of the Altera is 20Mhz The max freq of the encoder is 25Khz The max Freq of output is 30Khz Please Help. PliersArticle: 78141
Rudolf Usselmann wrote: > Yes I am using the Memec Insight Virtex 4 LX25 boards, Just > got three of them today. I kind of assumed that the boards > coming from Memec-Insight are professionally designed and > reliable. Thats why we for out the big bucks for these > boards. > Of course I placed an inquiry with them as well, just wanted > to see who is faster, the net or Memec ... will post an update > as soon as I have a solution ... > > Cheers, > rudi > ============================================================= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and Synthesis Another bit of information: I did try to reduce the speed of the programming cable to 200 KHz - didn't make any difference. It appears as my target application does work correctly even though of the reported errors. Perhaps bitgen/impact are not quite Virtex 4 tested/debugged ? Anybody here ever programed a Virtex 4 LX 25 ? Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 78142
Yaju N wrote: > >From what I have understood from the Xilinx Documentationa XAPP058, is > that the uP simulates the JTAG ports to configure the FPGA. Also I am > checked the XAPP502, where it discusses the slave serial and select MAP > method of configuring. > > Do the above methods require the use of Xilinx Cables or parallel > cables? > I'm assuming that the uP is on the same board as the FPGA, in which case you don't need Xilinx cables. However you may need some other connection to program the uP's flash. > I am guessing there is no size limit on the Flash PROM which I can use > for the FPGA? > No maximum limit, you need enough bits for the bitstream. Look at the datasheet for PlatformFlash (XCFxx) for representative bitstream sizes of various FPGA's. > I would like to be able to use the microprocessor to do the whole > conguration process. > Do you need to configure more than just the FPGA? If you want to do multiple chips in a JTAG chain you can do this, but for just an FPGA it is much easier to use slave serial mode. The uP flow for this is: 1. assert FPGA PROG# pin low. 2. wait for minimum reset time then de-assert PROG# high. 3. wait for INIT# to go high (you need a pullup on this pin). 4. place first bit of bitstream on DIN. 5. pulse CCLK high then low. 6. repeat 4, 5 for remaining bits of bitstream. While doing this monitor the INIT# line. If it goes low, the FPGA has detected a bitstream error. 7. place 1 on DIN. 8. pulse CCLK high then low until DONE goes high (pullup required). If you *want* to use the Xilinx PlatformFlash for configuration, you will need to program the flash by way of the JTAG pins. This can be done by the uP with some help from impact for generating the required commands. In this case the FPGA would be in master serial mode and load automatically from the PlatformFlash at power-on or when the JTAG code to reset the FPGA (using CF output) is sent by the uP or other programmer. In this configuration you *could* use a Xilinx parallel cable to program the flash as long as the uP doesn't try to drive the JTAG lines while the cable is attached. > ThanksArticle: 78143
Andrea Sabatini wrote: > Hi all. > > I am working on a project which is targetted on a Xilinx Virtex2Pro xc2vp30. > To debug the logic that I am developing I sometimes need to modify the code > that is executed by one of the two PPC available inside the fpga. The code > is completely stored in internal BRAM so if I change it I need to update the > bitstrem of the device and to me this seems quite easy: just press the > button "Update Bitstream" in Project Studio (version 6.3). I will admit that a similar situation, I generally don't use the XPS gui, but I do use the ISE gui. If all I do is make code changes, then my procedure is to do "make program", which I am guessing corresponds to clicking the "Compile Program Sources" button in XPS. Then when I go to ISE, the only thing it needs to rerun is "Generate Programming File". These two steps take a couple of minutes. -- My real email is akamail.com@dclark (or something like that).Article: 78144
In article <b93cv0p2kvkjrfra1ajdl0vujs8apukntl@4ax.com>, Jonathan Bromley <jonathan.bromley@doulos.com> wrote: >On 24 Jan 2005 09:57:37 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: > > >>I'm working on a program which will generate some VHDL or Verilog code >>to do some arithmetic operations. The code generated should be able to be >>synthesized into various FPGA families (an option to the code generating >>program). The function is something along the lines of: >> >> threshold= -15.0 #typically between -20.0 and -10.0 depending on problem >> X = vector of numbers in the range of -infinity to 0.0 >> Y = vector of numbers in the range of -n to +n >> accumulator = 0 >> foreach x in X, each y in Y >> if x > threshold #typically -20.0 to -10.0 depending on the problem >> accumulator += y*exp(x) >> end >> end >> answer = accumulator + bias > >The lower limit of X sounds a little difficult to synthesise :-) Right... that's the reason for that threshold test :) But in the hardware implementation, that will be our minium value that you can address the lookup table with. > >>Currently I've got a lookup table for the exp(x) function which works fine >>for this application since the values of x will always be negative and we >>canb disregard values of x which are less than some threshold (since for >>our purposes the result is essentially 0). I'm simulating the lookup >>table using a case statement in a programming language called Ruby. I can >>then replace the exp() function with the lookup table version in the code >>and compare results. So far the lookup table seems very manageable - 64 >>entries seems to work just fine. I need to do a bit more research, but it >>seems like 256 entries or less should work for the majority of problems. > >OK, but of course you need to be very careful that you understand all >the issues about precision - too few entries in your lookup table >will give significant errors in some cases. For well-behaved >functions such as exp() it's sometimes appropriate to use a fairly >coarse lookup table and then do linear interpolation between the >entries. Make each LUT entry hold two values: the value at the >chosen point, and the gradient from there to the next point. >(Hey, for exp() they're the same!!!) Then split the binary x >value into two fields: the most significant bits address the LUT, >and the less significant bits are multiplied by the gradient >and added to the LUT first-order result. Actually, I'm doing some experiements right now to determine how 'course' we can make the lookup table. It depends on the problem of course, so I also need to come up with a way to analyze a given problem to determine this prior to generating the lookup table. It turns out that for one of the problems a lookup table for exp(x) with only 32 entries works fine whereas for a different problem a lookup table closer to 640 entires is needed. > >>Now I need to start migrating more towards a hardware implementation. So >>I need some way to represent the values from the exp() function in binary. >>I'm looking for advice on how to scale these numbers. I'm currently >>thinking that given 8 bits (though the number of bits will probably be >>variable depending on the application and the size of the FPGA) I have a >>range of 0 to 255, so exp(0) (which is 1.0, of course) could be >>represented by 255 and exp(threshold) could be represented by 0. Then >>multiply this integer (between 0 and 255) by the y value which is itself >>scaled, and add (or subtract, depending on the sign) the result to/from >>the accumulator. At this point, I suspect that I would need to disregard >>some number of LSBs in the accumulator (because the x values were >>essentially scaled up to be greater than 0). > >Be somewhat wary of simply dropping unwanted LSBs. Whenever you >do that, you are introducing a bias into the result of (on average) >a 1 in the most significant lost bit. This is usually harmless on >a single value, but if you're accumulating many values then the >truncation errors can stack up. Consider rounding instead: add >a 1 in the most significant lost position, and then drop the LSBs >(or, if you prefer, increment the truncated result if the most >significant dropped bit is 1). > good point. What I was thinking was that the resolution of my LUT (determined via experiments as I mentioned above) could determine the number of bits addressing my LUT. So if x were an 8 bit integer (256 locations) and I only need 128 entries in my LUT then I was thinking that I would only use the 7 most significant bits of x to address the LUT. Does this make sense? Of course this all has to be scaled correctly so that the resolution lost by eliminating the lower bit will match the resolution of the LUTs in the experimental results... I suspect that could mean adding locations in the LUT to make it easier to match up the two without losing too much precision. Lucily, so far precision doesn't seem to be a problem. >>Am I on the right track? > >Yes indeed. You are, however, mixing together two slightly different >(but closely related) ideas and it might be a good idea to separate >them. > >First, you are considering scaling all the numbers in the problem >(scaling your exponent by 255). This is of course entirely >reasonable if (1) you can get the table into that form easily, >and (2) you can "un-scale" the final result before making use of it. > >VHDL library - you can read my notes by downloading the stuff at > http://www.doulos.co.uk/knowhow/vhdl_models/fp_arith/ >It's a reasonable "beginners' guide" to fixed-point binary >arithmetic. However, please DON'T use the fixed-point package >you'll find there, for two reasons: >(1) it's not very well tested, and I found a horrible bug in > it a couple of months ago >(2) there's a proposed standardised fixed-point package, > written by David Bishop, now available at > http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html > (look for the item "IEEE.Fixed_Pkg). Thanks for the pointer, I'll have a look. > >Finally, it sounds as though you've done all the prototyping in >Ruby so this probably doesn't help, but... if you use something >like Matlab then you would be able to simulate all the effects >of limited bit precision without too much trouble. Actually, it's quite doable in Ruby as well - there's the RHDL (Ruby Hardware Description Language) as well as some other libraries (it's fairly easy to do ranged integers, for example) that should make it fairly easy. Currently I'm generating lookup tables (case statements, actually) for various problem/data sets and varying the range and resolution until I get failures from the testcases associated with these problems. This is easily done by replacing the standard 'exp()' function with the lookup table (which are all still in floating point using case statments) but the next step is to convert to using ranged integers. After that I should be able to start having the program generate VHDL. > >Hope this helps a bit Yes, thanks for the pointers. PhilArticle: 78145
Hello again I solved it now. I used two DCM's and two dividers. I set the first DCM to 24/5 then an external 1/10 then the second DCM set to 24/5 and last an external 1/20 :-) So the output frequency is: 24MHz x (16/5) x (1/10) x (24/5) x (1/20) = 24 MHz x (48/625) = 1843200 Hz "Gabor" <gabor@alacron.com> skrev i meddelandet news:1106606998.724453.194100@c13g2000cwb.googlegroups.com... > Allan Herriman wrote: > > > Are you aware of the effects of clock jitter on ADC performance? You > > should check with your system designers about this effect, otherwise > > you may get "sub-optimal" results, i.e. it won't work. > [snip] > > It's possible that the divide by 13 counter would be better, as it > > generates no jitter. Can you tolerate the frequency error? > > > > Regards, > > Allan > > If you can't live with either 41 ns jitter or the frequency error you > could cascade two DCM's using 8/25 and 6/25 respectively for > CLKFX_MULTIPLY/CLKFX_DIVIDE. The intermediate frequency would be > 7.68 MHz. which is well below the output frequency specification for > CLKFX even in low frequency mode, so you'll need to really set the > first CLKFX_DIVIDE to 1 and then externally divide by 5 to generate > the input to the second DCM. > I don't have enough experience with Spartan 3 to tell you how much > jitter > you will get this way, but if the second DCM actually locks, I can't > believe it's anywhere near 41 ns. >Article: 78146
Hi, I'm trying to design my system using partial reconfig and bus macro. Routing a module, I obtain this error for some signals: ERROR:DesignRules:579 - Netcheck: The signal POS_I was found to be routed with nodes in two route area. This is not permitted for Modules in partial reconfiguration mode. Now, I've imposed the area constraints, and all the signals are internal to the module. Analizing with FPGA_Editor, this signals correspond to LUT placed on the boundary of the module area. Can someone help me? Another question. Somewhere I read I can't use LUT to pilot enable signal of bus macro three-state buffer. This means I have to pilot them with I/O pad? If I use a direct allocation LT<='0' I'm wrong? In adding to this, the signals piloting LT and RT must be driven in the top level or, instead, left module must provide LT and right module RT, without involving top-level? Thank you very much. ScarexArticle: 78147
Rudolf Usselmann wrote: > > I've got several boards from Memec-Insight with the Virtex 4 LX-25. > Unfortunately they are marked "Engineering Samples", which worries > me. > > Can some one from Xilinx explain the difference between Engineering > Samples and Production devices ? Are there any function/electrical/ > timing differences ? > > Thanks, > rudi > ============================================================= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and Synthesis Rudi, You must download the XC4VLX25CES errata datasheet, find out what the short comings are, and decide if they matter for your application and evaluation. Unfortunately, the Xilinx web site uses session specific dynamic links, so this is as close as I can get an exact url to point you to the pdf for the ES. Go to the errata section at the bottom of this page: http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Virtex-4&iLanguageID=1 This datasheet describes some JTAG specific issues that may be the root cause of your other post. More power requirements during init -- check your power supplies! Thanks, SteveArticle: 78148
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1106626400.522496.188140@f14g2000cwb.googlegroups.com... > Low-pass filter followed by Schmitt trigger is the only safe bet. Pedantically, I disagree. Debouncing with delays is also a safe bet. It can also saves all those R's & C's! See Dan's post. Cheers, Syms.Article: 78149
Sean,
The cable will most likely work in XP SP2. Our testing was indeed
limited in duration and intensity owing to the conflicting schedules of
XP SP2 release and the release of the cable but that testing did show
full functionality on our systems.
Sean Durkin wrote:
> Hi again,
>
> I'm thinking about buying one of Xilinx' Platform USB cables. However,
> it says in answer record 20429:
>
> "Windows XP SP2 is not an officially supported environment."
>
> I guess that means Xilinx just hasn't tested it in this environment (or
> at least they hadn't last time the answer record was updated), hence
> they won't guarantee it will work.
>
> Has anyone successfully used it or encountered any problems?
>
--
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