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lomtik wrote: > Hi, > I am working max_sample_temp and min_sample_temp over several Clocks. > Then at symbol_clk_edge I would like to assign most recent value of > these signals to another signals (marked as _result) and load new value > to _temp signals again. > Is the next a good way to do it? > I suspect that max_sample_result <= SAMPLE_IN can occur since all > statements are executed AT THE SAME TIME. That's what I don't want. Yes they all execute at the same time, i.e. the rising edge of clk. But... if you look at it like a simulator, the order of operation is: 1. sample all inputs (right side of equation) 2. generate output values from the logic (here these are all simple assignments so output values come from sampled inputs directly) 3. update all outputs from the generated values. So... all outputs change at the same time, but using the input values from before any change occurs. This is how flip-flops work in real life. > What should I do? Try the code just as you wrote it. > > if (clk'event and clk='1') then > if (symbol_clk_edge='1') then > -- Store results in another signal and reset temp signal > -- to the first new sample > max_sample_result <= max_sample_temp; > min_sample_result <= min_sample_temp; > max_sample_temp <= SAMPLE_IN; > min_sample_temp <= SAMPLE_IN; > end if; > end if; > > > > ThanksArticle: 77476
I used Xilinx EDK base system builder for an ML310 development board and added UART, sysACE, DDR, BRAM and the design comes up--via an ACE file. I'm trying to add XilFATFs lib support and make a standalone boot app that will read the vxWorks BSP file from CF and then jump to it. this would allow me to hopefully use soft reboots, bootChange, etc that I cannot now. I added the Xil_FATFs lib and wrote a simple piece of code to see if the File IO is working and I get the following build error under LibGen. Running DRCs for OSes, Drivers and Libraries ... ERROR:MDT - ERROR FROM TCL:- Sysace HW module not present or not accessible from this processor. FATfs cannot be used without this module ERROR:MDT - Error while running DRC for processor ppc405_1... I had to mod the Defaults on the Lib to say I needed write support to get this far in the build-otherwise it complained that write.o didn't exist. Even though I don't need write capability. Note this problem seems to disappear when using EDK 6.3. (I had been using 6.2 because many of Xilinx examples won't build in 6.3) I am not using processor1 at all. I think that error is perhaps being falsely generated and the real error is the 1st one-but I have no idea why it thinks Sysace HW module not present. (I am using a V2P30 based card that has 2 PPC405s in the Silicon--not soft-core processors) Has anyone here done anything like this? or can point me to some working examples? On the surface it would appear this should be very easy to do, but the EDK tools aren't the most helpful when it comes to error messages and problem resolution suggestions. Thanks, Paul pcalvert@no_spam_radiancetech.kill_all_spam.com If replying via email, please remove the obvious spam refs from emailArticle: 77477
I found the problem!!! The design targeted a Cyclone FPGA. I generated a 9 bit counter lpm_counter0 and used my signal INC_WF_ADDR as input to increment that counter. That signal was missing form the design. I changed device to ACEX1K and problem was reported instead of the internal type crash. I sourced the signal changed back to Cyclone and the desing now compiles. GeorgeArticle: 77478
Hi- I have a project in which I imported an EDK instantiated processor core- and have a whole bunch of logic around it. For my initial build- this all worked well. The processor core was all EDK generated (NGC files I think), and I used synplify to synthesize my system_stub and user logic. For the final build- I had to switch to importing my user logic as an EDF file from Synplify because I used a embedded core which uses a library- and ise doesn't pass that information to Synplify properly (acccording to user app notes). The problem is in the initial build- under mapping properties- I get a whole slew of options- "Perform Time driven packing and placement" down to other map line options. (Solaris version 6.2.03i) In the final build- I see a much smaller subset of these options- "Perform time driven packing and placement" is not one of them. I had to use this option to meet my timing. Anybody have any clue as to why these options would be gone? The fact that I am using a EDF for most of my RTL (top is still VHDL structural code)- shouldn't make any difference in the back end I wouldn't think?! Any ideas appreciated.... WPArticle: 77479
David <david.nospam@westcontrol.removethis.com> writes: > I don't know about Sweden, but in Norway the tax rate isn't actually as > bad as that - only about 40% or so. It varies widely according to your I'm (in Norway) close to 50% income tax, sales tax (VAT) is 25%, a gallon of gasoline is US$ 6. Then there are road tax, toll, lots of extra taxes on certain gods, if you buy a high range Mercedes you can pay more than 1 million NOK (160,000 US$) in taxes alone on that single purchase. 0.5L beer costs 5+ US$ in the store and usually US$ 10+ in a resturant. > the cost of living here (in Norway - Sweden is similar), some things are > relatively cheap (like housing, and electricity), and others expensive > (like petrol). Salaries have much less spread here - high-paying jobs are > lower-paying than the UK or the US, but low-paying jobs are better paid. > And as an indication, my four-bedroom house cost about twice my salary, > although admittedly that was an unusually good deal. You can't be living in a major city. In Oslo a four bedroom house cost at least 5x my annual income (or 10x after income tax). I've lived in California and the only think I can think of which is more expensive there than in Norway is lift tickets at ski resorts... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 77480
If you're using ISE from the project Navigator, there is a switch in the preferences for advanced options. This would seem to be global, since normally the same user would always want the same interface regardless of project, however the setting is saved with the project. So when you create a new project you need to go back to: Edit --> Preferences --> Processes --> Advanced. This should bring up the remaining options.Article: 77481
I would like to assign TEMP value to RESULT at symbol_clk_edge and reset TEMP to SAMPLE_IN value. The most important for me is to store last value of TEMP to RESULT before resetting it. I'll try using it again as I did write originally. I had some problems with this implementation though. That's why I've posted the question. Sometimes at symbol_clk_edge, RESULT would be assigned with SAMPLE_IN (bad), and sometimes with TEMP as I want it. But also, it looked like there was no delay between SAMPLE_IN and RESULT or TEMP!! maybe because of that? SAMPLE_IN is a port TEMP, RESULT are signals. ?? I'll try assigning port to signal first. Maybe it will create a proper 1 CLK delay. Hope that helpsArticle: 77482
Hi everyone! I've run into a problem with a design I'm working on and I hope someone may have had a similar problem before. I have a narrow but deep SelectRam with some data in it, that I am trying to read into a std_logic_vector. The problem is when I try to synthesize the design using Synplify Pro, it gives me the following error: "Expecting constant expression" which refers to this line of code: q_out_buff(q_up_idx downto q_idx) <= q_dout(1 downto 0); The above code is in a clocked process, and executes a finite number of times to load the vector. On each clock, q_up_idx and q_idx get incremented and q_dout is the output from the SelectRam. Now, the synthesizer doesn't like the dynamic index into my vector, even though functionally it is correct. Does anyone know of a more explicit way to write this so Synplify can understand what I am trying to do? Thanks in advance, Joe LancasterArticle: 77483
gja wrote: > Tried that, but i get this warning message: > > Started process "Generate Post-Place & Route Simulation Model". > > WARNING:Anno:255 - command line '-s -4' overrides .pcf TEMPERATURE = 70.000 > C > This message is when you build the model? It looks like NGDanno is being invoked with -s -4 (change speed to 4) in the command line. If you run NGDanno from the process window in the ISE navigator I don't think you can turn this off. Maybe someone knows how to run this from a command line. Check out the Development System Reference Guide chapter 24 "NGDanno" in the online documentation. > > > > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message > news:345bivF47eeulU3@individual.net... > > > > "gja" <geeja@hotmail.com> schrieb im Newsbeitrag > > news:SQdDd.3214$yK7.3065@fe11.lga... > > > I want to do post place and route timing simulation on a Virtex2 part > > using > > > the Xilinx Modelsim starter simulator, how can I set the temperature > point > > > to 70 celcius? > > > > Add > > > > temperature=70C; > > > > to your UCF > > > > Regards > > Falk > > > > > > > > > >Article: 77484
Hello, and thank you all for your answers In my design i had 3 modules, each driven by the same clock and reset, all on the rising edge of the clock, processing states machines. I did change the clock of one of the module to have it on the falling edge (it was the middle module of the design) and it worked. Switching to Quartus 4.2 helped as well. Regards Nick On Thu, 6 Jan 2005 00:31:08 -0500, "Vaughn Betz" <no_spam@altera.com> wrote: >Hi Nick, > >It sounds like your reset is sometimes close to a clock edge, and hence skew >on it leads to some of your flops coming out of reset one cycle (or more) >before others. That leads to a bad reset, where the ones that come out of >reset early grab a bad next-state value based on a circuit state where some >FFs are still being held in reset, and some aren't. > >You should use Quartus' recovery and removal timing analysis feature to >check that the reset will bring all flops out of reset in the same clock >cycle, well away from an active clock edge. > >A good way to ensure that happens: > >- If all your logic is +ve edge-triggered, register your async reset signal >with a series pair of -ve edge triggered FFs. This avoids metastability, >and creates a synchronized reset that now changes well away from active >clock edges. Quartus will automatically route this reset signal on a global >network to minimize its skew. Its still best to run a recovery and removal >analysis though, since this is a timing constraint, and in my opinion you >should always check all your static timing constraints. > >Hope this is helpful, >Vaughn Betz >Altera >v b e t z (at) altera.com [remove spaces and use proper @ to reach me] > >"Nick" <char-DONTBUGME-les@YY.iiedotcnam.france> wrote in message >news:nkeft0p16he6k60fb2fnae6tood9gh3tt2@4ax.com... >> On Sat, 01 Jan 2005 20:03:24 -0600, hmurray@suespammers.org (Hal >> Murray) wrote: >> >> >>I have seen startup issues with state machines as well. >> >>Using synch state machines and asynch resets. Using >> >>Quartus 4 spX. A couple thoughts from what I read on Altera's >> >>website and just trying stuff. Make sure your state >> >>machine is using one-hot encoding, and define >> >>all states. This may solve random startup issue. If >> >>not try using a 3rd party tool like leonardo. (I think >> >>this ultimately fixed our issue. >> > >> >Async resets are evil. They are, well, asynchronous. Using >> >a one-hot state machine doesn't solve the problem. It might >> >reduce the probability (size of window), maybe even enough so >> >you won't see it easily. Are you running a few lab tests or >> >do you need a solid system? >> > >> >This gets discussed here frequently. The usual context is >> >the global reset signal that the hardware provides. It's slow >> >enough so that even if it is synchronous at the pins, it's probably >> >several clocks of prop time on high speed systems. (and hence >> >logically asynchronous) >> >> >> Well, basically for my test I use a switch for the reset, if it's at 1 >> the state machine should start, if it's at 0 the state machine should >> reset. I would really like to have a fairly long reset that I can >> control for my tests. And my clock is only 32 MHz >> As long as the design isn't too big it works. And after a certain >> amount of complexity it doesn't anymore >> >> Thank you for your answer, I shall try using Leonardo, and i'll keep >> you informed. >> >> Happy new year to you all >> >> Nick >Article: 77485
Hi All Sorry for this being slightly off-topic, but this was the closest group I could find. I need to configure a xilinx XC9536XL under linux. I've tried using naxjp, which can identify the CPLD correctly (sort of - it identifies it as being a cs48 when it actually is a pc44 ..), but when I try to program it I get $ ./naxjp -auto xc9536xv_pc44:/home/brian/projects/extensionboard/cpld/wiring.jed Device position 1. Command 'auto'. Partname 'xc9536xv_pc44'. File 'pc44:/home/brian/projects/extensionboard/cpld/wiring.jed' Plug-in file 'algxc95xl' not found. Device error:ISP algorithm is unknown for device 'xc9536xv_pc44' Elapsed time: 37 ms However the algxc95xl IS in the directory. Since all documentation is in japanese and the source code not available I'm pretty stuck here. Btw. this is running on a Suse 9.1 system. So my questions are: 1) Have anybody seen/solved this problem ? 2) Are there any other solutions at all for programming the CPLD under linux ? ((X)SVF files are not an option - I can't get impact from webpack 6.3 to run at all under wine, so I can't generate them) 3) Does anyone have the details of the programming algorithm for the xc9500xl devices or a link to it (I can't seem to find it in the manuals with enough detail, and xapp058 is of no help since SVF is out) ? I can parse the JEDEC file and I'm willing to do the necessary parport programming to get this to run. Hope someone can help - thanks in advance -- Brian Pedersen M.Sc.EEArticle: 77486
Hi all, I'm seeking your knowledge on some "attemptable" Master Project for a Computer Engineering student. I have done some courses on Digital Design, Verilog, Computer Architecture and Microprocessor Design. I'll love to try my hands on FPGA but I have no idea where to start. I've checked Xilinx site but had difficulty focusing on varieties of choices. I need some ideas on project that can be done in 4-5 months' timeframe, with next to none budgetry, not to mention skill and graduate level req... thanks, loisArticle: 77487
Nicholas Weaver wrote: > California is worse. Say a marginal fed of 25%, state of 9%, social > security and medicare of ~8%, and the marginal tax rate is pretty > high. Then add the >8% sales tax, the 1% property tax, and its quite > amazing just how poor the state government is with taxes as high as > they are. > California is absolutely outrageous. Be sure to throw in the car taxes onto what Nicholas just enumerated, and the fact that firearms have essentially been de facto outlawed. Unlike Europe, most public transportation alternatives here are a joke and there are no serious interurban transit alternatives which makes the prices for getting around comparable. That said, there is a buzz you can kind of feel in places like SJ, you're rubbing shoulders with some of the brightest people in the world - if you're at the right company. To the original poster, sounds like the pay is too low and the job doesn't deliver enough to you. I'd keep looking, and hope your current boss doesn't read comp.arch.fpga :)Article: 77488
Brian Drummond wrote: >>This discrepancy between >>the original grid and the placement grid is what causes problems when an >>RPM is not placed in the correct slice type. There are inherent problems >>anyway wrt shifting logic across CLB boundaries in something other than >>full CLB increments. > > > That may be part of what my test case is exposing. > > Incidentally I DID find a recommmendation to place RPMs such that they > began at R0C0 in the answers database ... but it went on to say "this > problem will be fixed in 4.2"! This sounds as though you've searched the Answer Archive and found an old obsolete Answer Record. If not and that's an active Answer Record please let me know what the number is. Some aspect of this problem probably was fixed in version 4.2. It's always a challenge to write an Answer Record that won't be misapplied to similar but different problems. Here's one that is applicable to your situation: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=17217 >>Yes, normalization needs to be taken into account even when there is >>only one component grid involved if you are using RLOC_ORIGIN. If you >>don't calculate an offset to compensate for normalization, then the >>macro won't get placed where you expect it. > > > Oh I calculate an offset. The problems are that the tools appear to > modify that offset in undefined ways or ignore them. I took a look at your test case and do agree that there is some unexpected behavior resulting from the normalization of your negative RLOC constraints. Focusing on the macro "I1/hset", You have a number of instances RLOC'd into column 0 beginning with X0Y0, so far so good. Then you have some instances RLOC'd to X-2Y8, X-4Y8 and X-5Y8. The first two don't cause a problem because they are S0 slices. The last one does cause a problem because it's an S3 slice and the normalization pushes every thing else into the wrong slice type. If I disable that RLOC with the following UCF constraint, the macro starts behaving like a good citizen again: INST "I1/int_delay1" USE_RLOC=FALSE ; # LUT2 at X-5Y8 > >>>Strictly speaking the placer ignores the MACRO LOCATE constraints >> >>The placer doesn't often ignore LOCATE constraints. It's more likely >>that you are just getting unexpected results because of the >>normalization issue. Note the difference between your RLOC_ORIGIN and >>the resulting LOCATE constraint. That difference is due to normalization. > > > Possible, but I would expect the placer report (.par) file to contain > "RESOLVED that <x> be placed at <y>" messages, but I only get 6 for 8 > constraints (this file is included in the testcase), and the > normalisation for the other two was X20Y22 and X18Y-12, for modules 6x9 > in size. Seems unlikely that this is just normalisation. > > The other 6 were placed within a couple of CLBs of the expected > location, I am trying to reconcile the differences with what you have > told me about normalisation. I looked at this and found a messaging issue. All eight macros were locked, but the "RESOLVED" messages only listed five of them. Note that there are three macros missing from that list and three macros that generate the following warning about alignment: WARNING:Place:206 - This design contains an RPM macro for which a specific alignment on the CLB grid was desired. The macro can not be aligned in this specific way. The placer will disregard this alignment. > >>>This may be the problem, but I don't see why the limitation exists. >>>Hand placement of the same components onto the other slice types (again, >>>excepting SRL16s in "odd X" locations) seems to work fine, though not >>>placement of RPMs. >> >>The best way to illustrate this is to manually place RPMs in FPGA Editor >>using different slice types. > > > part of this exercise has been to see how far I could get with the free > tools and the S3/1500, but now I'm convinced it's time to upgrade. I can understand that. I have a Linux PVR project going at home. Regards, BretArticle: 77489
Lois wrote:
> I'm seeking your knowledge on some "attemptable" Master Project
Consider a "completable" project.
> I have done some courses on Digital Design,
> Verilog, Computer Architecture and Microprocessor Design.
If you know verilog, consider a synchronous rtl design
and a simulation testbench to prove that it works.
> I'll love to try my hands on FPGA but I have no idea where to start.
Consider targeting your tested rtl code to
several FPGA devices using synthesis
and compare utilization and fmax, from
the synthesis reports. This will prove
that your code is portable without having
to build circuit boards.
-- Mike Treseler
Article: 77490Kadir Solid Gold Suleyman wrote: > firearms have > essentially been de facto outlawed. I don't understand this comment. All of my friends in San Jose and surrounding communities own multiple firearms-long guns and hand guns both. I can buy guns from at least 12 firearms emporiums less than 30 minutes from my house. Another though: With hundreds (if not thousands)of unemployed engineers in Silicon Valley, why is any employer trying to import a foreign engineer?Article: 77491
>I would like to assign TEMP value to RESULT at symbol_clk_edge and >reset TEMP to SAMPLE_IN value. The most important for me is to store >last value of TEMP to RESULT before resetting it. That sounds like you are thinking with your software hat on. In hardware, you want to do both on the same clock. I'd expect you would have a clock-enable for loading RESULT and you could use the same signal to on a mux in front of TEMP to force loading SAMPLE_IN_value rather than maybe keeping the old value. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 77492
Greg Lara wrote: > Another though: > With hundreds (if not thousands)of unemployed engineers in Silicon > Valley, why is any employer trying to import a foreign engineer? One of two things: the speciality pyramid, or the talent pyramid. It's still hard to find the best people. They all have jobs, and don't stay unemployed long... even in this environment. People with highly specialized skills don't stay unemployed long (unless there's no demand, which is a different problem). I would wager most of the unemployed valley people are either Web/VB/Java programmers, or just not very good. Harsh, but probably true.Article: 77493
Brian, Don't have a clue what the utility is of which you speak. But try "strace" to confirm exactly what file it is trying to open when it dies. Perhaps you will get some hints as to what and/or where (i.e. perhaps another directory) the program looking for that it doesn't find "it". Thanks, Steve Brian Dam Pedersen wrote: > Hi All > > Sorry for this being slightly off-topic, but this was the closest group > I could find. > > I need to configure a xilinx XC9536XL under linux. I've tried using > naxjp, which can identify the CPLD correctly (sort of - it identifies it > as being a cs48 when it actually is a pc44 ..), but when I try to > program it I get > > $ ./naxjp -auto > xc9536xv_pc44:/home/brian/projects/extensionboard/cpld/wiring.jed > Device position 1. Command 'auto'. Partname 'xc9536xv_pc44'. File > 'pc44:/home/brian/projects/extensionboard/cpld/wiring.jed' > Plug-in file 'algxc95xl' not found. > Device error:ISP algorithm is unknown for device 'xc9536xv_pc44' > Elapsed time: 37 ms > > However the algxc95xl IS in the directory. Since all documentation is in > japanese and the source code not available I'm pretty stuck here. Btw. > this is running on a Suse 9.1 system. So my questions are: > > 1) Have anybody seen/solved this problem ? > 2) Are there any other solutions at all for programming the CPLD under > linux ? ((X)SVF files are not an option - I can't get impact from > webpack 6.3 to run at all under wine, so I can't generate them) > 3) Does anyone have the details of the programming algorithm for the > xc9500xl devices or a link to it (I can't seem to find it in the manuals > with enough detail, and xapp058 is of no help since SVF is out) ? I can > parse the JEDEC file and I'm willing to do the necessary parport > programming to get this to run. > > Hope someone can help - thanks in advance >Article: 77494
vizziee@yahoo.com wrote: > Hi All, > > I am in search of some good references on FPGA implementation of > Order-Statistic CFAR (constant false alarm rate) detector in radars. > > If anyone has any idea or information, please send-in the references. > Thanx in advance. You might already be aware of these, but in case your not: Hu GuoRong Han LiTing Han YueQiu Mao ErKe Dept. of Electron. Eng., Beijing Inst. of Technol. , China; This paper appears in: ASIC, 1996. 2nd International Conference on Programming and development environments for configurable computing systems Kumar, S. Bhatt, D. Vestal, S. Wren, B. Shackleton, J. Shirley, H. Bhatt, R. Golusky, J. Vojta, M. Nanavati, C. Zumsteg, P. Symosek, P. Crago, S. Schott, B. Parker, R. Gardner, G. Honeywell Technol. Center, Minneapolis, MN, USA; This paper appears in: Aerospace Conference Proceedings, 2000 IEEEArticle: 77495
Make a move, come to california, best place on earth. Don't worry about salary, you will jump in a year - gauranteed for the skills that you are going to gain. For your reference here is the salary table in bay area for ASIC/FPGA/CKT designer 1-2 yr. from school : 55k to 65k 2-5 yy. exp, : 65k to 90k 5-7 yr : 90k to 105k 7yr to 11 yr : 105k to 135k -Purvesh pm940@yahoo.com wrote: > Greg Lara wrote: > > Another though: > > With hundreds (if not thousands)of unemployed engineers in Silicon > > Valley, why is any employer trying to import a foreign engineer? > > One of two things: the speciality pyramid, or the talent pyramid. > > It's still hard to find the best people. They all have jobs, and don't > stay unemployed long... even in this environment. > > People with highly specialized skills don't stay unemployed long > (unless there's no demand, which is a different problem). > > I would wager most of the unemployed valley people are either > Web/VB/Java programmers, or just not very good. Harsh, but probably > true.Article: 77496
> Unlike Europe, most public >transportation alternatives here are a joke and there are no serious >interurban transit alternatives which makes the prices for getting >around comparable. That said, there is a buzz you can kind of feel in >places like SJ, you're rubbing shoulders with some of the brightest >people in the world - if you're at the right company. Yes, the cost of living in Silicon Valley is silly. Yes, the commute sucks. But the comment about the "buzz" out here is important, at least to me. The downside is that you can easily get trapped in a workaholohic mode. The weather is generally good. Many people spend a lot of time outdoors, so you don't need as big a dwelling. This can offset a lot of the other costs if you like to hike/bike/whatever. If you have a family and want a big place to live you will probably have a long commute (which takes time from your family). If you are considering a job out here, I'd suggest coming out for a long weekend to check the place out. Talk to people face to face. Figure out where you are going to live and/or what to expect for a commute and/or what you are going to do in your non-work time. Commuting is generally horrible. (It will get worse if the economy improves.) If you live close enough (or are crazy enough) you can bike to work much/all of the year. (Living close costs big $. Biking saves big $.) Yes, the public transportation is not great. On the other hand, CalTrain isn't that bad if it goes where you want to go. I have friends who take it to/from Silicon Valley to San Francisco. CalTrain is bicycle friendly. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 77497
Hi, Austin. Thank you for your description of the three families. This confirms what I've heard before. I've checked out about the first 200 links yielded by Google when searching for 'xilinx hardwire'. Every one is about the most recent gate-array based family. The first two families seem to be hard to track down. My patent laywer is asking me for public documents on the first two families, since these are considered strong prior art in the structured ASIC market. Unfortunately, these families were gone before the web took off, so there was never any on-line docs, so Google hasn't helped me. Of course, the devices themselves can still be found, and that's technically enough. Thanks, BillArticle: 77498
It would be easier to compare netlist output files. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "Jansyn" <jansynf@worldnet.att.net> wrote in message news:h4xDd.76363$uM5.73317@bgtnsc05-news.ops.worldnet.att.net... > Hello, > I am running Xilinx ISE software to do a schematic > based FPGA design. Are there any tools to show the > differences between 2 version of a schematic? > I can diff the .sch files and get hints as to what > has changed, but I was looking for a graphical tool > to see the schematics. > > Any suggestions? > > Thanks, > Ben J > >Article: 77499
Brian Dam Pedersen <brian.pedersen@mail.danbbs.dk> wrote: > Hi All > Sorry for this being slightly off-topic, but this was the closest group > I could find. > I need to configure a xilinx XC9536XL under linux. I've tried using > naxjp, which can identify the CPLD correctly (sort of - it identifies it > as being a cs48 when it actually is a pc44 ..), but when I try to > program it I get > $ ./naxjp -auto > xc9536xv_pc44:/home/brian/projects/extensionboard/cpld/wiring.jed > Device position 1. Command 'auto'. Partname 'xc9536xv_pc44'. File > 'pc44:/home/brian/projects/extensionboard/cpld/wiring.jed' > Plug-in file 'algxc95xl' not found. > Device error:ISP algorithm is unknown for device 'xc9536xv_pc44' > Elapsed time: 37 ms > However the algxc95xl IS in the directory. Since all documentation is in > japanese and the source code not available I'm pretty stuck here. Btw. > this is running on a Suse 9.1 system. So my questions are: Is is a 95xl versus 95xv Problem. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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