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Jim Granville wrote: (snip about benchmarks and lies, not that benchmarks have ever done better than that. Remember MIPS... Meaningless Indicator of Processor Speed.) > Then you need another class of benchmarks, that ARE public ? > If you look at the EEBC (sp?) Embedded controll benchmarks, they also > extend the meaning of benchmarks by having TWO columns. > a) = "out of the Box" = Std tools, Compilers, not hand level > tuned in assembler, or using special HW fabric. > b)"Optimised" = Experienced designer, hand optimised Assembler,and > using all relevant special HW fabric. > Not surprisingly, there can be 10:1 or 100:1 between a) and b) > So, how about making some PUBLIC simple candidate benchmarks ? I thought about this some years ago, what is needed is a scalable benchmark that can adjust to the size of the FPGA. At the time I don't think it was very practical, but it might be better now. FPGAs are bigger, so the error due to requiring a whole number of units to fit is smaller. One possibility could be an N bit processor where N is adjusted as appropriate. Another is N of your favorite vendor independent processor, the smaller the better. For each device N is adjusted to maximize the product of N and the speed, thus balancing routing effects. (If you pack too much in the routing can slow down the logic.) Other scalable design ideas could be offered. -- glenArticle: 78601
Hello Spehro, >The motivation is green (at least the US version is) and there is lots >and lots of it to be had. > > It might not always pan out that way. I am just transitioning to a European CAD program so the green flows in the other direction. They didn't outsource it and still had the best pricing. Regards, Joerg http://www.analogconsultants.comArticle: 78602
I hope nobody wants to repeat the PREP experiment, killed -as most people would agree- by the devious tricks of a certain company, not dear to my heart. :-( But think for just a moment: Today, there really are only two serious contenders X and A. the rest are niche players, and getting smaller every year. Now imagine that there were a universal, scientific, believable, accurate set of benchmarks. I would hope that Xilinx wins, but that would be the end of Altera. The other way round, it would spell the end of Xilinx. Nobody really wants either of that to happen, least of all the users. They actually want biodiversity, for several good reasons. Competition sees to it that the two main players have comparable qualities, otherwise one of them goes down, and the other one goes up. The better one becomes or stays #1, the lesser one becomes or stays #2. That's the way Xilinx and Altera have ranked for many years. Altera has a stable %PLD market share in the lower 30s(now 34%), Xilinx moved up from the high 30s to now 52% PLD market share. That's the result of good products and happy customers, not of benchmarks! Capitalism has some advantages, you cannot fool the market in the long run. The only people benefitting from benchmark wars are the marketing and sales departments of the two FPGA houses. For the rest of the community, it's a silly circus. Well, some people enjoy a bloody circus... Nero did. Peter AlfkeArticle: 78603
Peter Alfke wrote: > I seldom have serious issues with Paul (he is not part of their local > marketing snakepit anyhow) and I will not have a dirty fight with him. > Altera had skewed the benchmark results in their favor by comparing > their fastest against our middle speed grade (I know that our fastest > speedfiles were not yet public, but that is a poor excuse if you want > to create benchmarks for the benefit of the public. Learn from tennis, > where you don't surprise a temporarily not-yet-ready opponent !) > Altera also did not use the Xilinx software the way a user interested > in top performance would use it. And bingo: +39% ! > No lies, just cheats. > The stable of designs is naturally different in the two companies. And > they are not public... <snip> Certainly seems "benchmarks" should now include a date (and time!) - [Remember the days when you could just specify a Device family... :)] I see Altera have just anounced updated Speed and Power Parameters too, on their devices. http://www.altera.com/corporate/news_room/releases/products/nr-perf_power.html Claims of +20% on Max speed, -45% on static Power, and no inrush... Xilinx will, of course, include these 'still warm' numbers in their V4 Power comparisons comming soon... -jgArticle: 78604
On Fri, 04 Feb 2005 01:34:47 GMT, the renowned Joerg <notthisjoergsch@removethispacbell.net> wrote: >Hello Spehro, > >>The motivation is green (at least the US version is) and there is lots >>and lots of it to be had. >> >> > >It might not always pan out that way. I am just transitioning to a >European CAD program so the green flows in the other direction. They >didn't outsource it and still had the best pricing. > >Regards, Joerg > >http://www.analogconsultants.com Do you know that for a fact? A while ago I was talking to some developers who worked with their company's "European" team on a large software project- in St. Petersburg Russia. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 78605
Peter Alfke wrote: > I hope nobody wants to repeat the PREP experiment, killed -as most > people would agree- by the devious tricks of a certain company, not > dear to my heart. :-( > But think for just a moment: > Today, there really are only two serious contenders X and A. the rest > are niche players, and getting smaller every year. Now imagine that > there were a universal, scientific, believable, accurate set of > benchmarks. > I would hope that Xilinx wins, but that would be the end of Altera. The > other way round, it would spell the end of Xilinx. Why/how ? The rationale here has me lost... There is plenty of diversity in the marketplace, and users are not so silly as to buy purely on one benchmark. Look at http://www.eembc.hotdesk.com/ - there are a lot of uC/iP listed, and they are not fearfull that comming 2nd in some benchmark will be the kiss of death ? Also look at the uC markets - some of the biggest $$ do not come from the fastest, or smartest, devices. > Nobody really wants > either of that to happen, least of all the users. They actually want > biodiversity, for several good reasons. > Competition sees to it that the two main players have comparable > qualities, otherwise one of them goes down, and the other one goes up. > The better one becomes or stays #1, the lesser one becomes or stays #2. > That's the way Xilinx and Altera have ranked for many years. Altera has > a stable %PLD market share in the lower 30s(now 34%), Xilinx moved up > from the high 30s to now 52% PLD market share. That's the result of > good products and happy customers, not of benchmarks! > Capitalism has some advantages, you cannot fool the market in the long > run. > > The only people benefitting from benchmark wars are the marketing and > sales departments of the two FPGA houses. For the rest of the > community, it's a silly circus. > Well, some people enjoy a bloody circus... Nero did. > Peter Alfke You have missed another important function of PUBLIC benchmarks, and that is code & design training. Users can see generic and optimal source files, and learn a _lot_ from that. If the word benchmark has such a strong, averse reaction, then think of them as portable application notes with numbers ? :) -jgArticle: 78606
C'mon, Jim. You cannot be serious. There is no dearth of learning and training material. Xilinx publishes many hundreds of app notes (now often with code examples), there are reference designs, evaluation boards, and the User Giudes have thousands (!) of pages. And Altera does the same. There is plenty of learning material. But we do not need the artificial title "benchmark" that implies objectivity (without ever living up to it). PeterArticle: 78607
Thomas and Ben, thank you for your answers. >Quartus will attempt to meet timing, and will stop when it reaches timing or >after a number of iterations hasn't found a workable solution (after which >you will see errors in the timing report). I am pretty sure that if you set >the PLL to output 36MHz, you will reach this performance. I have already tried that and, you are right, I' ve achieved that fmaxvalue. >But why do you think that 33.1 MHz is not OK when you need 33MHz? My only fear is that, due to a possible Quartus underestimation of max delays (it is an old release), that margin (about 100 ps) could be not enough. The design includes an vhdl IP core and associated scripts (for Quartus 3.0) and, in the past, Quartus newer releases had problems when reading directives written for older ones. Again, thanks.Article: 78608
>Another is a safety-related reset, perhaps in a motion control system, >where you >need the reset to halt motion and cause an emergency stop, even if the >clock were >to fail. I have something like this in some of my designs. The >external, analog-based >one-shot watchdog timer will cause an e-stop even if the clock to the >FPGA has >gone static. I don't have any problem with an asynchronous release of >this reset, >in this case. it could cause a problem with a simulation, but it won't >cause any >problem in the actual application. The worst case is one more >millisecond before >the e-stop condition ends. I missed something. This is a safety critical application. Why aren't you concerned about coming out of asynchronous resets? [It's one of my hot buttons. I learned the hard way.] -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 78609
>4)SoftCPUs : SoftCPUs are advancing, and there are public cores out there. > This gets more political, as these make very good benchmarks, but >IC vendors would much rather lock customers into their own SoftCPU, >so do not want to publicise any alternatives. Might be worth it for a vendor to use a public core due to reduced support on the software. Gnu tools are pretty good. Once somebody gets them over the hump, the vendor might not need to do much support. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 78610
Spehro Pefhany wrote: > Do you know that for a fact? A while ago I was talking to some > developers who worked with their company's "European" team on a large > software project- in St. Petersburg Russia. That part of Russia belongs to the old definition of Europe, and most of them wants to join the European Union, because in the European Union it is forbidden to discriminate work. I think it is more a question what the salary is compared to level and quality of education. Many of the former east-block countries have exellent engineers and they are not so expencive as the western-european engineers. It is such a pity that most of the politicians who put up the legal framework for globalization never had to face competition on uneven levels -- SvennArticle: 78611
Hello, To interfacing DDR memory module to memory controller, I'm finding DDR SDRAM SODIMM socket. (Not memory module). I tried to search serveral socket & connector vendors like MOLEX, AMP. , but only SDRAM SODIMM and DDR DIMM are available in their catalog. Does anyone know the vendor and part number? Regards, S.H, LeeArticle: 78612
I used FLEX8000 device and developed with MAX2+. For poor performance, altera produced advanced synthesis tool as I know. Synthesis tool name is 'Altera Max+plus II advanced synthesis'. It is download free, but you may feel hard to find it from altera web site. :-) Regards, S.H, Lee "Vincent Perron" <vincent.perron@usherbrooke.ca> wrote in message news:8290822c.0502021107.6689e006@posting.google.com... > Here's a question I know has already been asked but I was not > satisfied with the answer. > > How could I get Quartus II to support the FLEX 8000 devices? > > I've already got a couple of FLEX 8000 chips and a complete version of > Quartus II 4.1. All the FLEX family is supported (6000, 10K, 10KA and > 10KE) except for the 8000. > > Is there a way to add the FLEX 8000 to this list? I would really > prefer working with Quartus II than Max Plus II. > > thx, > VincentArticle: 78613
On Fri, 04 Feb 2005 09:32:11 +0100, the renowned Svenn Are Bjerkem <svenn.are@bjerkem.de> wrote: >Spehro Pefhany wrote: > >> Do you know that for a fact? A while ago I was talking to some >> developers who worked with their company's "European" team on a large >> software project- in St. Petersburg Russia. > >That part of Russia belongs to the old definition of Europe, and most of >them wants to join the European Union, because in the European Union it >is forbidden to discriminate work. > >I think it is more a question what the salary is compared to level and >quality of education. Many of the former east-block countries have >exellent engineers and they are not so expencive as the western-european >engineers. Yes, I believe that Western Russia (and Western Turkey, for that matter) is European in culture. In this case, there was a deliberate attempt to make it look like the work was done in Germany without actually lying. Kind of like saying "North American" and giving a North Carolina US address, but doing the bulk of the work in Cuba or Honduras. >It is such a pity that most of the politicians who put up the legal >framework for globalization never had to face competition on uneven levels I imagine that they are indirectly profiting from it. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 78614
I read in sci.electronics.design that Svenn Are Bjerkem <svenn.are@bjerkem.de> wrote (in <ctvbub$afc$1@athen03.muc.infineon.com> ) about 'Exportability of EDA industry from North America?', on Fri, 4 Feb 2005: >It is such a pity that most of the politicians who put up the legal >framework for globalization never had to face competition on uneven >levels They did , but their levels were the highest! -- Regards, John Woodgate, OOO - Own Opinions Only. The good news is that nothing is compulsory. The bad news is that everything is prohibited. http://www.jmwa.demon.co.uk Also see http://www.isce.org.ukArticle: 78615
Hal Murray wrote: >>4)SoftCPUs : SoftCPUs are advancing, and there are public cores out there. >> This gets more political, as these make very good benchmarks, but >>IC vendors would much rather lock customers into their own SoftCPU, >>so do not want to publicise any alternatives. > > > Might be worth it for a vendor to use a public core due to reduced > support on the software. Gnu tools are pretty good. Once somebody > gets them over the hump, the vendor might not need to do much support. True, could be a solution for Actel or Lattice ? It does not seem that Xilinx are PREPared to do public 'pushed case' examples so users can do their own measurements, and given the 'half lifes' of the Speed Files of FPGAs, that is looking important. If we cannot trust the vendors marketing depts to match like with like, seems the info flow should come from the engineerings depts ? Maybe Altera could start ? -jgArticle: 78616
On Fri, 04 Feb 2005 16:16:19 +1300, Jim Granville <no.spam@designtools.co.nz> wrote: >There is plenty of diversity in the marketplace, and users are not >so silly as to buy purely on one benchmark. > >Look at http://www.eembc.hotdesk.com/ - there are a lot of uC/iP listed, >and they are not fearfull that comming 2nd in some benchmark will be the >kiss of death ? EEMBC isn't public; the sources cost ~ $30K. This makes it pretty much useless, because only the processor vendors buy in, and there's no obligation to publish results. The average user can't run a benchmark on two different systems, and it's in the user's system that performance really counts. Another issue with benchmarks is that vendors simply target their processor/FPGA/whatever at the benchmark. It would be relatively easy for an FPGA vendor to increase performance on a known benchmark, either by targetting their software at it, or by introducing dedicated hardware in the next device. In the long run, everybody loses. Besides, how many FPGA end-users actually buy on raw performance? Very few, I suspect, and they're probably the ones who are targetting ASICs anyway. EvanArticle: 78617
Hey, I made a user ip and want to use it in EDK off course, so i added it to the pcores directory, wrote an MPD\tcl\pao file and it found the ip in the add/change cores window ... so i added it to the PBD and filled in the right parameters ... but when i want to build the netlist, i get the follow error message: C:\EDK_SDK_workspace\RadPad_test\system.mhs:778 - Running XST synthesis ERROR:HDLParsers:3317 - C:/EDK_SDK_workspace/RadPad_test/synthesis/../hdl/plb_ddr_rp_1_wrapper.vhd Line 28. Library plb_ddr_rp_v1_11_a cannot be found. ERROR:HDLParsers:3014 - C:/EDK_SDK_workspace/RadPad_test/synthesis/../hdl/plb_ddr_rp_1_wrapper.vhd Line 29. Library unit plb_ddr_rp_v1_11_a is not available in library work. ERROR:MDT - HDL synthesis failed! INFO:MDT - Refer to C:\EDK_SDK_workspace\RadPad_test\synthesis\plb_ddr_rp_1_wrapper_xst.srp for details ERROR:MDT - platgen failed with errors! make: *** [implementation/plb_ddr_rp_1_wrapper.ngc] Error 2 Done. What could i have done wrong? thanx in advance for your help ... kind regards Tim Verstraete tim.verstraete@barco.comArticle: 78618
Hello, I'm interested in high Speed Designs (450MHz to 500MHz). The advertising of Xilinx states, that the Virtex4 can be clocked up to 500HMz. I guess this is only possible using Devices with speedgrade 12. I wanted to evaluate the Virtex4 using ISE Foundation 6.3i. Unfortunately only devices with speedgrades 10 and 11 can be selected. If I try to instanciate a DCM_ADV using the Wizard, it is stated, that the maximum frequency that can be generated is 315MHz. Is that because of the given speedgrades? Can the 500MHz be generated in a device of speedgrade 12? Is it possible at all to generate 500MHz with a DCM or is it necessary to use an external 500MHz clock? Is there a chance to get a pipelined structure with one logic level per stage implemented implemented with 450 to 480MHz if I buy an evaluation boord with a device of speedgrade 10 supplying an external clock? Could I cool down the device and increase to core voltage in order to achive this performance? Which parts of the Virtex4 can be clocked with 500MHz? Only the XtremeDSP cells? Were do they get their clock from? Can logic be clocked with 500MHz at all? Thank you for your answers! Regards, MatthiasArticle: 78619
I'm working with "Excalibur Stripe Simulator" (ESS) in order to simulate
the stripe conected to my vhdl design (software-hardware simulation).
This design includes my coprocessor and alt_exc_stripe entity which is
included in the alt_exc_stripe_ess.vhd file, the path of this file is:
$QESS_ROOTDIR/eda/sim_lib/excalibur/lpm. In adition, I have included in the
ModelSim project the file ess_hdl including alt_exc_upcore entity.
I have created the ess_options.txt file with the desired options and
the memory inicialization file (MIF) (using Quartus II software). Both
files are included in the simulation directory.
I have configured AXD Debugger as the user guide explains. In the
ModelSim software, I have run alteradebugger.do macro, compiled the
files and loaded my design. Finally, I have run modelsim with -all
options. The console (in the ModelSim) shows:
info:waitin for connection from software debugger
simulation halt requested by foreign interface
After that, I have opened and configure AXD Debugger, it shows:
info:Logic simulator conection successful
and then, the ModelSim accepts software debugger conection.
>From AXD Debugger, when I press the "go" button, the modelsim screem shows:
simulation halt requested by foreign interface
run -continue
This message is shown a lot of time and then I can not control the debugger.
Do yo have any idea about the reason why this problem appears?
Thank you
Sincerly
Article: 78620Hi Gabor, Did you remember how to do it? Do you have example code? I don't understand the inputs and outputs in the example that I posted above. Is it true that all I need is to put an instance of BSCAN in the code?Article: 78621
SeungHeun, Lee wrote: > Hello, > > To interfacing DDR memory module to memory controller, I'm finding DDR > SDRAM SODIMM socket. (Not memory module). I tried to search serveral socket > & connector vendors like MOLEX, AMP. , but only SDRAM SODIMM and DDR DIMM > are available in their catalog. > Does anyone know the vendor and part number? > look at AMP 1473005-1 > Regards, > S.H, LeeArticle: 78622
Hi Matthias, In my honest opinion, even with FX series, 450 to 500 MHz. will be extremely difficult to achieve. For 500 MHz. , I would recommend using external low jitter clock. Check DCM's jitter spec and see if that is tolerable to you, else stick with epson clk driver. Also differential clock driver is that you are looking at those frequencies. As far as advertised speeds of 500 MHz. it might be achievable on their DSP family of devices especially their hard DSP macros. As far as your other question, about cooling the device and increasing core voltage to run at higher clock frequencies, you might possibly damage the device. Check with Xilinx about it. Make sure you are talking to right FAE about such issues to get correct answer. Finally I would shoot for 300 to 350 Mhz. max with FPGAs. However most of it will depend on the size of design and part selected. Larger the part, more likely you will have trouble hitting the frequencies. Regards, Purvesh Matthias M=FCller wrote: > Hello, > > I'm interested in high Speed Designs (450MHz to 500MHz). The advertising of > Xilinx states, that the Virtex4 can be clocked up to 500HMz. I guess this is > only possible using Devices with speedgrade 12. > > I wanted to evaluate the Virtex4 using ISE Foundation 6.3i. Unfortunately > only devices with speedgrades 10 and 11 can be selected. If I try to > instanciate a DCM_ADV using the Wizard, it is stated, that the maximum > frequency that can be generated is 315MHz. Is that because of the given > speedgrades? Can the 500MHz be generated in a device of speedgrade 12? > > Is it possible at all to generate 500MHz with a DCM or is it necessary to > use an external 500MHz clock? > > Is there a chance to get a pipelined structure with one logic level per > stage implemented implemented with 450 to 480MHz if I buy an evaluation > boord with a device of speedgrade 10 supplying an external clock? Could I > cool down the device and increase to core voltage in order to achive this > performance? > > Which parts of the Virtex4 can be clocked with 500MHz? Only the XtremeDSP > cells? Were do they get their clock from? Can logic be clocked with 500MHz > at all? >=20 > Thank you for your answers! >=20 > Regards, > MatthiasArticle: 78623
Anybody has an idea why the NIOSII 1.1 toolchain build fails on Linux/BSD systems with: *** ld does not support target nios2-elf *** see ld/configure.tgt for supported targets make: *** [configure-ld] Error 1 Somehow it looses "nios2-unknown-elf"... It builds fine on Win2k under Cygwin... rickArticle: 78624
I get this warning: WARNING:NgdBuild:440 - FF primitive 'XLXI_7_XLXI_1/BU199' has unconnected output Who can i locate this pin and fix the problem ?
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