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Giani wrote: > I get this warning: WARNING:NgdBuild:440 - FF primitive 'XLXI_7_XLXI_1/BU199' has unconnected output > > Who can i locate this pin and fix the problem ? You may be able to locate it down to the COREgen module it's in, but unlikely to "fix" the problem. I generally ignore these messages. Very informative names starting with BU are a mark of Xilinx COREgen designs. These often end up with unconnected innards that are ripped out at mapping time. One thing that can cause this is generating odd width FIFO designs using block RAM (e.g. using 27 bits of a 36-bit block RAM). The problem with trying to fix this is that you can't easily modify the internals of the COREgen module, so if you can't find the right settings to generate a module without the errors you might as well live with the warnings.Article: 78626
Hello
For some reasons I have an IP with bidirectionnal IOs that is
instantiated inside a higher level wrapper and that I can't modify. The
proble is that the wrapper inserts some logic between an IO bus of the
IP and the actual chip IOs.
It seems that QuartusII (4.2) produces garbage from my VHDL. How can I do?
The problem is that int_bus is x"FF" when en = '1', instead of int_bus_in.
Sample code :
entity wrapper is
port (
io_bus_1 : inout std_logic_vector(31 downto 0);
io_bus_2 : inout std_logic_vector(31 downto 0);
... );
end entity wrapper;
architecture str of wrapper is
signal en : std_logic;
signal int_bus_in : std_logic_vector(7 downto 0);
signal int_bus_out : std_logic_vector(7 downto 0);
signal int_bus : std_logic_vector(7 downto 0);
component ip is
port(
io_bus_1 : inout std_logic_vector(7 downto 0);
io_bus_2 : inout std_logic_vector(7 downto 0);
ctrl : out std_logic;
... );
end component ip;
begin
ip_inst : ip
port map (
io_bus_1 => int_bus,
io_bus_2 => io_bus_2(7 downto 0),
ctrl => en,
... );
int_bus_out <= int_bus;
int_bus <= int_bus_in when en = '1' else (others => 'Z');
end str;
--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
Article: 78627John Woodgate wrote: >>It is such a pity that most of the politicians who put up the legal >>framework for globalization never had to face competition on uneven >>levels > They did , but their levels were the highest! Given the statistics of politician population, that statement smells of racism and sexism.Article: 78628
Hello, I'm working on a simple hardware design lab - Microblaze.When I start a new project with BSB in Xilinx Platform Studio(XPS)and select target development board I face a problem. The board which I have is Spartan-3 and the lab exercise is based on Spartan-3. But the software 6.2i which i have in system does'nt show all the xilinx board names. When i select Xilinx in the board vendor, it shows only 2 names in Board Names(AFX Virtex and Virtex II). I wish to select Spartan-3 which isnt there. how to include Spartan-3? Could anyone please help me. Thank youArticle: 78629
As I mentioned in the seminar, 500 MHz is achievable in most blocks, but a complete 500 MHz system may be tough to put together, since it means that you must never loose even a fraction of a ns. If Matthias needs 500 MHz, I invite him to send me some specific ideas and requirements, so we can take a look at the feasibility. I tried to mail him directly, but his e-mail address is camouflaged. Peter Alfke, Xilinx Applications peter@xilinx.comArticle: 78630
Hi , I hope somebody else has had the same problem.... I am currenlty migrating some software from an XC3400-4PQ208 to a SPARTAN-3 XC3400-4TQ144. The software and everything is running perfectly in the previous spartan. I have created a new project for the TQ144 and synthesised it without any error. However, when I run the PACE software to assign the pins, the Design Rule Check gives me lots of errors with the same legend "The bank number specified does not exist", It is worth to note that I am not assigning the bank, I am assigning a pin and PACE selects the Bank by itself. The bank for each case is correct though, I have double checked the data sheets and the pins are currently assigned to a correct bank. If I dont pay attention to this errors and try to generate the programming file , the bitgen generates an error without reason. I have tried to disselect the option of "Run Design Rules Checker" under the general options for generate programming files. Then, the bitgen doesn't give any error but I am afraid this is causing my FPGA to be incorrectly programmed since no input/outputs are working... do you have any idea what can i do in this case? My Project Navigator and PACE's versions are 6.01.3i... thank you SergioArticle: 78631
Peter Alfke wrote: (snip) > But think for just a moment: > Today, there really are only two serious contenders X and A. the rest > are niche players, and getting smaller every year. Now imagine that > there were a universal, scientific, believable, accurate set of > benchmarks. > I would hope that Xilinx wins, but that would be the end of Altera. The > other way round, it would spell the end of Xilinx. Nobody really wants > either of that to happen, least of all the users. They actually want > biodiversity, for several good reasons. > Competition sees to it that the two main players have comparable > qualities, otherwise one of them goes down, and the other one goes up. Besides all the problems that benchmarks have, I don't believe everyone has the same design goals. Some systems need to be as fast as possible, others as dense as possible, and some in between. What I would like to see is a series of devices in similar sizes, but varying in the special purpose blocks. Two popular additions are hardware multipliers and block RAMs. Some designs use more of one or the other, some less. A designer may know early in the design process which of those will be needed. Consider a family of devices of similar size, but varying in the two dimensional space of number of hardware multipliers and block RAMs. That would probably depend on the ability at mask generation time to substitute a multiplier or RAM for a set of CLBs in an automated fashion, and for routing software to follow those changes. Those within a family should be otherwise pin compatible. Given such a family of devices, it is unlikely that benchmarks would show all equally useful. Benchmarks for devices with CPU logic inside would be even worse. -- glenArticle: 78632
Hi Peter, Can you tell us eagerly awaiting the -12 Virtex4 devices when we can expect them to be available in ISE? I've heard that they will be in ISE 7.1, but have not had it confirmed. Thanks, KevinArticle: 78633
A few additional comments: LX, SX and FX inherently have the same speed for a given speed grade. (LX and SX are just a different mix of identical functions, "gin&tonic vs. tonic&gin", FX adds PPC, MGT and EthernetController to it.) In many cases, we are quite conservative. I know that the DSP core runs much faster than 500 MHz, and so might the BRAM. For a production design, that does you no good, the part "is" only as fast as the vendor guarantees. But if you want to tinker, you might be surprised. Keeping Vcc at the high end (but stay within spec!) helps a few %, and so does a heatsink, to keep the junction temperature below the specified max 85 degree limit. I am always interested in designs that challenge the max performance. When I joined Xilinx 17 years ago, I designed a 40 MHz counter. You cannot imagine the logic contortions required to do that in an XC3020. Now I'm thinking of (ab)using the MGTs to count up to 5 GHz, and also to do frequency synthesis up to 5 GHz. Maybe later this year...It helps to think ahead. :-) Peter Alfke, Xilinx ApplicationsArticle: 78634
A free C compiler for Picoblaze is ready to be tested(used!) Ver.alpha1.1.4 is ready and seems bug free. If you want to program in C with Picoblaze, send me an email I'll send you the compiler asap. User manual is partially written. few example for spartan2/3 are available! program in C and avoid the pain of assembler!! FrancescoArticle: 78635
Phillipp,
If you have synthesized your pcore with Mentor Precision, you can
bring it into EDK as a blackbox. Use
OPTION STYLE = BLACKBOX
and add a BBD file instead of a PAO in the datadirectory. This way,
platgen won't synthesize the IP again and will take the netlist created
beforehand.
Amit.
Philipp Grabher wrote:
>We designed an own IP, which performs some specific ALU operations. We have
>added it to the FSL interface of the microblaze core. Everything worked
>properly, but now I have extended the ALU with a root and cubic operation.
>When I now try to run the synthesis in EDK I get an fatal error with no
>further information
>
>Error Message:
>---------------------------------------
>Generating synthesis project file ...
>
>Running XST synthesis ...
>INFO:MDT - The following instances are synthesized with XST. The MPD option
>IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
>synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. A
>batch
>file, synthesis.sh, has been created that allows you to synthesize those
>instances in your specified synthesis tool of choice.
>fsl_ff3_0_wrapper (fsl_ff3_0) - C:\FF3_Arithmetic\FF3_ALU\system.mhs:133 -
>Running XST synthesis
>FATAL_ERROR:MDT:Portability/export/Port_Main.h:127:1.53 - This application
>has discovered an exceptional condition from which it cannot recover.
>Process will terminate. To resolve this error, please consult the Answers
>Database and other online resources at http://support.xilinx.com. If you
>need further assistance, please open a Webcase by clicking on the "WebCase"
>link at http://support.xilinx.com
>make: *** [implementation/microblaze_0_wrapper.ngc] Error 1
>Done.
>
>As I said everything was working properly until I added two new HDL files to
>my IP module. The compilation and simulation looks fine of these files so
>there shouldnt be anything wrong with them. I used Mentor Graphics Precision
>RTL Synthesis and there my whole module was synthesised without any error
>messages. I also added this two files to my .pao file. I use EDK 6.2.03i.
>
>Anyone encountered a similar problem and has some advice what could be
>wrong? Unfortunately I cant find anything on the Xilinx Homepage for this
>kind or error
>
>Best Regards
>Philipp
>
>
>
>
Article: 78636Anyone who has used the Power PC cores on Xilinx FPGAs has undoubtedly paid some dues... I selfishly ask if anyone has compiled a quick set of recipes, lessons-learned, or other guides for *quickly* getting up to speed on using these. There is no shortage of documentation available, especially from Xilinx. The problem (in classic Xilinx style) is that I don't have all year to read it. Thus, any pointers to the most-recommended, quickly-effective reading material would be appreciated. Specific scenario and questions: 1) I will soon have a board (with V2P30) on it. I wasn't originally planning to use the PPC, so no buses were routed for external memory. Hope to use on-chip memory only, now that I have a use for the PPC... 2) My tool set includes Mentor ModelSim, Synplicity (Synplify Pro), and Xilinx ISE. Do I need other $non-free$ tools in order to use the PPC? (i.e., Xilinx EDK, etc...) 3a) I first want to instantiate one PPC, load some instructions in memory via ModelSim, tie the PPC core to the rest of the FPGA fabric, and simulate enough instructions to make sure the flow works. 3b) Next, I'd like to create some real short test programs, compile them with gcc (no RTOS required, but if easy to configure and use, that's a bonus), load the memory image (via ModelSim) and simulate. 4) Load the PPC memory instruction via the bitfile when I power up the real hardware, have the PPC boot and start running my code when I toggle an input, so I can watch some outputs toggle on a scope. (Eventually this board will serve as a stimulus/waveform generator for another board.) 5) Where might I find an appropriately configured copy of gcc and libraries? That's it in a nutshell. I don't expect this to be a one-weekend project, but I don't have all year either. C code, VHDL code, Synplicity scripts, etc... for getting up to speed fast would be ideal. Thanks very much for *any* help you can provide. mjArticle: 78637
Hello Spehro, >>It might not always pan out that way. I am just transitioning to a >>European CAD program so the green flows in the other direction. They >>didn't outsource it and still had the best pricing. >> >> >Do you know that for a fact? A while ago I was talking to some >developers who worked with their company's "European" team on a large >software project- in St. Petersburg Russia. > > Sure, as a customer thousands of miles away you may not know for sure. But there is one telltale sign that pops up when you have a tough question. That will often require the original programmer or designer to answer. Accents are really hard to hide. Like with a graphics card manufacturer in Canada. When I got answers such as 'that's aboot right' or I heard 'Bonjour' I somehow knew it's got to be Canada ;-) Regards, Joerg http://www.analogconsultants.comArticle: 78638
"What I would like to see is a series of devices in similar sizes, but varying in the special purpose blocks. Two popular additions are hardware multipliers and block RAMs. Some designs use more of one or the other, some less. A designer may know early in the design process which of those will be needed. " Sounds like a description of the ASMBL architecture of Virtex-4, where LX and SX differ in the percentage mix of functions, SX having relatively more multiplier/accumulators and BlockRAMs, otherwise the functions are identical. Seems like we are getting there. Just remember, any different chip is a multi-million dollar investment by the manufacturer... Peter AlfkeArticle: 78639
[ Apologies if this is a frequently asked question but I've been googling for hours and haven't found much info. ] I'm looking to buy a Spartan-3 Starter Kit:- http://www.xilinx.com/products/spartan3/s3boards.htm# in the UK. The only supplier in the UK with a website is nuhorizons.com and I've seen some warnings about using them. I'll give Xilinx UK a call tomorrow (or Monday) but I'm wondering if anyone has any suggestions for suppliers I can check with. Or how quick/expensive is it to order from the US and deliver to the UK. Which suppliers would you recommend? Ta, -AlexArticle: 78640
Evan Lavelle wrote: > On Fri, 04 Feb 2005 16:16:19 +1300, Jim Granville > <no.spam@designtools.co.nz> wrote: > > >>There is plenty of diversity in the marketplace, and users are not >>so silly as to buy purely on one benchmark. >> >>Look at http://www.eembc.hotdesk.com/ - there are a lot of uC/iP listed, >>and they are not fearfull that comming 2nd in some benchmark will be the >>kiss of death ? > > > EEMBC isn't public; the sources cost ~ $30K. This makes it pretty much > useless, because only the processor vendors buy in, and there's no > obligation to publish results. The average user can't run a benchmark > on two different systems, and it's in the user's system that > performance really counts. What you mean is it is not free. That is their busines model, EEMBC are there to make money. > Another issue with benchmarks is that vendors simply target their > processor/FPGA/whatever at the benchmark. It would be relatively easy > for an FPGA vendor to increase performance on a known benchmark, > either by targetting their software at it, or by introducing dedicated > hardware in the next device. In the long run, everybody loses. Why ? - if the benchmarks are application relevant, then then surely the application speed improves, and everyone wins ? Static Icc and package sizes are also design benchmarks. > > Besides, how many FPGA end-users actually buy on raw performance? Very > few, I suspect, and they're probably the ones who are targetting ASICs > anyway. Correct, but benchmarks are not all about speed, they are about a defined set of designs, so you can exercise a device and get mA/MHz, or LUT, or MHz or ns, or whatever parameter matters to you most. A vendors claim of 39% is of little use to anyone. Another use is they can show you how to get more of something, for more effort, in the optimised benchmark category. Of course, the optimised category is not a level playing field, that is the whole point. -jgArticle: 78641
Kevin, you heard right: -12 speedfiles will be in ISE 7.1, available later this month (February ). Peter AlfkeArticle: 78642
On Fri, 04 Feb 2005 18:57:55 GMT, the renowned Joerg <notthisjoergsch@removethispacbell.net> wrote: >Sure, as a customer thousands of miles away you may not know for sure. >But there is one telltale sign that pops up when you have a tough >question. That will often require the original programmer or designer to >answer. Accents are really hard to hide. Like with a graphics card >manufacturer in Canada. When I got answers such as 'that's aboot right' >or I heard 'Bonjour' I somehow knew it's got to be Canada ;-) > >Regards, Joerg ATI and Matrox don't pretend to be headquartered anywhere else do they? Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 78643
I'm currently taking a class in embedded system design and we have a major project which involves using the XESS XSB-300E board as the development platform. I was interested in making a very basic VoIP phone using the mic-in and audio out ports and the onboard ethernet. Obviously I am new to the XESS board and was curious as to how difficult this project might be. I don't know if the whole thing can be programmed onto the MicroBlaze core or if certain parts should be done in VHDL. I also am not sure if I could fully implement H.323 or SIP for setting up calls and such. I'm just trying to get a better idea of whether or not I should pursue this project within a semester's time. MikeArticle: 78644
(not posted) Peter Alfke wrote: > Sounds like a description of the ASMBL architecture of Virtex-4, where > LX and SX differ in the percentage mix of functions, SX having > relatively more multiplier/accumulators and BlockRAMs, otherwise the > functions are identical. > Seems like we are getting there. > Just remember, any different chip is a multi-million dollar investment > by the manufacturer... I am way behind in following the newer chips. How automated is the generation of the different family members? I was trying to imagine a design where at the mask level one could insert a multiplier, RAM, or CLB array where all the signals would line up. That is, each block could be separately routed and then an array of such blocks assembled. Still, I am sure that the costs are high, even for just cataloging and inventorying a new device without considering the mask costs. I believe, though, as devices get bigger more intermediate family members will be needed. (I had wondered once how much it costs to create a new breakfast cereal, maybe just a different flavor of an existing one. There doesn't seem to be a limit to the combinations they can come up with. thanks, -- glenArticle: 78645
http://www.geocities.com/leon_heller "Alex" <uksb@greenbank.org> wrote in message news:cu0hm7$vm$1@localhost.localdomain... >[ Apologies if this is a frequently asked question but I've > been googling for hours and haven't found much info. ] > > I'm looking to buy a Spartan-3 Starter Kit:- > http://www.xilinx.com/products/spartan3/s3boards.htm# > in the UK. > > The only supplier in the UK with a website is nuhorizons.com > and I've seen some warnings about using them. > > I'll give Xilinx UK a call tomorrow (or Monday) but I'm > wondering if anyone has any suggestions for suppliers I can > check with. > > Or how quick/expensive is it to order from the US and deliver > to the UK. Which suppliers would you recommend? Memec-Insight should have them (£76.38). LeonArticle: 78646
I managed to find one in the uk on ebay but i suspect that I was just lucky,if you contact one of xilinx's reps in England such as Arrow then they will sell you stuff but you'll be forever fighting them off once they smell money.Article: 78647
I am about to start a similar excercise, but haven't done much yet. I think you should begin with getting the EDK and perhaps one of the cheaper eval boards, e.g. V2Pro LC by Memec Design. Together with the board you will get access to several complete sample projects including C source code on the Memec web site. I am not sure about the simulation. I believe this sort of simulation will be extremely slow. /Mikhail <jjohnson@cs.ucf.edu> wrote in message news:1107543066.103030.262780@c13g2000cwb.googlegroups.com... > > Anyone who has used the Power PC cores on Xilinx FPGAs has undoubtedly > paid some dues... I selfishly ask if anyone has compiled a quick set of > recipes, lessons-learned, or other guides for *quickly* getting up to > speed on using these. > > There is no shortage of documentation available, especially from > Xilinx. The problem (in classic Xilinx style) is that I don't have all > year to read it. Thus, any pointers to the most-recommended, > quickly-effective reading material would be appreciated. > > Specific scenario and questions: > > 1) I will soon have a board (with V2P30) on it. I wasn't originally > planning to use the PPC, so no buses were routed for external memory. > Hope to use on-chip memory only, now that I have a use for the PPC... > > 2) My tool set includes Mentor ModelSim, Synplicity (Synplify Pro), and > Xilinx ISE. Do I need other $non-free$ tools in order to use the PPC? > (i.e., Xilinx EDK, etc...) > > 3a) I first want to instantiate one PPC, load some instructions in > memory via ModelSim, tie the PPC core to the rest of the FPGA fabric, > and simulate enough instructions to make sure the flow works. > > 3b) Next, I'd like to create some real short test programs, compile > them with gcc (no RTOS required, but if easy to configure and use, > that's a bonus), load the memory image (via ModelSim) and simulate. > > 4) Load the PPC memory instruction via the bitfile when I power up the > real hardware, have the PPC boot and start running my code when I > toggle an input, so I can watch some outputs toggle on a scope. > (Eventually this board will serve as a stimulus/waveform generator for > another board.) > > 5) Where might I find an appropriately configured copy of gcc and > libraries? > > That's it in a nutshell. I don't expect this to be a one-weekend > project, but I don't have all year either. C code, VHDL code, > Synplicity scripts, etc... for getting up to speed fast would be ideal. > > Thanks very much for *any* help you can provide. > > mj >Article: 78648
I have bought ours via their web-shop (our distributor (Austria) recommend it that way). There add up some shipping charges (I think about EUR 30,-), but it worked fine. Regards, Thomas www.entner-electronics.com "Alex" <uksb@greenbank.org> schrieb im Newsbeitrag news:cu0hm7$vm$1@localhost.localdomain... >[ Apologies if this is a frequently asked question but I've > been googling for hours and haven't found much info. ] > > I'm looking to buy a Spartan-3 Starter Kit:- > http://www.xilinx.com/products/spartan3/s3boards.htm# > in the UK. > > The only supplier in the UK with a website is nuhorizons.com > and I've seen some warnings about using them. > > I'll give Xilinx UK a call tomorrow (or Monday) but I'm > wondering if anyone has any suggestions for suppliers I can > check with. > > Or how quick/expensive is it to order from the US and deliver > to the UK. Which suppliers would you recommend? > > Ta, > > -AlexArticle: 78649
Peter Alfke wrote: > A few additional comments: <snip> > Now I'm thinking of (ab)using the MGTs to count up to 5 GHz, and also > to do frequency synthesis up to 5 GHz. Maybe later this year...It helps > to think ahead. :-) Sounds good - you will make this public ? - and perhaps do two versions, one that is FPGA generic, and one (clearly faster) that is as heavily HW optimised as possible. I'd also suggest adding Pulse Width Synthesis, to Freq measure, and Freq Synthesis (DDS?) -jg
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Compare FPGA features and resources
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