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Hello, everyone, I am a new one. I am now doing a module design project. I follow the "modular design" chapter in "development System reference guide" of Xilinx. When I do the active module implementation phase, there are some error here. --output pad net " a_out_OBUF"(a_out is the top-level outport and an output of module A either) has an illegal buffer. --logical net " a_in_IBUF"(a_in is the top-level input and an input of module A either) has mutiple drivers. The possible drivers causing this are: pin O on block a_in_IBUF with type IBUF, pin PAD on block test_a/a_in_IBUF with type PAD.(test_a is the instance name of module A). In this sample test, I just do 2 modules, and only a register in each module. in the top-level UCF file, I constrain the area of 2 modules and assign the top-level ports to IOBs. So, how to resolve this problem. Thank you. regards. michel.Article: 75626
I'm looking ahead to an application in the future which will need a lot of DSP power but more importantly a huge amount of I/O bandwidth (interfacing to multiple ultra-high-speed DAC/ADCs). Up to now we've used parallel LVDS buses at up to 1Gs/s for this, but this eats lots of pins and is a PCB nightmare, so we plan to switch to serial I/O for which we have on-chip transceivers available. I've been trying to work out what total serial I/O capability is available on the latest (and near future!) FPGAs, but it's not always easy. In the timescales I'm looking at I guess that the likely candidates are Virtex-4 (for which little information is available on the MGTs), and whatever the "next-generation" Altera device is (Stratix-II doesn't have serial I/O, Stratix GX does but may be lacking in processing power) -- can anyone at Altera give any clue about this? For Virtex-4 I'm confused about what the actual serial data rate on each pin pair is for the MGT -- I understand that there are up to 20 MGT, and that these can be "up to 12GB/s", but I assume that this is done by bonding together 4 physical 3Gb/s channels into 1 virtual 12Gb/s channel -- is this correct? In that case each block of 4 MGTs can do 12Gb/s; if not then this is the rate for each MGT, but I think this is extremely unlikely -- 300ps bit period is OK since it needs rise/fall times of about 80ps which is achievable in this technology, but 80ps bit period needs 20ps tr/tf which is not! So it seems that both Altera and Xilinx are similar here; both use blocks of 4 transceivers at 3.125/3.25Gb/s per channel, or 12.5/13Gb/s per block. Both have a maximum of 5 blocks (20 channels) per chip. Is this correct? What's coming in the next couple of years as far as serial I/O is concerned? Cheers Ian Dedic Chief Engineer Mixed Signal Division Fujitsu Microelectronics Europe P.S. If there are things which can only be revealed under NDA, please contact me off-list since we have NDAs with both Xilinx and Altera.Article: 75627
Francesco:
Your compiler assumes memory is attached to the I/O port, which is
usually not. When it is, it is mostly special purpose read or write
only memory (registers) not fit for storing variables. The idea with a
C compiler for Picoblaze is to have an intelligent use of the
registers. In your example all variables should be registers. Only if
needed you should offload variables to some scratchpad. The
Picoblaze-3 core (KCPSM3.vhd) has a 64 byte scratchpad for that, with
its own set of I/O instructions FETCH and STORE. Of course you must
also be able to declare references to the I/O ports to control your
attached hardware, which will then use INPUT and OUTPUT. A problem
with Picoblaze in relation to a, say C, compiler is its inability to
work with constant arrays (lookup tables, constant strings) and
computed jumps, often you end up with lists of compare/branch lists.
Otherwise Picoblaze is tiny yet powerful core to control all sorts of
things in an FPGA design. Your C compiler, if more focussed on the
typical use of Picoblaze, could nevertheless be very useful in using
the core.
Henk van Kampen
see: www.mediatronix.com/tools
francesco_poderico@yahoo.com (Francesco Poderico) wrote in message news:<1d6bc71.0411090836.21210d2b@posting.google.com>...
> Hi all,
> I'm designing a C compiler for the PicoBlaze processor.
> The compiler is a subset of the C language, but is quite good.
>
> I called the C compiler PicoC :-)
>
> I'm an FPGA designer and I want to use this compiler for my job.
> I think is very interesting to have a small microprocessor in an FPGA that
> you can program in C!
>
>
> Are you using PicoBlaze at moment?
> do you think you can help me to test the Compiler?
>
> The compiler at moment gives working code, but I need someone to do some
> good testing.
>
> I do not promise that I'll give the compiler to eveybody, but I'll give
> the compiler to 5 or 10 people in all.
>
> Also,the compiler is in pre Alpha version.
> That means that has not all the functionality.
>
> When the compiler will be finished I'll do some optimization on the generated code.
>
>
> At moment I can write code like this:
>
>
> EXAMPLE:
>
> int i;
> int *ii;
> char s;
> char *ss;
>
> void main()
> {
> i =0;
> for(i=0;i<0x123;i++){
> s=1;
> *ss=s;
> do {s++;
> *ss +=s;
> }
> while (*ss<100);
> if(s)
> i = 10;
> else
> i = 100;
> }
> ii = 1;
> *ii = 1;
> }
>
>
> and when I lunch the PicoC compiler this is the result:
>
> CONSTANT _i_low , ff
> CONSTANT _i_high , fe
> CONSTANT _ii , fd
> CONSTANT _s , fc
> CONSTANT _ss , fb
> LOAD S3 , fb
>
>
>
> ;int i;
> ;int *ii;
> ;char s;
> ;char *ss;
> ;void main()
> _main:
> ;{
> ; i =0;
> LOAD S5,00
> LOAD S4,00
> OUTPUT S5 , _i_low
> OUTPUT S4 , _i_high
> ; for(i=0;i<0x123;i++){
> LOAD S5,00
> LOAD S4,00
> OUTPUT S5 , _i_low
> OUTPUT S4 , _i_high
> L2:
> INPUT S1 , _i_low
> INPUT S0 , _i_high
> SUB S3 , 01
> OUTPUT S0 , (S3)
> SUB S3 , 01
> OUTPUT S1 , (S3)
> LOAD S5,23
> LOAD S4,01
> INPUT S1, (S3)
> ADD S3 , 01
> INPUT S0, (S3)
> ADD S3 , 01
> SUB S1 , S5
> SUBCY S0, S4
> JUMP C , L3
> JUMP L5
> JUMP L4
> L3:
> INPUT S5 , _i_low
> INPUT S4 , _i_high
> ADD S5 , 01
> ADDCY S5 , 00
> OUTPUT S5, _i_low
> OUTPUT S4, _i_high
> SUB S5 , 01
> SUBCY S5 , 00
> JUMP L2
> L4:
> ; s=1;
> LOAD S5,01
> OUTPUT S5 , _s
> ; *ss=s;
> INPUT S1 , _ss
> INPUT S5 , _s
> OUTPUT S5, (S1)
> ; do {s++;
> L6:
> INPUT S5 , _s
> ADD S5 , 01
> OUTPUT S5, _s
> SUB S5 , 01
> ; *ss +=s;
> INPUT S1 , _ss
> INPUT S5, (S1)
> SUB S3 , 01
> OUTPUT S5 , (S3)
> INPUT S5 , _s
> INPUT S1, (S3)
> ADD S3 , 01
> ADD S1 , S5
>
> ; }
> ; while (*ss<100);
> L7:
> INPUT S5 , _ss
> INPUT S5, (S5)
> SUB S3 , 01
> OUTPUT S5 , (S3)
> LOAD S5,64
> INPUT S1, (S3)
> ADD S3 , 01
> SUB S1 , S5
> JUMP C , L9
> JUMP L8
> L9:
> JUMP L6
> L8:
> ; if(s)
> INPUT S5 , _s
> LOAD S4 , 00
> OR S5 , S4
> JUMP NZ , L10
> JUMP L10
> L11:
> ; i = 10;
> LOAD S5,0a
> LOAD S4,00
> OUTPUT S5 , _i_low
> OUTPUT S4 , _i_high
> ; else
> JUMP L12
> L10:
> ; i = 100;
> LOAD S5,64
> LOAD S4,00
> OUTPUT S5 , _i_low
> OUTPUT S4 , _i_high
> L12:
> ; }
> JUMP L3
> L5:
> ; ii = 1;
> LOAD S5,01
> LOAD S4,00
> OUTPUT S5 , _ii
> ; *ii = 1;
> INPUT S1 , _ii
> LOAD S5,01
> LOAD S4,00
> OUTPUT S5, (S1)
> SUB S1 , 01
> OUTPUT S4 , (S1)
> ;}
>
>
>
>
>
> I hope someone of you is interested
>
> Regards,
> Francesco
Article: 75628Jan Vorbrüggen wrote: >> What's the part number? > > I think it was A100 and/or A110. The only time I saw those used for graphics was an early B429 TRAM. It captured video in real time and munged it. According to the 1991 "iq systems" databook it carried two A110's and a T800. IIRC it ran convolution filters in real-time, fun demos. Cheers, Rupert -- Threading sequential code through the eye of a parallel needle makes little sense. ;)Article: 75629
John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<cmu719$av8$1@bunyip.cc.uq.edu.au>... > Bob, > > Bob Perlman wrote: > > On 10 Nov 2004 13:30:48 -0800, wpiman@aol.com (MS) wrote: > >> > >>I haven't tried washing it yet. Has anyone managed to get all the > >>wrinkles out? > > > > Forgive me for asking, but if you object to wearing a free, wrinkled > > T-shirt, are you absolutely certain you're an engineer? > > That's priceless - deserves to be printed and framed! > > John reminds me of this one :)) http://www.dilbert.com/comics/dilbert/archive/images/dilbert200411095097.jpg -LasseArticle: 75630
Austin, thanks very much for your answer. It's in a sense good to know that the simulation seems to be accurate - despite the fact that we then have to worry more about signals and spend more real estate for terminations. What makes me wonder, though, is that the simulations also said that one cannot even connect two FPGAs directly without violating undershoot limits - this doesn't reflect reality. What I really would like to know is whether or not I can damage the 2V4000 chip with strong over/undershoot. You said that the clamp diodes will withstand that stress, but what about the MOS transistors? The voltage across the gate oxide might become too large if excessive current causes a large voltage drop across the clamp diodes. I couldn't find anything on this topic in the VII-docs. Can you shed some light on this? Thanks very much Gunter "Austin Lesea" <austin@xilinx.com> wrote in message news:cmtdif$ru81@cliff.xsj.xilinx.com... > Gunter, > > The protection diodes are clamping the overshoot and undershoot. They > will not be damaged, but your signal integrity is terrible, you will have > excessive jitter, and that may lead to bit errors, and other behavior that > you will not like at all. > > I doubt the simulation is pessimistic, as I get the same results, and > often worse when too strong a driver is used unterminated. > > I suggest a small series resistor at the driver to better match the lines. > Perhaps somewhere from 22 ohms to 43 ohms. Simulate until you have the > best choice for the slow/weak and fast/strong IBIS model corners. > > Oh, and thank you for using IBIS before you built the board. We are happy > (and you are happy) when you fix problems before the board layout. > > Austin > > Gunter Knittel wrote: > >> Hi, >> >> I'm planning to use ALVCH-Transceivers located 4-8 inches away from a >> 2V4000 FPGA. >> The board impedance is said to be 50R. I used IBIS models for both >> the transceiver and the FPGA (LVCM316S), and simulated one wire using >> PSPICE. The line is not terminated in any way. >> I get serious overshoot (>4V at 3.3V VCCO) and undershoot (-1V) >> at the (tri-stated) input of the FPGA. Current reaches 100mA during a >> short spike, otherwise some 50mA. >> My question: is this tolerable? >> Doc for VII-Pro states that the FPGA would suffer damage (gate oxide >> breakdown). >> Could it be that the simulation is too pessimistic in these cases? >> >> Thanks for any help >> Gunter >> >>Article: 75631
Marc, thanks very much for your answer. Using transceivers with built-in series resistors would be a solution. Unfortunately, I'm planning on using the 32501 36-bit transceiver, of which no version with resistors is available. To my knowledge, this chip exists in only one additional technology, LVCH, which is just as fast. Cheers Gunter "Marc Randolph" <mrand@my-deja.com> wrote in message news:g42dnSCPxoSDlw_cRVn-qg@comcast.com... > Gunter Knittel wrote: >> Hi, >> >> I'm planning to use ALVCH-Transceivers located 4-8 inches away from a >> 2V4000 FPGA. >> The board impedance is said to be 50R. I used IBIS models for both >> the transceiver and the FPGA (LVCM316S), and simulated one wire using >> PSPICE. The line is not terminated in any way. >> I get serious overshoot (>4V at 3.3V VCCO) and undershoot (-1V) >> at the (tri-stated) input of the FPGA. Current reaches 100mA during a >> short spike, otherwise some 50mA. >> My question: is this tolerable? >> Doc for VII-Pro states that the FPGA would suffer damage (gate oxide >> breakdown). >> Could it be that the simulation is too pessimistic in these cases? >> >> Thanks for any help >> Gunter > > Howdy Gunter, > > I'm probably missing something here due to lack of sleep, but my first > reaction was that a 100 mA current spike into a tri-stated FPGA pin > doesn't seem quite right. I'm sure someone else will speak up on that > part of the issue. > > Regardless, you could probably reduce the overshoot by using a ALVCHR > instead - they contain a ~25 Ohm series resistor. Another idea would be > to use a lower VCC (either in the ALVC, or on a related family that may > have higher input voltage tolerance like LVC or AVC). > > Good luck, > > MarcArticle: 75632
"Derek Simmons" <DerekSimmons@FrontierNet.net> wrote in message news:7b311686.0411102012.1a33aed5@posting.google.com... > What's the part number? A100 and A110 > I know about the G300 and its predecessors but > they were just a display controller Indeed, based on the 6845. http://homepage.ntlworld.com/kryten_droid/inmos/ims_an004.htmArticle: 75633
suntthekid wrote: > I simulate vhdl code in modelsim and then it is correct. but, when i > burn this code into FPGA chip (Stratix S25F672C6) it's wrong (i saw a > signal in signaltap and found it 's wrong) > so i want everybody who know this problem help me to solve this > problem > thank you Did you simulate the circuit after you fit it into the chip? vax, 9000Article: 75634
Kryten wrote: > "Derek Simmons" <DerekSimmons@FrontierNet.net> wrote in message > news:7b311686.0411102012.1a33aed5@posting.google.com... >> What's the part number? > > A100 and A110 > >> I know about the G300 and its predecessors but >> they were just a display controller > > Indeed, based on the 6845. > http://homepage.ntlworld.com/kryten_droid/inmos/ims_an004.htm I've coded for both and I really can't ever recall thinking that a G3xx was anything like a 6845, so I am a bit surprised to see a claim that they were "based" on them ! IIRC G3xx parts had VTGs, memory interfaces and CLUTs (also used for gamma correction). I think that G332/G364 had hardware cursor support. They were pretty easy to code for, I liked them a lot. Cheers, Rupert -- Threading sequential code through the eye of a parallel needle makes little sense. ;)Article: 75635
Hi all, I am a beginner in FPGA arch. I was going through the Spartan 2 architecture where I found that each lut can be configured as a 16 bit ram. That means lut is a decoder + a 16 bit register. This might be a foolish quesiton but please clarify me. Thanks. Regards, Mohammed A KhaderArticle: 75636
Dear newsgroup community, recently I came across the following challenge. There are several digital values which I want to convert to analog signals. Ok then, no problem. Simply D/A conversion! But after converting the signals the general set up requires that these values should be held for about - let's say - a period of 5 minutes with practically no droop (decay of the analog value) at best! The D/A conversion itself takes place in a 1 MHz period, the values to be set have to pend for about 5 minues. I guess a hold-element (capacitor and op-amp) would be the obvious choice. But how should I dimension the capacitance and how can I affect the droop? Is it realistic to expect virtually no droop assuming an optimal configuration ? Isn't it, that with a large time constant the charging time would be endless, too? Please help me, if you can. I am almost become desperate. I need this for my graduation report. Thank you in advance and many greets VeronicaArticle: 75637
suntthekid@gmail.com (suntthekid) wrote in message news:<9f23080e.0411102312.20a1dc2d@posting.google.com>... > I simulate vhdl code in modelsim and then it is correct. but, when i > burn this code into FPGA chip (Stratix S25F672C6) it's wrong (i saw a > signal in signaltap and found it 's wrong) > so i want everybody who know this problem help me to solve this > problem This happens all to often. First thing to check is that you don't have any timing violations. Check the STA report. Next, is it possible that you have a problem with data crossing between clock domains (i.e. could be a problem that means your code is incorrect, but it just doesn't show in the simulation because of the way the clocks are generated. More details on your exact problem would help)? If you are convinced that it's the synthesis or P&R tools that have got it wrong, then you should try running simultions on the post-synthesis and post-P&R netlists. Alternatively, if you have a equivalence checking tool, you can compare the next lists automatically. You can try synthesizing the design with different optimisation settings to see if the bug changes / disappears. That's quite a good sign that something is wrong with the tools. Cheers, JonArticle: 75638
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0411110211.457ecd58@posting.google.com>... > Hi newsgroups users, > > maybe someone has experienced the following problem: > > > I have a HDL design in which a PLL is instantiated (QuartusII). > > To test the functionality of the PLL I made a smaller design > containing exactly the same PLL. > For the small design I have found out that the PLL does work. > > When I compile my original design I can see that the PLL does not > work. > > As I said the pin assignments and pll assignments are exactly the same. > > Where could be the problem? > > Unused pins are set to ground. > There are also defined input pins which are not used. Could it be > that the fitter does produce some strange combintation of > setting the unused input pins to ground so that some driver > conflict exists ? Something additional: I have found out that when I reserve all unused pins 1. as inputs, tri-states --> PLL does not work 2. as outputs, driving ground --> PLL does not work 3. as output, driving an unspecified signal --> The PLL works I do not understand why this has an influence on the PLL. I would appreciate your opinion. Rgds AndréArticle: 75639
Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote in message news:<41932cc1$0$20382$ba620e4c@news.skynet.be>... > What about the Avnet Virtex-4 kit ? > > http://www.em.avnet.com/evk/home/0,4534,CID%253D16863%2526CCD%253DUSA%2526SID%253DNoNav%2526DID%253DDF2%2526LID%253D4746%2526BID%253DDF2%2526CTP%253DEVK,00.html > > > 299$ For a virtex 4 sounds ok. It's only 3x the price of the spartan3 starter kit and has lots of stuff. > > > > Sylvain That definetly has been the best priced thing ive seen so far. Thank you very much for that link, I beleive I will be getting that. Thanks -MarkArticle: 75640
The hard part isn't getting the wrinkles out: the hard part is folding it
back into the football shape!
MS wrote:
> I just got one of these Xilinx V4 tshirts that must have been vacuumed
> sealed into a small package in the shape of a football. It was so
> small I thought it was a notepad. Well- I opened this thing up- and
> it was more wrinkled than prune. It seriously looks damaged it was
> crinkled up so tight.
>
> I haven't tried washing it yet. Has anyone managed to get all the
> wrinkles out?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 75641
This won't answer your question but here are some sources I have found
helpful for better understanding what goes on under the hood.
See if your favorite library can find one of these books
Betz et al, Architecture and CAD for Deep-Submicron FPGAs
Trimberger, Field-Programmable Gate Array Technology
Then there are journals like IEEE Trans. VLSI, proceedings of the yearly ACM
SIGDA Intl. Symp. on FPGAs, device vendor patents, etc.
Jan Gray
Article: 75642
Thank you henk for your comment,
Yes, I'm assuming to have some external memory attached to the
processor.
But if you declare a variable as register you may not need any
external ram
eg.
void main(){
register char i;
register int *p;
p=1;
for(i=0;i<100;i++){
{
*p=(int)i;
}
}
In this case the compiler generate code that doesn't need any memory
attached to PicoBlaze :-)
If you still don't bealeve me, send me some code and I'll send you
back the code
generated by PicoC :-)
So, it depeand from the application... you can use the external memory
or not.
The compiler also tells you how much memory you need (if you need)
Unfortunatly I still have a lot work to do, but the compiler start to
be
working.
The version alpha will be read in few weeks time,(I still have some
bugs to fix)
I hope to fix some bugs in 2 or 3 week time, after that I will
appriciate
anyone could help me in the testing(I won't give the source)
Also, I want to say thanks to all the people that seems interested in
this project.
Francesco
henk@mediatronix.com (Henk van Kampen) wrote in message news:<23ecd97d.0411110331.2992002d@posting.google.com>...
> Francesco:
> Your compiler assumes memory is attached to the I/O port, which is
> usually not. When it is, it is mostly special purpose read or write
> only memory (registers) not fit for storing variables. The idea with a
> C compiler for Picoblaze is to have an intelligent use of the
> registers. In your example all variables should be registers. Only if
> needed you should offload variables to some scratchpad. The
> Picoblaze-3 core (KCPSM3.vhd) has a 64 byte scratchpad for that, with
> its own set of I/O instructions FETCH and STORE. Of course you must
> also be able to declare references to the I/O ports to control your
> attached hardware, which will then use INPUT and OUTPUT. A problem
> with Picoblaze in relation to a, say C, compiler is its inability to
> work with constant arrays (lookup tables, constant strings) and
> computed jumps, often you end up with lists of compare/branch lists.
> Otherwise Picoblaze is tiny yet powerful core to control all sorts of
> things in an FPGA design. Your C compiler, if more focussed on the
> typical use of Picoblaze, could nevertheless be very useful in using
> the core.
> Henk van Kampen
> see: www.mediatronix.com/tools
>
> francesco_poderico@yahoo.com (Francesco Poderico) wrote in message news:<1d6bc71.0411090836.21210d2b@posting.google.com>...
> > Hi all,
> > I'm designing a C compiler for the PicoBlaze processor.
> > The compiler is a subset of the C language, but is quite good.
> >
> > I called the C compiler PicoC :-)
> >
> > I'm an FPGA designer and I want to use this compiler for my job.
> > I think is very interesting to have a small microprocessor in an FPGA that
> > you can program in C!
> >
> >
> > Are you using PicoBlaze at moment?
> > do you think you can help me to test the Compiler?
> >
> > The compiler at moment gives working code, but I need someone to do some
> > good testing.
> >
> > I do not promise that I'll give the compiler to eveybody, but I'll give
> > the compiler to 5 or 10 people in all.
> >
> > Also,the compiler is in pre Alpha version.
> > That means that has not all the functionality.
> >
> > When the compiler will be finished I'll do some optimization on the generated code.
> >
> >
> > At moment I can write code like this:
> >
> >
> > EXAMPLE:
> >
> > int i;
> > int *ii;
> > char s;
> > char *ss;
> >
> > void main()
> > {
> > i =0;
> > for(i=0;i<0x123;i++){
> > s=1;
> > *ss=s;
> > do {s++;
> > *ss +=s;
> > }
> > while (*ss<100);
> > if(s)
> > i = 10;
> > else
> > i = 100;
> > }
> > ii = 1;
> > *ii = 1;
> > }
> >
> >
> > and when I lunch the PicoC compiler this is the result:
> >
> > CONSTANT _i_low , ff
> > CONSTANT _i_high , fe
> > CONSTANT _ii , fd
> > CONSTANT _s , fc
> > CONSTANT _ss , fb
> > LOAD S3 , fb
> >
> >
> >
> > ;int i;
> > ;int *ii;
> > ;char s;
> > ;char *ss;
> > ;void main()
> > _main:
> > ;{
> > ; i =0;
> > LOAD S5,00
> > LOAD S4,00
> > OUTPUT S5 , _i_low
> > OUTPUT S4 , _i_high
> > ; for(i=0;i<0x123;i++){
> > LOAD S5,00
> > LOAD S4,00
> > OUTPUT S5 , _i_low
> > OUTPUT S4 , _i_high
> > L2:
> > INPUT S1 , _i_low
> > INPUT S0 , _i_high
> > SUB S3 , 01
> > OUTPUT S0 , (S3)
> > SUB S3 , 01
> > OUTPUT S1 , (S3)
> > LOAD S5,23
> > LOAD S4,01
> > INPUT S1, (S3)
> > ADD S3 , 01
> > INPUT S0, (S3)
> > ADD S3 , 01
> > SUB S1 , S5
> > SUBCY S0, S4
> > JUMP C , L3
> > JUMP L5
> > JUMP L4
> > L3:
> > INPUT S5 , _i_low
> > INPUT S4 , _i_high
> > ADD S5 , 01
> > ADDCY S5 , 00
> > OUTPUT S5, _i_low
> > OUTPUT S4, _i_high
> > SUB S5 , 01
> > SUBCY S5 , 00
> > JUMP L2
> > L4:
> > ; s=1;
> > LOAD S5,01
> > OUTPUT S5 , _s
> > ; *ss=s;
> > INPUT S1 , _ss
> > INPUT S5 , _s
> > OUTPUT S5, (S1)
> > ; do {s++;
> > L6:
> > INPUT S5 , _s
> > ADD S5 , 01
> > OUTPUT S5, _s
> > SUB S5 , 01
> > ; *ss +=s;
> > INPUT S1 , _ss
> > INPUT S5, (S1)
> > SUB S3 , 01
> > OUTPUT S5 , (S3)
> > INPUT S5 , _s
> > INPUT S1, (S3)
> > ADD S3 , 01
> > ADD S1 , S5
> >
> > ; }
> > ; while (*ss<100);
> > L7:
> > INPUT S5 , _ss
> > INPUT S5, (S5)
> > SUB S3 , 01
> > OUTPUT S5 , (S3)
> > LOAD S5,64
> > INPUT S1, (S3)
> > ADD S3 , 01
> > SUB S1 , S5
> > JUMP C , L9
> > JUMP L8
> > L9:
> > JUMP L6
> > L8:
> > ; if(s)
> > INPUT S5 , _s
> > LOAD S4 , 00
> > OR S5 , S4
> > JUMP NZ , L10
> > JUMP L10
> > L11:
> > ; i = 10;
> > LOAD S5,0a
> > LOAD S4,00
> > OUTPUT S5 , _i_low
> > OUTPUT S4 , _i_high
> > ; else
> > JUMP L12
> > L10:
> > ; i = 100;
> > LOAD S5,64
> > LOAD S4,00
> > OUTPUT S5 , _i_low
> > OUTPUT S4 , _i_high
> > L12:
> > ; }
> > JUMP L3
> > L5:
> > ; ii = 1;
> > LOAD S5,01
> > LOAD S4,00
> > OUTPUT S5 , _ii
> > ; *ii = 1;
> > INPUT S1 , _ii
> > LOAD S5,01
> > LOAD S4,00
> > OUTPUT S5, (S1)
> > SUB S1 , 01
> > OUTPUT S4 , (S1)
> > ;}
> >
> >
> >
> >
> >
> > I hope someone of you is interested
> >
> > Regards,
> > Francesco
Article: 75643
My apologies,
A C compiler for PicoBlaze ? Is really needed ?
Leaving out an academic research, is the correct choice ?
Walter.
"Francesco Poderico" <francesco_poderico@yahoo.com> a écrit dans le message
de news:1d6bc71.0411090836.21210d2b@posting.google.com...
> Hi all,
> I'm designing a C compiler for the PicoBlaze processor.
> The compiler is a subset of the C language, but is quite good.
>
> I called the C compiler PicoC :-)
>
> I'm an FPGA designer and I want to use this compiler for my job.
> I think is very interesting to have a small microprocessor in an FPGA that
> you can program in C!
>
>
> Are you using PicoBlaze at moment?
> do you think you can help me to test the Compiler?
>
> The compiler at moment gives working code, but I need someone to do some
> good testing.
>
> I do not promise that I'll give the compiler to eveybody, but I'll give
> the compiler to 5 or 10 people in all.
>
> Also,the compiler is in pre Alpha version.
> That means that has not all the functionality.
>
> When the compiler will be finished I'll do some optimization on the
generated code.
>
>
> At moment I can write code like this:
>
>
> EXAMPLE:
>
> int i;
> int *ii;
> char s;
> char *ss;
>
> void main()
> {
> i =0;
> for(i=0;i<0x123;i++){
> s=1;
> *ss=s;
> do {s++;
> *ss +=s;
> }
> while (*ss<100);
> if(s)
> i = 10;
> else
> i = 100;
> }
> ii = 1;
> *ii = 1;
> }
>
>
> and when I lunch the PicoC compiler this is the result:
>
> CONSTANT _i_low , ff
> CONSTANT _i_high , fe
> CONSTANT _ii , fd
> CONSTANT _s , fc
> CONSTANT _ss , fb
> LOAD S3 , fb
>
>
>
> ;int i;
> ;int *ii;
> ;char s;
> ;char *ss;
> ;void main()
> _main:
> ;{
> ; i =0;
> LOAD S5,00
> LOAD S4,00
> OUTPUT S5 , _i_low
> OUTPUT S4 , _i_high
> ; for(i=0;i<0x123;i++){
> LOAD S5,00
> LOAD S4,00
> OUTPUT S5 , _i_low
> OUTPUT S4 , _i_high
> L2:
> INPUT S1 , _i_low
> INPUT S0 , _i_high
> SUB S3 , 01
> OUTPUT S0 , (S3)
> SUB S3 , 01
> OUTPUT S1 , (S3)
> LOAD S5,23
> LOAD S4,01
> INPUT S1, (S3)
> ADD S3 , 01
> INPUT S0, (S3)
> ADD S3 , 01
> SUB S1 , S5
> SUBCY S0, S4
> JUMP C , L3
> JUMP L5
> JUMP L4
> L3:
> INPUT S5 , _i_low
> INPUT S4 , _i_high
> ADD S5 , 01
> ADDCY S5 , 00
> OUTPUT S5, _i_low
> OUTPUT S4, _i_high
> SUB S5 , 01
> SUBCY S5 , 00
> JUMP L2
> L4:
> ; s=1;
> LOAD S5,01
> OUTPUT S5 , _s
> ; *ss=s;
> INPUT S1 , _ss
> INPUT S5 , _s
> OUTPUT S5, (S1)
> ; do {s++;
> L6:
> INPUT S5 , _s
> ADD S5 , 01
> OUTPUT S5, _s
> SUB S5 , 01
> ; *ss +=s;
> INPUT S1 , _ss
> INPUT S5, (S1)
> SUB S3 , 01
> OUTPUT S5 , (S3)
> INPUT S5 , _s
> INPUT S1, (S3)
> ADD S3 , 01
> ADD S1 , S5
>
> ; }
> ; while (*ss<100);
> L7:
> INPUT S5 , _ss
> INPUT S5, (S5)
> SUB S3 , 01
> OUTPUT S5 , (S3)
> LOAD S5,64
> INPUT S1, (S3)
> ADD S3 , 01
> SUB S1 , S5
> JUMP C , L9
> JUMP L8
> L9:
> JUMP L6
> L8:
> ; if(s)
> INPUT S5 , _s
> LOAD S4 , 00
> OR S5 , S4
> JUMP NZ , L10
> JUMP L10
> L11:
> ; i = 10;
> LOAD S5,0a
> LOAD S4,00
> OUTPUT S5 , _i_low
> OUTPUT S4 , _i_high
> ; else
> JUMP L12
> L10:
> ; i = 100;
> LOAD S5,64
> LOAD S4,00
> OUTPUT S5 , _i_low
> OUTPUT S4 , _i_high
> L12:
> ; }
> JUMP L3
> L5:
> ; ii = 1;
> LOAD S5,01
> LOAD S4,00
> OUTPUT S5 , _ii
> ; *ii = 1;
> INPUT S1 , _ii
> LOAD S5,01
> LOAD S4,00
> OUTPUT S5, (S1)
> SUB S1 , 01
> OUTPUT S4 , (S1)
> ;}
>
>
>
>
>
> I hope someone of you is interested
>
> Regards,
> Francesco
Article: 75644I see I am not the only one who is confused by your description of the problem. I think you want to do a DMA like transfer between the SDRAM and the SRAM. But I assume this data also needs to go to or come from another source, no? Or is your SRAM dual ported so that the SDRAM is a backup for the SRAM; or better put, you are using the SRAM as a cache for the SDRAM? In any event, I don't see how this is a very complex problem. Your description seems to be getting in your way of finding a good solution. First, I assume that all of this is running on the same clock. This is important. If they are on different clocks, then you will need to construct an appropriate interface. When you speak of the SRAM, I assume you mean a separate SRAM controller that in turn is being controlled by some other circuit. I will leave the nature of the SRAM controller to you since you have not given us any info on what this controller must do. I would do this by constructing an SDRAM controller, like you have done, that will respond to commands. I think you have a good handle on that with the signals A, B, C, D. But you will also need a signal from the SDRAM controller back to the "SRAM" telling it that valid data is available in a given clock cycle. To do block bursts, you can set up the SDRAM to burst as much as 256 words (or maybe more depending on the part). I believe that you can also overlap the next burst setup with the current burst data read. So you can move data continuously until the block is done. But you either need a handshake to flag when data is available, or you need to track the latency and the block size in both controllers. BTW, you need to change your block diagram so that the signals, A, B, C, D go to the SDRAM controller which in turn drives the SDRAM signals. You may also want to show exactly how the SRAM is being read/written from the outside. This will help you design the SRAM controller. Vick wrote: > > Hello all, > > I had psted this question earlier but havent got any response yet... > I was wondering if the questions I asked made any sense (or) were they > just out of the way... So again, I have the Micron SDRAM Verilog code > and I need to make SRAM read/write the SDRAM... Obviosuly, the SRAM > shold maintain its own functionality (i.e. it itself can be > read/written). > > The questions I have are: > > (1) Should my SRAM just issue Read/Write command to SDRAM Controller > and then it will do the rest i.e. Read/write from SDRAM. > > (2) Should'nt the SRAM output (Q) be a bi-directional since this pin > Q has to be used for SRAM read and also for SDRAM read? > > The logidc diagram I have come up with is as below: > > INTERFACE -Logic > ______________________________ > |IF Read_SDRAM = 1 then | `````````````````` > |- Initiate SDRAM Read Command |------>|SDRAM Controller| > |- Addr = SDRAM_Address; | `````````````````` > | | | > |IF Write_SDRAM = 1 then | | > |- We_n = Write_SDRAM; | | > |- Addr = SDRAM_Address; | | > ------------------------------ v > A ******>| | | ____________ > B**********>| | Addr(11-bits)--->| | > C*************>| other I/Ps | | > | | | ... | | > V V V ... | | > _____ ... | Micron | > Data---->| | ------>| SDRAM | > Wad ---->| |_________ Q | (168-pin) | > Rad ---->|SRAM | | | | > ---->|_____| | | | > ^ ^ ^ | | | > | | | |_______Dq (16-bits)__ | | > | | | | | > clk____| | | ____________ > WE ________| | > RE____________| > > Steps to the above logic-diagram: > > (1) I have allocated 3 new pins to the SRAM above namely A,B,C which > are designated as: > > A --> Read_SDRAM (1-bit) > B --> Write_SDRAM (1-bit) > C --> SDRAM_Address (11-bits) > > (2) The Interface-Logic shown above programs the SDRAM Controller as > to whether the SRAM wants to Read (or) Write the SDRAM. ie. the SDRAM > Controller is asked to fire the appropriate Command to the SDRAM > (Read, Write, Aotorefresh etc..) > > (3) The SDRAM Controller then takes over by firing executing the > Command requested by SRAM. > > (4) Say, if the SRAM requested a Read from SDRAM, then the data read > (16-bits) is sent back to the pin-Q of SRAM. > > Note: that the pin-Q is also used for outputting the 16-bit data for > Reading the SRAM itself! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75645
"Veronica Matthews" <ikeepthespiritalive@freenet.de> wrote in news:cmvum3$ici$1@news.cs.tu-berlin.de: > Dear newsgroup community, > > recently I came across the following challenge. There are several > digital values which I want to convert to analog signals. Ok then, no > problem. Simply D/A conversion! But after converting the signals the > general set up requires that these values should be held for about - > let's say - a period of 5 minutes with practically no droop (decay of > the analog value) at best! The D/A conversion itself takes place in a > 1 MHz period, the values to be set have to pend for about 5 minues. I > guess a hold-element (capacitor and op-amp) would be the obvious > choice. But how should I dimension the capacitance and how can I > affect the droop? Is it realistic to expect virtually no droop > assuming an optimal configuration ? Isn't it, that with a large time > constant the charging time would be endless, too? Please help me, if > you can. I am almost become desperate. I need this for my graduation > report. > > Thank you in advance and many greets > Veronica > > > Assuming that the DAC you use has a DC response, there should not be a droop problem. The DAC should maintain its output indefinitely until you write a new value. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 75646
mike_treseler wrote: > > > 1. Will this approach work? > > There is not enough information here > to base any judgment on. You could improve > your odds by focusing on the system description > without assuming so much in advance about > the optimum implementation details. > > Or maybe you could restrict the topic to > research into partial reconfiguration, since > this seems to be your overriding interest. > > > 2. If the logic is fixed, do I need long lines and TBUFs, > > There are no real tri-state buses current FPGAs. And those FPGAs without tbufs are not supported by the partial reconfiguration design software. You can only use this with the Xilinx parts prior to Spartan III. So be prepared to pay the higher prices for parts that let you reconfigure on the fly which is supposed to save you money by using smaller parts... sort of counter intuitive isn't it? I have been told more than once that partial reconfiguration is not a good thing to try to use in a commercial product. I would hazzard a guess that it is not a technolgy that is used enough (or requested enough) to have been fully developed. I believe they even put in an app note that you should limit your designs to just two modules, one fixed and one replacable. I think that was in the context of active partial reconfiguration. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75647
Thomas Reinemann wrote: > > reconfiguration. > The communication system connects all slots of my FPGA and shall even > work if a slot is under reconfiguration. However, if the CS signal is > active of a Xilinx FPGA, the complete logic works. Logic under > reconfiguration produces trashy signals, and therefore the C/S has to be > suspended if any slot is reconfigured. But IMHO trashy signals are only > produced by changing logic, therefore I want to fix the related logic > (only one CLB) within each module's type, to avoid suspending of the > C/S. And my question is, is this assumption true? I understand what you are saying. I know that the Virtex parts support this, but I don't know if the software makes it very easy to do in practice. You should contact Xilinx support about it. I assume you have checked for an app note or similar. > >>2. If the logic is fixed, do I need long lines and TBUFs, > > There are no real tri-state buses current FPGAs. > You haven't understand my question. Real tri-state behavior wasn't a > matter. Xilinx approach needs TBUFs and long lines to provide fixed > points within a slot to connect signals of all types of a module > properly, since logic is changing. But now I have some fixed logic, do I > still need fixed communication points? Actually, the current software requires you to use a true long line and tbufs for each signal in the bus macro. So again, the Virtext parts (not the Spartan parts which don't support active reconfiguration) might support using non-tbuf signals between modules, but I don't think the software does. But Xilinx is working on this for the new Virtex 4 and Spartan 3 parts which do not have tbufs. So the new software may have a way to do this without long lines. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75648
Nicolas Matringe wrote: > > Hello > Is there a way to specify a maximum signal fan-out for Altera Flex10K > FPGAs? The option seems only be available for more recent families. > I am explicitly duplicating high-fanout signals and putting "preserve" > constraints but it is long since I don't always know signals fan-out. This question tells me that you are treading on thin ice with high fan out signals. A few years ago, I worked on adding functions to an existing design in a EP10K100A, IIRC. The original design has a major problem where they suspected a high fanout node was not meeting timing even though the tools said it did. They had to conduct temperature tests on the completed design before they could sign off on it. We ran into the same problem even after we duplicated logic to get rid of the high fan outs. I belive we limited the fan out to something like 20 or less. There is an option in the Max+II software somewhere. If you are using Quartus, you may not have the same problem. If there is any way, I would recommend that you drop this chip and use a newer one. I expect you are updating an existing design, like we were doing, and you are stuck with the hardware. The other thing is to limit your total LE usage to about 85% and expect routing problems if you have timing restrictions that are at all tight. We found that at 90% full, the chip was almost impossible to route, even with location constraints. I called it the whack-a-mole problem. You arrange a couple of registers to get them to meet timing and a couple more fail... lather, rinse, repeat... That project used more of my free time than I have ever spent on any personal activity. I will still not use Max+II for a project no matter how much I am paid!!! One other thought, you might want to use "keep" rather than preserve. I was just reading about that and I don't recall that they do the same thing. "keep" inserts an LE buffer which makes this the output of a logic cell and will not be optimized away, it also uses your signal name in the netlist file. I don't remember what "preserve" does, but I found it would not work for my needs. I am using a lot of keeps in a 1K50 design to obtain optimal logic. The software is just not that good at orgainizing the logic... Opps, I just read up on it and "preserve" is for registers and "keep" is for LEs. Nevermind... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75649
In article <335c6753.0411110812.2f5e4427@posting.google.com>, weizbox <mwiesbock@gmail.com> wrote: >Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote in message news:<41932cc1$0$20382$ba620e4c@news.skynet.be>... >> What about the Avnet Virtex-4 kit ? >> >> http://www.em.avnet.com/evk/home/0,4534,CID%253D16863%2526CCD%253DUSA%2526SID%253DNoNav%2526DID%253DDF2%2526LID%253D4746%2526BID%253DDF2%2526CTP%253DEVK,00.html >> >> 299$ For a virtex 4 sounds ok. It's only 3x the price of the >> spartan3 starter kit and has lots of stuff. >That definetly has been the best priced thing ive seen so far. Thank >you very much for that link, I beleive I will be getting that. Do you have the spare $2400 for the software? None of the free Xilinx tools are aware of the existence of Virtex 4 yet. Tom
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