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On Tue, 07 Dec 2004 17:16:48 +1300, Jim Granville <no.spam@designtools.co.nz> wrote: >Allan Herriman wrote: >> On Tue, 07 Dec 2004 15:34:36 +1300, Jim Granville >> <no.spam@designtools.co.nz> wrote: >> >> >>>John_H wrote: >>> >>>>It's involved... >>>>With your example of 211kHz from a 1MHz reference, the ratio of >>>>906,238,099/2^32 has closest fractions in order of worst to best of >>>> >>>>1/5 >>>>4/19 >>>>23/109 >>>>211/1000 >>>>1987386/9418891 >>>>19873649/94187910 >>>>57633561/273144839 >>>> >>>>The offsets are the ideal frequency compared to the ratio frequency: >>>>211 kHz - 200 kHz >>>>211 kHz - 210.52632 kHz >>>>211 kHz - 211.00917 kHz >>>>211 kHz - 211 kHz... Here Excel starts to lose digits: >>>> >>>> The difference between 906,238,099/2^32 and 906,238,099.456/2^32 is about >>>>5.03e-10 at which point small amounts of jitter are lost. If the jitter at >>>>that tiny offset is large, you will experience phase jumps when that beat >>>>frequency is felt. There's no way to filter those with analog filters. >>>> >>>>Your largest observed peaks in the spectrum will be at offsets of 11 kHz, >>>>526 Hz, and 9.17 Hz. You should be able to see the 526 Hz modulating the >>>>11kHz for spikes much smaller than the 11 kHz peak. >>> >>>Good example maths, but is the principle right ? >>> >>> >>>For the example of 211KHz from 1Mhz, you have 1us quantize, and so will >>>be able to generate 4us, or 5us periods, giving 250KHz and 200KHz. >>> >>>Over many cycles, the 'wobbling' between these two will average to >>>211KHz. The more cycles, the better the match to 211KHz. >>> >>>Over a 6 cycle snapshot, you might see 5@200, 1@250, and Favge 208.33Khz >>>That's appx one part in 77 too slow. >>>This 6 cycle frame has a freq of 34.6KHz >>> >>>Next frame group would be (eg) >>>every 79 cycles, to see => 14 @ 250KHz, 65@ 200KHz => 210.76923Khz, >>>Error is now one part in 1000, and this finer frame is 2.65KHz >>>( etc ) as over wider frame snap-shots, the average frequency gets >>>closer to the 211KHz ideal. >>> >>>So I'd expect to see, on a spectrum analyser, 200KHz, (Dominant) 250KHz >>>and 34.6KHz and 2.65KHz (etc) energies. >> >> >> Did you actually plug it in to a spectrum analyser and see those >> tones? > > No, it was just 'back of an envelope' stuff, to get a feel for what >repetition frames are likely, and so what the likely energies are. > >> >> Ten highest spurious tones: >> >> 55.000kHz -11.4dBc >> 367.000kHz -16.7dBc >> 101.000kHz -17.0dBc >> 165.000kHz -22.4dBc >> 9.000kHz -22.9dBc >> 257.000kHz -24.1dBc >> 321.000kHz -25.1dBc >> 147.000kHz -25.8dBc >> 119.000kHz -27.4dBc >> 37.000kHz -27.7dBc > > Are these rounded to the nearest KHz, Nearest 1 Hz. > as I can't derive 55.00KHz >either... a 19 cycle @ 1MHz frame, would be 52.63KHz ? > It also seems strange to not see 200KHz, 250KHz... ? Not strange at all. Switching between 4us and 5us periods does not mean you will see high level 200kHz and 250kHz components in the output. As you said: "Good example maths, but is the principle right ?" (This is getting OT for c.a.f. Suggest moving this to news:comp.dsp if you want to discuss the spectrum.) Regards, AllanArticle: 76601
Moti wrote: > > Hi Falk, > My german is pretty "rusty" :) so if the document is in .pdf format it > will very hard... > but if it's in a html format it can translated by google and then it > will be possible to read it! > Regards, Moti. You should be able to copy and paste the text from a PDF into a web page for translation. But my experience has been that web page translations give you English that is not much easier to understand than the language you are translating from. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76602
Jacob Bower wrote: > Hi, > > I was wondering if anyone in this group can provide some insight as to how > hard it might be to get an FPGA to act as a USB host, for collecting data > at quite a high-bandwidth. Particularly can this reasonably be done at all > with a completely hardware implementation, possibly with an external > embedded USB host controller. Or would I be much better off using some > kind of soft-core CPU to collect and format data from the USB peripheral > due complexity of driving an embedded USB host controller? > > Thanks, > - Jake It's doable in hardware, but extremely complex. The enumeration process needs quite a bit of decisions making. However, once the enumeration is complete, there is no reason why other endpoints (non-zero) could not be 100% hardware interface pipes. Not sure what your interpretation of "high bandwidth" is, but USB 2.0 only goes to 480 Mbits/sec, or about 60Mbyes/sec. So it should be quite trivial to do this in FPGA. However you will need a High Speed USB PHY. Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 76603
>>>every 79 cycles, to see => 14 @ 250KHz, 65@ 200KHz => 210.76923Khz, > It also seems strange to not see 200KHz, 250KHz... ? We started with a 1 MHz clock. Right. The above recipe repeats after 14*5 + 65*4 cycles. That's a total of 381 uSec, or 2.624671 KHz. How do I get 200 KHz or 250 KHz from that? What harmonic? 200 / 2.624671 => 76.200026 250 / 2.624671 => 95.250033 Those aren't close enough to integers for rounding to explain the differences. (I might have fatfingered something.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76604
I have this vhdl source:
-----------------8<----------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lupicrudi is
Port ( clk : in std_logic);
end lupicrudi;
architecture Behavioral of lupicrudi is
signal count: std_logic_vector(7 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
count <= count + 1;
end if;
end process;
end Behavioral;
-----------------8<----------------------------
Then I add a Chipscope pro file .cdc, but I cannot find 'count' signal when
I setup net connections of trigger port.
How can I obtain chipscope pro to read count value?
thanks
--
Mastupristi?
Article: 76605Mastupristi a écrit: > I have this vhdl source: > [...] > Then I add a Chipscope pro file .cdc, but I cannot find 'count' signal when > I setup net connections of trigger port. > How can I obtain chipscope pro to read count value? Your signal is not used anywhere so it is optimized away. -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 76606
Your module does not have an output signal, so I assume that the synthisizer synthisized the entire module away... try the following code: entity lupicrudi is Port ( clk : in std_logic count : out std_logic_vector (7 downto 0)); end lupicrudi; architecture Behavioral of lupicrudi is signal count: std_logic_vector(7 downto 0); begin process (clk) begin if rising_edge(clk) then count <= count + 1; end if; end process; count_out <= count; end Behavioral Moti.Article: 76607
sorry I had a typo use the following code : entity lupicrudi is Port ( clk : in std_logic coun_out : out std_logic_vector (7 downto 0)); end lupicrudi; architecture Behavioral of lupicrudi is signal count: std_logic_vector(7 downto 0); begin process (clk) begin if rising_edge(clk) then count <= count + 1; end if; end process; count_out <= count; end Behavioral Moti.Article: 76608
On Tue, 07 Dec 2004 12:53:07 +0100 Nicolas Matringe <matringe.nicolas@numeri-cable.fr> wrote: > Mastupristi a =E9crit: > > I have this vhdl source: > >=20 > [...] > > Then I add a Chipscope pro file .cdc, but I cannot find 'count' signal > > when I setup net connections of trigger port. > > How can I obtain chipscope pro to read count value? >=20 > Your signal is not used anywhere so it is optimized away. How to avoid the optimization of this signal? I use it only for debug purpose so I don't want (and I don't have space) to put it out. thanks --=20 Mastupristi?Article: 76609
Viktor Steinlin wrote: > Hello Marc > > The is that for the DDR2 SDRAM controller, the time constraints are such > that the higher speed grade is required, which increases the FPGA cost by > about $100. We would clock the DDR2 with a clock frequency at the lower > bound (say 133 MHz), so that theoretically it should work with the lower > speed grade. But we are not quite sure if this would really work. > A distributor of Micron memory suggested to use DDR2 because normal DDR > would solwly disappear during 2005. Howdy Viktor, I would agree with the distributor - always go with the newest *available* DRAM technology you can to insure future availability of the individual ICs. I say available, because if something that is just being rolled out, the big boys will get all the parts and leave none for you. > For RocketIO board-to-board communication we plan to use serial ATA cables > and connectors, with bandwidth up to 2Gbits/s, with a cable length around > 50cm, using XC2VP30. I see that there is a serial ATA II spec out now... I don't know how it compares against the original serial ATA spec, but if it calls for improved cables, that may be something to check into. With the different pre-emphasis and signal swing options that are available with the Rocket I/O, I suspect you will not have any trouble going 50cm on such a cable. If you discovered that running at 2 Gbps didn't provide enough of an data eye, you could channel bond two or four RocketIO's together and run them at a slower speed. > Did you already use RocketIO? Which speed? Did you encounter any problems? You may be interested in a few other responses to the same question a few weeks ago: http://groups.google.com/groups?selm=cnsj5c%24dqr%241%40sunnews.cern.ch Part of my response to him is below: We have successfully used the RocketIO in the V2Pro in a number of applications. There was a small learning curve associated with getting it configured correctly in the HDL, but haven't had any problems with the physical parts. Here are the configurations we've run: 2VP7-6FG456I: dual OC-48 (2.488 Gbps) across 12" of trace and a 3" backplane. 2VP50-5FF1152I: dual GbE user interfaces connected directly to fiber transceivers 2VP4-6FG456I: dual OC-48 (2.488 Gbps) across ~40" of trace and 3" backplane 2VP40-5FF1152I: single GbE backplane interface The most impressive app is the first one. The FG676 package is less than ideal for Rocket I/O since it is not a flip chip package. Not only that, but we have a 622 MHz global clock driving a little bit of logic, plus the device has a source-sync 4 bit x 622 SDR interface, in addition to something around 40% of the chip running at 311 MHz (including a number of the BRAM's). The rest runs a mix of 77 and 155 MHz. All BRAMs are used. In short, I think we're doing a pretty good job of exploring the limits on that chip, and the MGT keeps running error free, even at industrial temperatures (junction of 100C). Having used them, here are my suggestions: 1. Follow the Xilnix guidelines for power filtering on the MGT and vccaux. 2. Use a low jitter clock reference for the MGT. No PLL or DLL sources. A cheap crystal osc will do just fine. 3. Use the BREFCLK pin for the MGT if possible. 4. Use the flip-chip package if possible. Not a requirement, but it'll just make signals, ground, and power just that much better. Even just doing the first two items should result in the MGT working just fine for you. My opinion changes slightly if you are considering the V2ProX (2.488 to 10 Gbps) devices. They can be made to work (at less than 10 Gbps), but there is some (or at least, was) errata, and possibly some trial and error involved, depending on which mode you are operating in. Good luck, Marc -- Tired of popups and Microsoft security problems? Get the free Mozilla Firefox web browser: http://www.getFirefox.com/Article: 76610
Hey, Looks like Xilinx.com got hacked this morning.. I went to look through some answer records and was offered Viagra instead. Make it your ASIC indeed! //ian.Article: 76611
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:cp24o5$k36$1@gnus01.u.washington.edu... > > > Arash Salarian wrote: > (snip regarding ISA interface) > >> -Pulse Polarity: You should send a Positive voltage for the interrupt >> -Pulse length: There is no minimum or maximum!! You should keep the IRQ >> high till you recieve the acknowlege from the interrupt handler. But >> there is no interrupt acknowlege line on ISA!? So in practice, you should >> use something like a D flip-flop and connect the output to the IRQ line. >> When you reach the interrupt routine, the software should write to a port >> to clear this flip-flop using its asyc reset (or sync reset: the one that >> is simpler for you). Now, you may ask how on earth would it be possible >> to share the same interrupt line between different cards? but the answer >> would be a long story.... > > I thought ISA was edge triggered, which is the reason it is > hard to share IRQ lines. Newer ones are level triggered so that > the request will stay after the first is serviced, and be processed > later. > > -- glen Actually you can change the trigger the behavior of the ISA interrupts (to level or edge) by programming the 8259 interrupt controller chip on the motherboard and intrestingly, by default it is programmed differently on different operating systems! I could only assum the OP was about using the ISA card with windows that normally sets the trigger to level for the ISA bus. Regards ArashArticle: 76612
viron wrote: > ? Yeah, sorry... disregard. Turns out it was our corporate DNS server that got hacked. You can now go back to your regularly scheduled program... //ian.Article: 76613
Rudi, > It's doable in hardware, but extremely complex. The enumeration > process needs quite a bit of decisions making. Is it possible to "cheat" and reduce this complexity, if I know that I will literally only ever have exactly zero one specific device connected? Are there any free/commercial IP cores around that could help with this? > Not sure what your interpretation of "high bandwidth" is, but > USB 2.0 only goes to 480 Mbits/sec, or about 60Mbyes/sec. So > it should be quite trivial to do this in FPGA. However you > will need a High Speed USB PHY. It doesn't matter if it can be done completely in hardware. The only reason I wanted to mention high-bandwidth was for the case where I would have to use a soft-core processor as the complexity of driving the USB host controller is too great to be feasible in anything but software. Then of course I would have the consideration that the processor would need to be fast enough to handle passing through the data. Thanks for the suggestions, - JakeArticle: 76614
All, http://www.xilinx.com/bvdocs/whitepapers/wp218.pdf For anyone interested in how V4 really stacks up. AustinArticle: 76615
"Jacob Bower" <jacob.bower@gmail.com> wrote in message news:slrncrbkfa.pma.jab00@sprite.doc.ic.ac.uk... > Rudi, > > > It's doable in hardware, but extremely complex. The enumeration > > process needs quite a bit of decisions making. > > Is it possible to "cheat" and reduce this complexity, if I know that I will > literally only ever have exactly zero one specific device connected? that makes it a lot simpler, in very minimal case you possible only need setAddress and setConfiguration to put the device in "configured" state. After that you possible can do the special tasks for the gadget as you need it. If you need different devices to be supported or even worse need to support hubs then the host enumeratio would be way more complex. > Are there any free/commercial IP cores around that could help with this? > commercial sure are available, but I guess none of the existing ones is directly optimized to support one gadget and doing it in fpga directly. Choices are 1) SoC + bus peripheral USB host ip core 2) same as above but with some dedicated logic that "routes" some endpoints/buffers to on fpga dedicated handler to achive maximum bandwidth and bypass the cpu directly. - this is most likely not needed free, hm I think there is no free HS host as of today > > Not sure what your interpretation of "high bandwidth" is, but > > USB 2.0 only goes to 480 Mbits/sec, or about 60Mbyes/sec. So > > it should be quite trivial to do this in FPGA. However you > > will need a High Speed USB PHY. > > It doesn't matter if it can be done completely in hardware. The only reason > I wanted to mention high-bandwidth was for the case where I would have to > use a soft-core processor as the complexity of driving the USB host > controller is too great to be feasible in anything but software. Then of > course I would have the consideration that the processor would need to be > fast enough to handle passing through the data. > > Thanks for the suggestions, > - Jake yes, if you need the absolute maximum possible bandwidth then any fpga softcore processor would have it hard time shuffling the data, most likely there would be some "gaps" of time when the cpu has not managed to fill/empty some buffer at the time when the usb bus would be ready. If the usb ip core uses dma and data is mostly in big chunks the soft overhead is very small, if the cou has todo something between packets (and if packets are small) then software overhead increases. AnttiArticle: 76616
Austin Lesea wrote: > > All, > > http://www.xilinx.com/bvdocs/whitepapers/wp218.pdf > > For anyone interested in how V4 really stacks up. Stacks up to what? FPGA-90 is no product that I am aware of. Why can't Xilinx use the name of the competition part? Otherwise this is a pretty pointless paper. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76617
Austin Lesea wrote: > All, > > http://www.xilinx.com/bvdocs/whitepapers/wp218.pdf > > For anyone interested in how V4 really stacks up. > > Austin Recheck Table 2. The VHDL code is swapped. Kolja SulimmaArticle: 76618
> 2. Use a low jitter clock reference for the MGT. No PLL or DLL > sources. A cheap crystal osc will do just fine. Many of the fast delivery oscillator packages now include a PLL and get programmed at the last minute rather than grinding a special crystal. What sort of jitter is acceptable? Are the PLLs in such an oscillator good enough if there aren't any other PLLs? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76619
Please give more info about the board / cable. Is this a Xilinx Parallel port cable? The error indicates that the FPGA did not complete the configuration process. There is a DONE pin on the FPGA that you can probe to see if it goes high or not, there is also the INIT_L line to check. If there is a transmission error on the cable (ie, flaky connection to your board) you may be getting CRC errors in the bitstream. In that case, the FPGA should drive INIT_L low to indicate an error (as well as DONE remaining low).Article: 76620
Austin, Are the blocks of code misplaced in Table 2? I'd say the code on the left had two levels of pipeline. Cheers, Syms. "Austin Lesea" <austin@xilinx.com> wrote in message news:cp4k3n$puu1@cliff.xsj.xilinx.com... > All, > > http://www.xilinx.com/bvdocs/whitepapers/wp218.pdf > > For anyone interested in how V4 really stacks up. > > AustinArticle: 76621
Hi Austin, I just had a quick look, and there seems to be a mistake in table 2, p.5 (Verilog descriptions should be swapped for one stage vs two stage pipeline). Regards, Steven Austin Lesea wrote: > All, > > http://www.xilinx.com/bvdocs/whitepapers/wp218.pdf > > For anyone interested in how V4 really stacks up. > > AustinArticle: 76622
"Austin Lesea" <austin@xilinx.com> wrote in message news:cp4k3n$puu1@cliff.xsj.xilinx.com... > All, > > http://www.xilinx.com/bvdocs/whitepapers/wp218.pdf > > For anyone interested in how V4 really stacks up. > > Austin there was one good pointer in the above Xilinx white paper! its on page 6 www.opencores.org ! :) and yes looks like Stratix just got a new name: "FPGA-90nm"! LOL, if "FPGA-90nm" is now reference/alias to Altera Stratix then its good add for them! or? AnttiArticle: 76623
I want to learn Verilog for small FPGA degigns. I don't have a background in VHDL but I am an experienced designer. For simple designs, I have used the schematic capture method. What do you guys recommend? -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 76624
Al Clark wrote: > I want to learn Verilog for small FPGA degigns. I don't have a background > in VHDL but I am an experienced designer. For simple designs, I have used > the schematic capture method. > > What do you guys recommend? I recommend Verilog HDL by Samir Palnitkar. It is the best Verilog book for a beginner (people who never been exposed to HDLs but familiar with logic design). The author explains exactly what's going on in each line of the code. Other authors usually just give you a bunch of examples without explanation. The book helped me to complete my projects with great success. For more explanation please see my review at amazon.com. Hendra
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