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Hi Marc, many thanks for your suggestions! It worked, but afterwards I got some problems with product terms. That's why I switched to buffers now. They can be located anywhere in the CPLD, so that I am not that restricted anymore.. Greetings, Stephan "Marc Randolph" <mrand@my-deja.com> schrieb im Newsbeitrag news:1103027985.683504.75530@f14g2000cwb.googlegroups.com... > Stephan Mueller wrote: > > Hi, > > > > I have a quit simple question abaut cpld fitting: > > I'm using a Xilix Coolrunner (XPLA3) CPLD with pin locking and trying > to > > access a SRAM. > > If I try to fit my code, the following error message is given by the > fitter > > for some pins: > > > > WARNING:Cpld:1081 - Cannot assign signal 'sram_data<22>' to location > > '73=FB16_3'. Not enough control terms. > > > > Searching the Xilinx answer data base I came across a posting ( > > > http://university.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=19477 > > ) in which this problem was described and the following workaround > was > > presented: > > > > Adjust the design to remove unnecessary unique control term usage > (for > > example, use synchronous reset or preset as opposed to asynchronous > reset or > > preset, and use synchronous load as opposed to asynchronous load). > > > > Unfortunalty I don't know what a "synchronous reset or preset " > means! Does > > this means that I have to have an synchronous reset for the cpld > device > > (which I have) or does this mean that the macrocell itself should > somehow be > > reseted synchonously? And how do I do that?? > > Howdy Stephan, > > They are referring to the reset for the flip-flop in the macrocell. > > I'm a tad rusty on CPLD design, so I don't know how much it is really > hurting you, but it looks like you are inferring latches rather than > FF's on a number of your signals. Latches typically require extra > feedback, which can chew up extra resources. Since on CPLD"s most of > the inputs already feed into the interconnect, this is probably less of > an issue, but it still might be pushing you over the edge. > > To get around this, every signal that has assignment within the reset > clause should also have an assignment after the "else" that is > associated with your synchronous reset (which I couldn't help but > notice is commented in your code). > > You can do this by either assigning all signals in each and every one > of your states, or you can make a default assignment (so you only have > to do it once) immedately before the case statement. > > Have fun, > > Marc > > > > [...] > > > --//////////////////////////////////////////////////////////////////////// // > > /////////////// > > > > if (CLK'event and CLK = '1') then > > > > > --//////////////////////////////////////////////////////////////////////// // > > /////////////// > > -- > > -- synchronous RESET > > -- > > > --//////////////////////////////////////////////////////////////////////// // > > /////////////// > > > > if RESET_not = '0' then > > -- usb > > EF_not <= '1'; > > FF_not <= '1'; > > > > --sram > > sram_adsc_not <= '1'; > > sig_sram_bw_not <= "1111"; > > sig_sram_add <= '0'; > > sram_oe_not <= '0'; > > -- sram_adsp_not <= '1'; > > sram_data <= (others => 'Z'); > > sram_address_sig <= (others => '0'); > > testpin <= (others => '1'); > > --testtest > > -- state <= IDLE; > > state <= SRAM_FILL_1; > > -- state <= SRAM_OUT_WAIT; > > -- state <= GET_LENGTH; > > -- data_length <= X"0080"; > > -- command_state <= IDLE; > > -- command_state <= SRAM_OUT; > > -- end testtest > > > > else > > > > > > case state is > > > > > --//////////////////////////////////////////////////////////////////////// // > > /////////////// > > -- > > -- IDLE > > -- > > > --//////////////////////////////////////////////////////////////////////// // > > /////////////// > > > > when IDLE => > > > > testpin( 15 downto 12) <= "0000"; > > > > > > -- test > > if userset_not = '0' then > > testpin(0) <= '0'; > > state <= SRAM_FILL_1; > > end if; > > > > > > > > > --//////////////////////////////////////////////////////////////////////// // > > /////////////// > > -- > > -- USER SRAM DELETE > > -- > > > --//////////////////////////////////////////////////////////////////////// // > > /////////////// > > > > when SRAM_FILL_1 => > > > > testpin( 15 downto 12) <= "1001"; > > testpin(1) <= '0'; > > > > -- all Bytes > > sram_adsc_not <= '0'; > > sig_sram_bw_not <= "0000"; > > sram_oe_not <= '1'; > > sram_address_sig <= sram_address_sig + '1'; > > sram_data(15 downto 0) <= (others => '0'); --sram_address_sig; > > sram_data(31 downto 16) <= (others => '0'); --sram_address_sig; > > > > state <= SRAM_FILL_2; > > > > > > when SRAM_FILL_2 => > > > > -- testpin( 15 downto 12) <= "1010"; > > -- testpin(2) <= '0'; > > testpin <= sram_address_sig; > > -- test > > --if userset_not = '0' then > > > > > > sram_address_sig <= sram_address_sig + '1'; > > > > if sram_address_sig(15) = '1' then > > -- end > > testpin(4) <= '1'; > > state <= IDLE; > > sram_adsc_not <= '1'; > > sram_oe_not <= '0'; > > sig_sram_bw_not <= "1111"; > > sram_address_sig <= (others => '0'); > > sram_data <= (others => 'Z'); > > -- else > > -- write another word > > -- sram_data(15 downto 0) <= (others => '1'); --sram_address_sig; > > -- sram_data(31 downto 16) <= (others => '1'); > --sram_address_sig; > > end if; > > > > --end if; > > > > > > > --//////////////////////////////////////////////////////////////////////// // > > /////////////// > > -- > > -- OTHER States > > -- > > > --//////////////////////////////////////////////////////////////////////// // > > /////////////// > > > > when others => > > state <= IDLE; > > > > end case; > > end if; > > > > end if; > > > > end process; > > > > > --//////////////////////////////////////////////////////////////////////// // > > /////////////// > > -- > > -- End PROCESS MAIN > > -- > > > --//////////////////////////////////////////////////////////////////////// // > > /////////////// >Article: 76876
> Stupid me! > You were right! > I cut the PCB traces of the VCCINT pins off the 3V3 rail and straped > them to 1V5 - works perfectly! No heat, no config mess-up. Thanks for > the advice. I guess it was obvious to the experinces guys out there. I > slaped myself a few times after carefully looking over the datasheet. I > guess now I have to clean up my reputation :). > Thanks for helping! Spank yourself with a soldering iron while reciting the complete Cyclone manual 5 times (including appendix) and you'll receive an absolution from the Almighty FPGA...Article: 76877
Hi I would like to know if any of you knows a good paper (app note etc.) that describes the xilinx slice sturcture in details, I know the general cell architecture (e.g. - two LUTs, Two regs and carry logic) but I wanted to get a lot more fimiliar with the architecture and functionally of each logic element in the cell, for example how exactly does the carry logic is structured etc. The reason for this qeustion is that I want to implement arithmetic block using as less logic and routing as possible I wonder if there is an application note that explains how to code and route your arithmetic functions in a way that is best suitable for the xilinx chip (spartan 2E). So if any of any of you is fimiliar with such a paper I will be grateful for a link. Regards MCArticle: 76878
We are using a Stratix device and have an extensive verilog test bench. When we use the behavioral models altera_mf.v and 220model.v that come from Quartus II version 4.2 (just out) and run the test bench (with vcs) it compiles just fine but gets lots of errors. Many of the failures were things like register X reads xxx and should be something real. I thought maybe I might have to regenerate all the RAMs and such that were generated with the Megawizard plug in manager so I did that. It had no effect. I do not have time to track down the specifics of why we got failures since I have a chip to develop. Needless to say I have gone back to 4.1 SP2 and its altera_mf.v and 220model.v, which work just fine. Does anyone else have experience, good or bad, with 4.2? NateArticle: 76879
Petter Gustad wrote: > Sean Durkin <smd@despammed.com> writes: > > > This makes vias in the signal path unavoidable, something I'd rather > > not do if it can be avoided somehow. Any tips or tricks for this? > > Swap the differential pairs and to polarity inversion on the receiver. The p vs n trace order is just a matter of how you route out of the pin field... I believe you can achieve either order at will. I like Symon's idea of rotating one chip 180 degrees, but if the OP had to keep them pointed the same direction for some crazy reason, he could use the middle MGT for the TX and then one of the MGT's on either side of it for RX, as needed. This only has to be done with one of the devices - the other device can continue using a single MGT for both RX and TX. Hopefully the OP has a good clock reference and is using a fast speed grade device... 3.125 Gbps is humming! > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail? Great sig! Marc -- http://www.getFirefox.com 10 million downloads in the past month. Do YOU have it?Article: 76880
I think if you connect them head to head (top of device to top), then the TX pads will face the RX pads. You can ignore the pair polarity, since the receivers have a control bit to do polarity inversion. John On Tue, 14 Dec 2004 14:44:33 +0100, Sean Durkin wrote: > Hi *, > > I'd like to establish a high-speed connection between two > Virtex-II-Pro-FPGAs, using several bidirectional > 3,125Gbit/s-RocketIO-links in parallel (using e.g. Aurora). How do I > route something like this properly? > > If I want to connect 2 FPGAs that are directly adjacent to each other, > the TX-pads are always opposite other TX-pads, and RX-pads always > opposite other RX-pads. So the way I see it I'd have to cross each and > every TX/RX-pair, like it's usually done in a cross-over-cable... > > This makes vias in the signal path unavoidable, something I'd rather not > do if it can be avoided somehow. Any tips or tricks for this? > > cu, > SeanArticle: 76881
Hello, i'm trying to implement a obp-ipif with a master attachement to the bus. I managed to to implement an ipif based on the example provided with the edk 6.2. But this example is very basic: no interrupts.. When comparing my implementation to ipifs created with the peripheral wizard (slaves only :( ) , it doesn't seem too easy to plug an interrupt controller into that ipif (i am a beginner in writinhdl-code). So i'd like to ask if somebody knows any useful/demonstrative(/easy to understand) examples of dma-capable opb/plb-ipif-implementations (You need to have a master attachement to use dma, don't you?). Best regards Patrick SiegelArticle: 76882
Marc Randolph wrote: > I like Symon's idea of rotating one chip 180 degrees, but if the OP had > to keep them pointed the same direction for some crazy reason, he could > use the middle MGT for the TX and then one of the MGT's on either side > of it for RX, as needed. This only has to be done with one of the > devices - the other device can continue using a single MGT for both RX > and TX. Problem is I need to use *ALL* MGTs, so that wouldn't work for me. But Symon's rotating-solution is perfect. > Hopefully the OP has a good clock reference and is using a fast speed > grade device... 3.125 Gbps is humming! I'm using the Pletronics oscillator Xilinx recommends in the RocketIO-User-Guide. Speed-Grade is -6 and it's a device in a flipchip-package, so at least according to the Xilinx-specs that should be capable of 3.125Gbps. cu, SeanArticle: 76883
Peter, Thanks for responding. I understand pretty well the reasons behind speed binning and how artificial the boundaries are; however, there must be some overall criteria Xilinx uses to determine where to set those boundaries. When they bin their parts, they must be measuring several parameters and deciding that the aggregation of those measurements must be in a certain range to qualify as a -6. How does Xilinx decide what that range is? Craig "Peter" <peter@xilinx.com> wrote in message news:1103072858.873114.286400@f14g2000cwb.googlegroups.com... > Craig, remember that "speed grades" are an artificial way of > segregating devices that are naturally made with a continuum of > performance parameters. To accomodate the unavoidable manufacturing > spread, IC manufacturers sort the devices into bins, so that they can > guarantee performance, but also sell the devices that came out slow or > "not so fast". > In a perfect world, all parameters would scale perfectly, i.e. a device > marked slow would have all its delays longer by the same factor, as > compared to the devices labeled fast. > The world is not perfect. > The only thing you can be sure of is that you will never buy a part > that is slower than its specification. > All parameters will be better than the spec, but not all by the same > percentage. > Let me therefore discourage you from your elaborate plans. There is no > simple answer. > Peter Alfke > ============================== > Craig Conway wrote: >> I'm trying to determine the delay curve of a particular path in a >> Virtex2Pro -5 from min timing to max, including all points in > between. >> Obviously I can get the two end points (min and max) from the timing >> analyzer, but I assume that points between the two don't necessarily > fall on >> a straight line. I considered also plotting the max timing of the > other >> speed grades (-7 and -6), but I don't know what their relationship to > each >> other is, so I wouldn't know exactly where to plot them relative to > the -5 >> max endpoint. >> >> If anyone knows where performance graphs might exist in the Xilinx >> documenation, or what the relationship of speed grades to each other > is, I'd >> be most appreciative of a response. >> >> Thanks! >Article: 76884
MC wrote:
>Hi
>I would like to know if any of you knows a good paper (app note etc.)
>that describes the xilinx slice sturcture in details, I know the
>general cell architecture (e.g. - two LUTs, Two regs and carry logic)
>but I wanted to get a lot more fimiliar with the architecture and
>functionally of each logic element in the cell, for example how exactly
>does the carry logic is structured etc.
>
>The reason for this qeustion is that I want to implement arithmetic
>block using as less logic and routing as possible
>I wonder if there is an application note that explains how to code and
>route your arithmetic functions in a way that is best suitable for the
>xilinx chip (spartan 2E).
>
>So if any of any of you is fimiliar with such a paper I will be
>grateful for a link.
>
>Regards
>MC
>
>
>
No need to study a paper on this. Open the FPGA editor tool. All the
information you need is there.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 76885
fwj_733 wrote:
>There is a lot of square operations in my FPGA projects (using Xilinx VitexE). Now, I complete them by multiple, but this method is slice consuming and slow. As we know, square operation has many characters, which multiple operation of any random numberic don' have, then could we utilize these features to calculate square operations more economical and more fast? Thanks for all advice. Best Regards
>
>
You really need to give us more information. Are the squares sequential
(eg squares of an arithmetic progression of values)? How many clock
cycles per square are available? How many bits? Do you have BRAM
available? Do you have area restrictions? etc. As with many other
problems, there are many ways to approach this.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 76886I have a bdf schematic with some pins labeled DAI[13..1] & and DAI[14], DAI [15], etc. I have different pins labeled in a similar fashion for example IO_Bus[10..0]. I then assigned pins to DAI[1], DAI[2], etc. in the assignment editor. After I compile, Quartus creates new assignments of my DAI pins to DAI1, DAI2, DAI3, etc and ignores all my DAI[1], DAI[2], etc assignments. Other non-DAI pin assignments keep the brackets, IO_Bus[0], IO_Bus[1] Why are the brackets dropped in some cases at not in others? -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 76887
Sorry for not giving sufficient info. The squares works parallel, that is, one clock cycle per square. Bits width of Operand are about 10~20. VirtexE do have BRAM, I use Virtex600E, and the remaining maximum capacity for square operation is 128 Kb. I hope square of a 20bit number can be completed by less than 30 VirtexE slices, and work above 70MHz. I still wonder, for a multiplier written as: use IEEE.std_logic_arith; ... C<=A*B; ... Does ISE synthesis this multiplier most efficient in area sense? If not, how can I complete it more efficient?Article: 76888
"fwj_733" <fwj@nmrs.ac.cn> wrote in message news:ee8aa81.2@webx.sUN8CHnE... > Sorry for not giving sufficient info. The squares works parallel, that is, > one clock cycle per square. Bits width of Operand are about 10~20. VirtexE > do have BRAM, I use Virtex600E, and the remaining maximum capacity for > square operation is 128 Kb. I hope square of a 20bit number can be > completed by less than 30 VirtexE slices, and work above 70MHz. I still > wonder, for a multiplier written as: use IEEE.std_logic_arith; ... C<=A*B; > ... Does ISE synthesis this multiplier most efficient in area sense? If > not, how can I complete it more efficient? Generally modern synthesize tools generate a very high quality result for basic operatinos like add, multiply. Both Xilinx and Altera have already highly optimized macros for these operations (remember LPMs?) and usually they are hand optimized and very efficient. The synthesize tool selects from a library of these pre-made macros for these operations. Also the output generated for C <= A*B is different from C <= A*A and the tool selects a different macro which can be potentially more optimized for this case. So unless you have a very special need you can just type the operations in high level and let the synthesize tool take care of it. Regards Arash SalarianArticle: 76889
Hi Is there a significant difference in the time it takes to download a configuration to an Altera Cyclone (EP1C6) using JTAG, vs. the Passive Serial Configuration method? In January, Greg Steinke here mentioned a program to program a Serial Configuration Device (e.g. EPCS1) _through_ a Cyclone, with the programmer attached only to the Cyclone's JTAG port. It was beta, then. Is this option available in e.g. Quartus today, or even available as source code (a "combined" Jrunner + Srunner?). Thanks for info KoljaArticle: 76890
Craig, Before we fabricate the device (ie after we tape out) we examine the spice model corners, and decide what range of speed we can expect. We then decide to bin based on a yield goal into each speed bin. Once we have the parts, we fine tune the process with our fab partners to get what we designed to (after all, if the models don't match, how in the hell can we know if it will work?). Then, by construction, we have the yield (or better) to the bins we desired. Every technology node is different (process changes with each generation). So, take Peter's advice, Austin Craig Conway wrote: > Peter, > > Thanks for responding. I understand pretty well the reasons behind speed > binning and how artificial the boundaries are; however, there must be some > overall criteria Xilinx uses to determine where to set those boundaries. > When they bin their parts, they must be measuring several parameters and > deciding that the aggregation of those measurements must be in a certain > range to qualify as a -6. How does Xilinx decide what that range is? > > Craig > > "Peter" <peter@xilinx.com> wrote in message > news:1103072858.873114.286400@f14g2000cwb.googlegroups.com... > >>Craig, remember that "speed grades" are an artificial way of >>segregating devices that are naturally made with a continuum of >>performance parameters. To accomodate the unavoidable manufacturing >>spread, IC manufacturers sort the devices into bins, so that they can >>guarantee performance, but also sell the devices that came out slow or >>"not so fast". >>In a perfect world, all parameters would scale perfectly, i.e. a device >>marked slow would have all its delays longer by the same factor, as >>compared to the devices labeled fast. >>The world is not perfect. >>The only thing you can be sure of is that you will never buy a part >>that is slower than its specification. >>All parameters will be better than the spec, but not all by the same >>percentage. >>Let me therefore discourage you from your elaborate plans. There is no >>simple answer. >>Peter Alfke >>============================== >>Craig Conway wrote: >> >>>I'm trying to determine the delay curve of a particular path in a >>>Virtex2Pro -5 from min timing to max, including all points in >> >>between. >> >>>Obviously I can get the two end points (min and max) from the timing >>>analyzer, but I assume that points between the two don't necessarily >> >>fall on >> >>>a straight line. I considered also plotting the max timing of the >> >>other >> >>>speed grades (-7 and -6), but I don't know what their relationship to >> >>each >> >>>other is, so I wouldn't know exactly where to plot them relative to >> >>the -5 >> >>>max endpoint. >>> >>> If anyone knows where performance graphs might exist in the Xilinx >>>documenation, or what the relationship of speed grades to each other >> >>is, I'd >> >>>be most appreciative of a response. >>> >>> Thanks! >> > >Article: 76891
gja, All single ended non reference voltage standards use the same schmidt trigger single ended input circuit. All single ended reference voltage standards use the same differential comparator which has one input tied to Vref. All differential input standards use the same differential comparator (different that the single ended Vref one above). These three input circuits are selected by the type of standard chosen, and are designed to operate over the range of the Vcco voltages used, and designed to meet all input standards stated. The actual specifications obviously exceed (are better than) what is required by a standard, as the circuits have to do all of the jobs, over all process, voltage, and temperature corners. The published specifications are those of the standards, as publishing anything else would confuse those who don't understand how to interpret the specifications (like some purchasing agents or component engineers who mindlessly compare us to our competition). Austin gja wrote: > For Virtex II parts, I see that the Vih and Vil levels are the same for > LVTTL and LVCMOS33, my question is are the input structures really different > or are they the same for the two standards. Also, are the output structures > for LVTTL the same as LVCMOS33, since both Vol are the same, and LVTTL Voh > is a subset of LVCMOS33 Voh. > >Article: 76892
Austin, just a quick question. Do many devices fail to meet your parametric specification, i.e. have performance that does not satisfy the lowest speed grade? Thanks, On Wed, 15 Dec 2004 08:02:39 -0800, Austin Lesea <austin@xilinx.com> wrote: >Craig, > >Before we fabricate the device (ie after we tape out) we examine the >spice model corners, and decide what range of speed we can expect. We >then decide to bin based on a yield goal into each speed bin. > >Once we have the parts, we fine tune the process with our fab partners >to get what we designed to (after all, if the models don't match, how in >the hell can we know if it will work?). Then, by construction, we have >the yield (or better) to the bins we desired. > >Every technology node is different (process changes with each generation). > >So, take Peter's advice, > >Austin > >Craig Conway wrote: >> Peter, >> >> Thanks for responding. I understand pretty well the reasons behind speed >> binning and how artificial the boundaries are; however, there must be some >> overall criteria Xilinx uses to determine where to set those boundaries. >> When they bin their parts, they must be measuring several parameters and >> deciding that the aggregation of those measurements must be in a certain >> range to qualify as a -6. How does Xilinx decide what that range is? >> >> Craig >> >> "Peter" <peter@xilinx.com> wrote in message >> news:1103072858.873114.286400@f14g2000cwb.googlegroups.com... >> >>>Craig, remember that "speed grades" are an artificial way of >>>segregating devices that are naturally made with a continuum of >>>performance parameters. To accomodate the unavoidable manufacturing >>>spread, IC manufacturers sort the devices into bins, so that they can >>>guarantee performance, but also sell the devices that came out slow or >>>"not so fast". >>>In a perfect world, all parameters would scale perfectly, i.e. a device >>>marked slow would have all its delays longer by the same factor, as >>>compared to the devices labeled fast. >>>The world is not perfect. >>>The only thing you can be sure of is that you will never buy a part >>>that is slower than its specification. >>>All parameters will be better than the spec, but not all by the same >>>percentage. >>>Let me therefore discourage you from your elaborate plans. There is no >>>simple answer. >>>Peter Alfke >>>============================== >>>Craig Conway wrote: >>> >>>>I'm trying to determine the delay curve of a particular path in a >>>>Virtex2Pro -5 from min timing to max, including all points in >>> >>>between. >>> >>>>Obviously I can get the two end points (min and max) from the timing >>>>analyzer, but I assume that points between the two don't necessarily >>> >>>fall on >>> >>>>a straight line. I considered also plotting the max timing of the >>> >>>other >>> >>>>speed grades (-7 and -6), but I don't know what their relationship to >>> >>>each >>> >>>>other is, so I wouldn't know exactly where to plot them relative to >>> >>>the -5 >>> >>>>max endpoint. >>>> >>>> If anyone knows where performance graphs might exist in the Xilinx >>>>documenation, or what the relationship of speed grades to each other >>> >>>is, I'd >>> >>>>be most appreciative of a response. >>>> >>>> Thanks! >>> >> >>Article: 76893
Don't worry about it too much-- AVNET shipped us a rev. of their Xilinx V21000 eval boards w/ a similar error. (turns out a 0 ohm resistor was mistaken for a DNP in their 1.5V regulator network) They've since fixed the problem, and have been very nice about replacing the boards, but from what I can tell, they're a major distributor, so it happens to EVERYONE. --Josh "Alex Somesan" <alex.somesan@gmail.com> wrote in message news:1103055154.853600.241580@z14g2000cwz.googlegroups.com... > Stupid me! > You were right! > Tied VCCINT to 1V5 and all works well. No heat at all. > I slaped myself a few times after going over the datasheet again, more > carefuly. > Anyway, stupid rookie mistake. I must clean my reputation now :). > Thanks for helping. > > Alex. >Article: 76894
On Wed, 15 Dec 2004 17:07:57 +0000, Jules P wrote: > Austin, > > just a quick question. Do many devices fail to meet your parametric > specification, i.e. have performance that does not satisfy the lowest > speed grade? > > Thanks, > > > > > On Wed, 15 Dec 2004 08:02:39 -0800, Austin Lesea <austin@xilinx.com> > wrote: > >>Craig, >> >>Before we fabricate the device (ie after we tape out) we examine the >>spice model corners, and decide what range of speed we can expect. We >>then decide to bin based on a yield goal into each speed bin. >> >>Once we have the parts, we fine tune the process with our fab partners >>to get what we designed to (after all, if the models don't match, how in >>the hell can we know if it will work?). Then, by construction, we have >>the yield (or better) to the bins we desired. >> >>Every technology node is different (process changes with each generation). >> >>So, take Peter's advice, >> >>Austin >> >>Craig Conway wrote: >>> Peter, >>> >>> Thanks for responding. I understand pretty well the reasons behind speed >>> binning and how artificial the boundaries are; however, there must be some >>> overall criteria Xilinx uses to determine where to set those boundaries. >>> When they bin their parts, they must be measuring several parameters and >>> deciding that the aggregation of those measurements must be in a certain >>> range to qualify as a -6. How does Xilinx decide what that range is? >>> >>> Craig >>> >>> "Peter" <peter@xilinx.com> wrote in message >>> news:1103072858.873114.286400@f14g2000cwb.googlegroups.com... >>> >>>>Craig, remember that "speed grades" are an artificial way of >>>>segregating devices that are naturally made with a continuum of >>>>performance parameters. To accomodate the unavoidable manufacturing >>>>spread, IC manufacturers sort the devices into bins, so that they can >>>>guarantee performance, but also sell the devices that came out slow or >>>>"not so fast". >>>>In a perfect world, all parameters would scale perfectly, i.e. a device >>>>marked slow would have all its delays longer by the same factor, as >>>>compared to the devices labeled fast. >>>>The world is not perfect. >>>>The only thing you can be sure of is that you will never buy a part >>>>that is slower than its specification. >>>>All parameters will be better than the spec, but not all by the same >>>>percentage. >>>>Let me therefore discourage you from your elaborate plans. There is no >>>>simple answer. >>>>Peter Alfke >>>>============================== >>>>Craig Conway wrote: >>>> >>>>>I'm trying to determine the delay curve of a particular path in a >>>>>Virtex2Pro -5 from min timing to max, including all points in >>>> >>>>between. >>>> >>>>>Obviously I can get the two end points (min and max) from the timing >>>>>analyzer, but I assume that points between the two don't necessarily >>>> >>>>fall on >>>> >>>>>a straight line. I considered also plotting the max timing of the >>>> >>>>other >>>> >>>>>speed grades (-7 and -6), but I don't know what their relationship to >>>> >>>>each >>>> >>>>>other is, so I wouldn't know exactly where to plot them relative to >>>> >>>>the -5 >>>> >>>>>max endpoint. >>>>> >>>>> If anyone knows where performance graphs might exist in the Xilinx >>>>>documenation, or what the relationship of speed grades to each other >>>> >>>>is, I'd >>>> >>>>>be most appreciative of a response. >>>>> >>>>> Thanks! >>>> >>> >>> If they had a significant number of parts that failed to meet the lowest speed grade but otherwise worked they would just introduce a lower speed grade. In fact Xilinx offers parts that don't work completely. Some parts have slight defects which effect only a subset of designs. You can give Xilinx a bit file and a set of test patterns and they will test their slightly defective parts to see if they will work for your application, if they do they will sell them to you at a huge discount. It's the same principle as hog butchers, they sell everything except the squeal.Article: 76895
Peter wrote: > It's amazing how everything can become a Xilinx vs Altera battle. > It seems to me that the original posting was not really looking for the > most compact solution. Both Altera and Xilinx can of course provide > RAM-based shift registers, and as long as you stay below 16K length, > the A and X solutions are indistinguishable. > But let me fix one bad misstatement: > It does of course take 45 SRL16s to implement a 720 bit shift > register, but these 45 SRL16s fit in lessthan six CLBs, since there are > eight LUTs in a CLB. > That takes less silicon area than any big RAM in either Altera or > Xilinx chips... For the user, though, it is more complicated. If the RAMs are otherwise unused then they go to waste in the SRL16 case. If one is short on RAM resources, brand A may be at a disadvantage. In the beginning FPGA's had only one type of cell, and the only question was how many were requried. Now, one has to balance different designs based on the numbers of CLBs, RAMs, and anything else that may be added. Also, as pointed out in another post, different FPGAs may have different sized RAMs which may affect the optimal solutions to these problems. -- glenArticle: 76896
Austin, thank you very much for your response. You may have addressed it, but it was not clear to me, what about the output structures that were the second part of my question? Are LVTTL output structures the same as LVCMOS33 ? "Austin Lesea" <austin@xilinx.com> wrote in message news:cppnj8$8g81@cliff.xsj.xilinx.com... > gja, > > All single ended non reference voltage standards use the same schmidt > trigger single ended input circuit. > > All single ended reference voltage standards use the same differential > comparator which has one input tied to Vref. > > All differential input standards use the same differential comparator > (different that the single ended Vref one above). > > These three input circuits are selected by the type of standard chosen, > and are designed to operate over the range of the Vcco voltages used, > and designed to meet all input standards stated. > > The actual specifications obviously exceed (are better than) what is > required by a standard, as the circuits have to do all of the jobs, over > all process, voltage, and temperature corners. > > The published specifications are those of the standards, as publishing > anything else would confuse those who don't understand how to interpret > the specifications (like some purchasing agents or component engineers > who mindlessly compare us to our competition). > > Austin > > gja wrote: > > > For Virtex II parts, I see that the Vih and Vil levels are the same for > > LVTTL and LVCMOS33, my question is are the input structures really different > > or are they the same for the two standards. Also, are the output structures > > for LVTTL the same as LVCMOS33, since both Vol are the same, and LVTTL Voh > > is a subset of LVCMOS33 Voh. > > > >Article: 76897
Al Clark wrote: > I have a bdf schematic with some pins labeled DAI[13..1] & and DAI[14], DAI > [15], etc. (snip) > After I compile, Quartus creates new assignments of my DAI pins to DAI1, > DAI2, DAI3, etc and ignores all my DAI[1], DAI[2], etc assignments. (snip) > Why are the brackets dropped in some cases at not in others? Hopefully someone from Altera will explain it, but I have seen some effects that seem to be due to compatability with MaxPlus, which as I understand it assigned names without the brackets. As I remember .bdf is the MaxPlus extension, and .gdf is the Quartus extension. Rewrite the file as .gdf and maybe it will work. The assignments, as I understand it, are stored in a different file. Sometimes I just edit the assignments file by hand if I can't get it to work otherwise. -- glenArticle: 76898
Synplify now reads the defparam 'INIT' used for instantiated SRLs, so you can initialize the value of the SRL16 for both simulation and synthesis with a single defparam. However, I'm wondering if there is a way to infer SRL16 Johnson rings or shift registers with an initial value. This can be done with registers by setting the 'reset' value of the register to the desired value, but you can't have a reset clause with SRLs or they won't get inferred as SRLs. It would be nice to be able to infer a Johnson ring because if you want to instantiate SRLs you need to instantiate one for each 16 bits of the register which makes it hard to parameterize it.Article: 76899
Agreed. Years ago, when we offered unstructured "sandboxes" full of LUTs and flip-flops, it was easy to benchmark and compare. Now all FPGAs offer many features that are both more powerful and more dedicated. This gives the user higher performance at a lower cost, but it makes comparisons more complicated. Users should take benchmarks published by any one of the competitors with a big grain of salt, especially when they claim a vast superiority of their own product. That is often Marketing at its worst. If you are serious about evaluating X vs A, then look beyond the LUTs and memories, dig deeper into the architecture, and investigate the systems-oriented functions... Peter Alfke
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