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The following code was shown to me by a collegue. All of the logic has been removed for clarity (and to protect IP). The Synthsizer reports 3 errors that some of the signals are not declared as input, inout or output. If you remove the line comments in front of the input and output declarations, the program synthsizes as expected. 8.1 YUCK!! -EliArticle: 101451
> They do not mean they run at 2GHz _and_ @ 0.2V :) > > "operated correctly" is their carefull wording. > To me, correct (expected) operation at 0.2V is data retention. > > Target Vcc sounds ~1.2V : > "is capable of running common FPGA performance benchmark designs at up > to 1.93 GHZ at 1.2V" > > -- not sure what they were testing at 3.9V, - might have meant the > IO buffers, and probably not the Core Vcc! > >From eetimes.com: John Lofton Holt: We got 1.93-GHz equivalent performance at 21 degrees Celsius and 1.2-volts Vdd. At minus 196 degrees Celsius we got 2.3-GHz performance at 1.2-V. Performance does taper off with increased temperature. At 130 degrees Celsius we got 1.4-GHz at 1.0-V. But even more important for us is voltage scaling. As you linearly decrease the voltage you get a cubic improvement in power consumption. So at 0.6-V we got 400-MHz performance on our prototype but with an 87 percent reduction in power consumption. eetimes: But surely CMOS doesn't work at 0.2-V and at 3.9-V a device in a 90-nm process would burn up? John Lofton Holt: We've told you what we found. The chip did work down to 0.2-V and up to 3.9-V, but we did not test the chip for an extended period. Also it's true that the leakage current had increased by 50 percent when we brought the voltage back down from 3.9-V. It's also true that foundry SRAM cells would not work below about 0.8-V, but we've used proprietary SRAM cells. Cheers, JonArticle: 101452
Eli Hughes wrote: > The following code was shown to me by a collegue. All of the logic has > been removed for clarity (and to protect IP). The Synthsizer reports 3 > errors that some of the signals are not declared as input, inout or > output. If you remove the line comments in front of the input and > output declarations, the program synthsizes as expected. > > > 8.1 YUCK!! > > > > -Eli Oops, here is the verilog code: module Main(SysReset,Zero,ClkInput, UZBEERX, ROW_Q1, COL_Q1, ROW_Q2 , COL_Q2 , ROW_Q3 , COL_Q3 , ROW_Q4,COL_Q4,PSUP,PSUPo); /*inputs outputs registers wires*/ input SysReset; output Zero; input ClkInput; input UZBEERX; output [12:0] ROW_Q1; // row select quadrant1 output [12:0] COL_Q1; // column select quadrant1 output [12:0] ROW_Q2; // row select quadrant2 output [12:0] COL_Q2; // column select quadrant2 output [12:0] ROW_Q3; // row select quadrant3 output [12:0] COL_Q3; // column select quadrant3 output [12:0] ROW_Q4; // row select quadrant4 output [12:0] COL_Q4; // column select quadrant4 output [3:0] PSUP; output [3:0] PSUPo; endmoduleArticle: 101453
some long time ago writing your company name in non-ascii chars like a-umlaut a" in the schematic template header of the Xilinx ECS rendered the schematic to invalid, so you lost your work (ok it was possible to use binary editor to fix the char) - the comment type of error in Xilinx ISE/XST means that Xilinx is not using a proper qualified VHDL/verilog parser - a proper parser would not chokes on comments (in places where those are legal as per language reference) AnttiArticle: 101454
Ashu, You don't send code through the JTAG. Your code needs to be transformed into a bitstream that completely describes how all the bits in the FPGA should be set (describing what is in all of the LUTs and how they are connected). This bitstream is what you send through the JTAG. There are a number of steps between entering your code and generating this bitstream. Go to the Xilinx or Altera sites (or just google) and search for 'design flow'. Good luck, JoeyArticle: 101455
This was "Marketing at its Finest Hour" PeterArticle: 101456
Jon, A small enough area of 90nm will run for a while on 3.9 volts. But it is very likely that those gates are all overstressed, and the fact that their leakage popped up means that the devices are at "end of life." I liken this press release to one we made: (in 1999!) http://www.xilinx.com/xcell/xl31/xl31_57.pdf A demonstration of capability. What we are all waiting for is the PRODUCT with a usable set of design tools, and some cool CORES and IP so that it does something USEFUL at a reasonable COST. Right now this is a (proposed) solution looking for a problem (more likely looking for more funding). And, I am completely sincere when I said "good luck." AustinArticle: 101457
BurchED FPGA Systems, http://www.burched.biz Expansion Modules, 4-for-1 offer! Limited time! Buy 1 and get 3 for free! Unprecedented bargain. That's right, if you buy 1 unit (any of the expansion modules), you get 3 units absolutely free! What a great opportunity to get some expansion modules either for your B5-X300, or perhaps to wire up to another vendor's FPGA board. If you don't have an FPGA board, why not pick up a B5-X300 and a bunch of low cost expansion modules at the same time? This is a BELOW COST sale. We have big stocks of expansion modules & we want to liquidate some of them so that we can use the cash for our next project. The range of expansion modules includes Switches, LEDs, 7-Segment-Displays, Peripheral Connectors (VGA output, keyboard, mouse, serial RS232, plus buzzer) and the Advanced-Download-Cable (Xilinx Parallel Cable III compatible). Strictly limited time. Sale will end in 10 days. This offer will probably never be repeated again. We don't think the stock will run out but at liquidation prices, no one can say. If you act now you can get an absolutely great deal! Our chance to liquidate some stock is your chance to get some fine equipment at below cost price. Order now at our easy secure online form at https://host3.quickdns.net/burched/OrderFormCreditCard.html Sale will end in 10 days (Tuesday night, 12 May 2006). There is no limit per customer (for example if you buy 4 units, you will get 16 units - that is an incredible 12 units for free!). Best regards, Tony Burch http://www.burched.bizArticle: 101458
harikris@gmail.com wrote: > Hi, > > I am targeting the design for XC2C512 coolrunner device. That's the > biggest device i could find. Are you aware of any larger CPLD device? > I have a dual-edge triggered clock i.e i have no other CPLD choice > other than the coolrunner series. > > I find that i am falling short of a dozen macrocell counts. The > fitter report says it needs 524 macrocells and i have 512 macrocells > available to me :-( > > I have tried to optimize the design to my best possible knowledge (and > my knowledge is not that profound). > > Can anybody here advise me on how to squeeze the design a LITTLE BIT > more > to make it fit into the XC2C512 device? > > Thanks. You can try turning on the ISE options optimize density, and exhaustive fit. The result is a design that uses fewer gates, etc, but runs slower. If you accidentally created latches, they will eat up chip resources. -Dave PollumArticle: 101459
This came over the wire 5/1 from the CEO of Achronix: "The fundamental hypothesis of the company is that nobody needs to know that internally the architecture is asynchronous - and that means in terms of EDA, in terms of design, and at the foundry. In many ways making the software appear synchronous has been a bigger challenge than the hardware. " Let me paraphrase: "We are running 2GHz, but you don't need to know anything about the FPGA to use it. Oh, and by the way, the internal structure is asynchronous. The SW handles everything and it is the hardest part." John - Yes, I do need to know what you are doing internally. And yes, normally in the FPGA world, the SW is the hardest part. And the fact that you are 'asynchronous' makes me, umm, more than a little skeptical. Mike_la_jolla (mdini at dinigroup dot bomb)Article: 101460
Marco, this depends on the laws in your country. in the US, if the work is "work for hire" (typical employer / employee relationship) then the copyright is owned by the employer. iow, you can't copy it w/o their permission (you can't use it at your new employer). if you are an independent contractor, though, then you likely reatin the copyright unless you gave it away in the contract (which most companies will require in your case). the laws vary between countries, so do some research about your country specifics. good luck - and use this knowledge to get a better contract with you new employer.Article: 101461
Eli- > If you remove the line comments in front of the input and > output declarations, the program synthsizes as expected This happens in 7.1 also. A couple of years ago a Xilinx FAE told us "do not use C++ style comments for any reason except synthesis attributes" and we have followed that on blind faith. -JeffArticle: 101462
tuxfriend wrote: > Hello Peter, > thank you for the answer. But the XC3190A is big enougth for my small > projects and the package is good for hand soldering... > ..and at last I have the parts but not the money;) > For any projects I use the XC9536 and webpack 8.1i (21st century stuff!). > The Book price is about 25eur and even if the Software is not comfortable I > think its good enougth for my home build stuff. > That is the reason for my question: > Can I use the Book Software for my XC3190A? > > Thank you > tuxfriend > > Peter Alfke wrote: > > > The XC3190A was introduced 15 years ago, which makes it hopelessly > > obsolete. Even if you find the hardware sufficient (no on-chip RAM!), > > the software is so antiquated that nobody should be forced to use it. > > Get yourself a modern chip of Spartan or Virtex caliber and of 2003+ > > vintage. The hardware is cheap, and the software is free, and both are > > very competent. > > Happy designing with 21st century stuff! > > Peter Alfke, Xilinx tuxfriend; If you are concerned about soldering big chips with lots of tiny pins, there are several things you can try: 1) Some companies (Digilent comes to mind) have CPLDs or even FPGAs mounted on a board that plugs into a 40-pin 0.6" wide IC socket. 2) You can buy a CPLD or a FPGA development board. They usually have switches, LEDs, etc plus 0.1" headers that you can use to connect to your specific circuits. Xilinx's Spartan 3 board is around $100 (or is it $150?) 3) Use a toaster over plus solder paste to solder SMD chips. HTH -Dave PollumArticle: 101463
> There is no user interface byeound one single LED. Maybe use the LED for some kind of user /input/?! I recently came across this article (from 2003), http://www.merl.com/publications/TR2003-035/ Kolja -- mr. kolja waschk - haubach-39 - 22765 hh - germany fon +49 40 889130-34 - fax -35 - http://www.ixo.deArticle: 101464
> I recently came across this article (from 2003) ...and found again where: http://www.hackaday.com/entry/1234000873073550/ (has some more links regarding using LEDs as sensors)Article: 101465
Dave Pollum wrote: > tuxfriend; > If you are concerned about soldering big chips with lots of tiny pins, > there are several things you can try: > 1) Some companies (Digilent comes to mind) have CPLDs or even FPGAs > mounted on a board that plugs into a 40-pin 0.6" wide IC socket. > 2) You can buy a CPLD or a FPGA development board. They usually have > switches, LEDs, etc plus 0.1" headers that you can use to connect to > your specific circuits. Xilinx's Spartan 3 board is around $100 (or is > it $150?) > 3) Use a toaster over plus solder paste to solder SMD chips. > HTH > -Dave Pollum Hello Dave, 2) is a good choise ($149) 3) 0,8mm is big enough for hand soldering ...but the main problem still exist. I can't belive that there is no more software for my XC3190A in the whole world. Thank you for your answer!Article: 101466
Jeff Brower wrote: > Eli- > > >>If you remove the line comments in front of the input and >>output declarations, the program synthsizes as expected > > > This happens in 7.1 also. A couple of years ago a Xilinx FAE told us > "do not use C++ style comments for any reason except synthesis > attributes" and we have followed that on blind faith. > > -Jeff > So, if I cant use // or /* */, what can I use for commenting? -EliArticle: 101467
> Do you have a DOS 3.3 machine to run it on? No problem! > A DOS 3.3 SDK? What is a DOS SDK? Do you mean Win3.1 SDK? I have a MS C 1.0 for Win license. > I forget if the XC3190A tools were Windows friendly but they *were* all > command-line friendly but still not at all a pretty interface. I'm not > sure you'd be happy with the tool performance if you could get those 1990 > era tools running unless you used the NeoCad tools to up the performance > of the > Xilinx software before they bought out NeoCad. You can't get NeoCad keys > anymore as far as I know. The problem is the Place&Route Tool and the bitstream generation. There is no need for a graphical interface. Do you know the book software or have an idea where I can get the P&R Soft?Article: 101468
"tuxfriend" <tuxfriend@arcor.de> wrote in message news:445663d9$0$4496$9b4e6d93@newsread2.arcor-online.net... > > Hello Dave, > 2) is a good choise ($149) > 3) 0,8mm is big enough for hand soldering > ...but the main problem still exist. > I can't belive that there is no more software for my XC3190A in the whole > world. > > Thank you for your answer! Do you have a DOS 3.3 machine to run it on? A DOS 3.3 SDK? I forget if the XC3190A tools were Windows friendly but they *were* all command-line friendly but still not at all a pretty interface. I'm not sure you'd be happy with the tool performance if you could get those 1990 era tools running unless you used the NeoCad tools to up the performance of the Xilinx software before they bought out NeoCad. You can't get NeoCad keys anymore as far as I know.Article: 101469
Jon Beniston wrote: >>They do not mean they run at 2GHz _and_ @ 0.2V :) >> >>"operated correctly" is their carefull wording. >>To me, correct (expected) operation at 0.2V is data retention. >> >>Target Vcc sounds ~1.2V : >>"is capable of running common FPGA performance benchmark designs at up >>to 1.93 GHZ at 1.2V" >> >>-- not sure what they were testing at 3.9V, - might have meant the >>IO buffers, and probably not the Core Vcc! >> > > >>From eetimes.com: > > John Lofton Holt: We got 1.93-GHz equivalent performance at 21 degrees > Celsius and 1.2-volts Vdd. At minus 196 degrees Celsius we got 2.3-GHz > performance at 1.2-V. Performance does taper off with increased > temperature. At 130 degrees Celsius we got 1.4-GHz at 1.0-V. But even > more important for us is voltage scaling. These all sound plausible. > As you linearly decrease the voltage you get a cubic improvement in > power consumption. So at 0.6-V we got 400-MHz performance on our > prototype but with an 87 percent reduction in power consumption. That's quite a good parameter point. ( even if the numbers do not track his 'cubic' claim ) > > eetimes: But surely CMOS doesn't work at 0.2-V and at 3.9-V a device > in a 90-nm process would burn up? > > John Lofton Holt: We've told you what we found. The chip did work > down to 0.2-V Be nice to know what 'work' means at 0.2V. I can't see that being anything other than data retention ? > and up to 3.9-V, but we did not test the chip for an > extended period. Also it's true that the leakage current had > increased by 50 percent when we brought the voltage back down from > 3.9-V. :) - It might have been prudent to keep that number 'in the lab', as clearly it was a stress point. Hopefully, it was the last test, or done on a 'spare' sample! > It's also true that foundry SRAM cells would not work below > about 0.8-V, but we've used proprietary SRAM cells. > > Cheers, > Jon thanks - jgArticle: 101470
Eli Hughes wrote: > Eli Hughes wrote: > >> The following code was shown to me by a collegue. All of the logic >> has been removed for clarity (and to protect IP). The Synthsizer >> reports 3 errors that some of the signals are not declared as input, >> inout or output. If you remove the line comments in front of the >> input and output declarations, the program synthsizes as expected. Wow, that's a pretty impressive impact/laziness ratio :: (User Impact x N users) / (Suppliers Time to Fix) How long _should_ it take to fix this ? -jg >> >> >> 8.1 YUCK!! >> >> >> >> -Eli > > > > Oops, here is the verilog code: > > module Main(SysReset,Zero,ClkInput, UZBEERX, ROW_Q1, COL_Q1, ROW_Q2 , > COL_Q2 , ROW_Q3 , COL_Q3 , ROW_Q4,COL_Q4,PSUP,PSUPo); > > > > /*inputs outputs registers wires*/ > input SysReset; > output Zero; > input ClkInput; > input UZBEERX; > output [12:0] ROW_Q1; // row select quadrant1 > output [12:0] COL_Q1; // column select quadrant1 > output [12:0] ROW_Q2; // row select quadrant2 > output [12:0] COL_Q2; // column select quadrant2 > output [12:0] ROW_Q3; // row select quadrant3 > output [12:0] COL_Q3; // column select quadrant3 > output [12:0] ROW_Q4; // row select quadrant4 > output [12:0] COL_Q4; // column select quadrant4 > output [3:0] PSUP; > output [3:0] PSUPo; > > > endmoduleArticle: 101471
> > As you linearly decrease the voltage you get a cubic improvement in > > power consumption. So at 0.6-V we got 400-MHz performance on our > > prototype but with an 87 percent reduction in power consumption. > In my book it is f x C x Vsquared. Where does the third power come from? Physics is physics, even when it runs asynchronously. Peter AlfkeArticle: 101472
FWIW the following code seems to work with ise 8.1.03:
module test (test_in1, test_in2, test_out1, test_out2);
input test_in1; // comment here
input test_in2; /* comment here */
output /* comment here */ test_out1;
output test_out2; /* comment
here
and
here
*/
assign test_out1 = test_in1;
assign test_out2 = test_in2;
endmodule // test
HTH,
Jim
http://home.comcast.net/~jimwu88/tools
Article: 101473tuxfriend wrote: > Josh Rosen wrote: > ... >> If it's on 3 1/2" floppies then you'll be able to >> read them because 3 1/2" drives are still available, your system might >> even have on if it's more than 2 years old. If the software is on a CDROM >> that's a sure indicator that it won't have 3000 series support. By the >> time that CDROMs became the standard means of distributing software >> support for the 3000 series had already been dropped. > > Oh, I think that will be the problem. I have a moderately old copy of Foundation 2.1 around on CD. It is from circa 2000, and claims to support the XC3100A family of devices. I think Xilinx has the old versions of their software available on their website somewhere. But I would agree with others who are trying to talk you out of bothering with these old devices.Article: 101474
I'm guessing the third is due to the reduction in frequency. Cheers, Jon
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