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"Kolja Sulimma" <news@sulimma.de> wrote in message news:4459d02d$0$4501$9b4e6d93@newsread2.arcor-online.net... > > IMHO it is embarrassing that a 2006 compiler cannot synthesize > > if rising_edge(clk) and enable='1' then... > Hi Kolja, Just out of curiosity, which compiler are you talking about? XST? Synplify seems fine, I do get a "Feedback mux created for signal xxxxx" warning, but the output doesn't have this mux. Thanks. Cheers, Syms.Article: 101651
I see that this thread creates lots of interest, but it has gone a little off topic. I will try to describe the problem I face in more details. The grup I work in is composed of several hardware (FPGA) engineers. Some of them use VHDL, and some use graphic methods. Currently, no source control of any kind is used, making tracking design sources and sharing them among the group very difficult. In order to solve some of these problems, I want to install and start use Subversion as a source control system. What I look for is a way to automatically include in the source control components that are normally added in the graphic editor or using the MegaWizard interface. Another, related problem is taking an existing Quartus project, and putting it under source control without losing files and without including files that are not necessary. The best way to accomplish both tasks, in my opinion, is writing a script that wolud go through the project hierarchy (after synthesis), pick up all the source files used and add them to the source control system (if theyr'e not already there). Subroto Datta suggested to use the "Source Files Read" section of the analysis report, which seem to be a good direction, but I need to know if there is a way to get this information*programatically*, rather than text processing the report. This report also seem to lack memory initialization files (maybe more kind of files I don't know of?). Another type of problem is the SOPC builder. The SOPC builder takes the system specification from PTF files (as KJ mentioned) and copies HDL files from the relevant library into the project directory. These copied files are not strictly sources, but rather intermediate products, and as such they should not be under the soruce control (they should, in fact, but they should be controlled by the one that wrote the component, not the one using them). After SOPC builder has finished its run, there is no way (to my understanding) to distinguish between true source files and those who were copied. They will both show up the same in the said report. A possible solution might be to instruct SOPC builder to copy its files to a directory other than the project root (I think it would be much easier to manage also), but I don't know how to do that. Thanks for everyone who has replied (and will) AvishayArticle: 101652
What kind of cpu resources does fpga "compilation" (Analyse, Synthesis, etc..) use on a cpu..? Integer/Branch/Bitshifting..? Floating point..? Will a pipeline cpu greatly improve speed..?Article: 101653
Symon schrieb: > "Kolja Sulimma" <news@sulimma.de> wrote in message > news:4459d02d$0$4501$9b4e6d93@newsread2.arcor-online.net... > >>IMHO it is embarrassing that a 2006 compiler cannot synthesize >> >>if rising_edge(clk) and enable='1' then... >> > > Hi Kolja, > Just out of curiosity, which compiler are you talking about? XST? Synplify > seems fine, I do get a "Feedback mux created for signal xxxxx" warning, but > the output doesn't have this mux. Thanks. > Cheers, Syms. I never used synplify, but it is plausible that it has a more modern view on what should be synthesizable and what should not, as the company was started at a time where people allready complained about such limitations. I discovered limitations like these in the last couple of years in Synopsys FPGA Compiler as well as Design Compiler, in Magma DAs Blast RTL and in XST. IMHO the worst limitation was a version ov Blast RTL that restricted generics to be of type integer. My code used to turn on feature with boolean values. No it uses integers... Kolja SulimmaArticle: 101654
Hi all, I'm developping an application on PowerPC to programm a Lattice EPLD. For that, I'm using ispVM Lattice player. When I programm the CPLD which is already programmed by JTAG connector, all is running. But when I programm a new CPLD which has never been programmed, the programmation failed and I have message from VME player to tell that TDO signal is wrong. The CPLD is in a JTAG chain with a FPGA. Have you got an idea about my problem ??? Many thanks in advance.Article: 101655
ADEPT shows unbonded IOBs. You can copy and paste them to an editor or export the list to Excel spreadsheet. It is availabe at http://home.comcast.net/~jimwu88/tools/adept/ HTH, JimArticle: 101656
Hi All, I've started using ISE8.1. SP3 has been available awhile, and the angry posts about 8.1 on this newsgroup dropped enough for me to upgrade. Anyway, my new angry post is this. I think the new version of Chipscope, 8.1.03i seems to have worse timing than previous versions. When I have a wide capture buffer, say 80 ish, the thing won't place and route at 150MHz. This used to work fine. Also, all my own designs that were close to the timing limit before upgrading have similar if not identical timing, so it's not due to a timing file upgrade. I wonder if some bright spark in the Chipscope project has reduced the amount of pipelining to save on the amount of real estate? If so, they've buggered the performance when the thing has a wide capture bus. Anyone else had similar experiences? Cheers, Syms p.s. I'm using V2PRO parts.Article: 101657
"Symon" <symon_brewer@hotmail.com> wrote in message news:445a0b01$0$15786$14726298@news.sunsite.dk... > Anyway, my new angry post is this. I think the new version of Chipscope, > 8.1.03i seems to have worse timing than previous versions. When I have a > wide capture buffer, say 80 ish, the thing won't place and route at > 150MHz. Update: It seems that Chipscope has gone back to changing the names of nets so that the UCF contraints don't work. More soon....Article: 101658
You must distinguish between the relatively long time that th DLL takes to achieve lock (many microseconds) and the very small phase error on the outputs (picoseconds, which is million times shorter) once the DLL is locked So, the different DLL will most likely achieve lock at different times, but once in lock, they will each perform to data sheet specs, which means picoseconds of difference on the outputs Another matter is that frequency division can obviously generate out-of-step outputs between different chips. Peter Alfke, XilinxArticle: 101659
"Symon" <symon_brewer@hotmail.com> wrote in message news:445a1332$0$15789$14726298@news.sunsite.dk... > "Symon" <symon_brewer@hotmail.com> wrote in message > news:445a0b01$0$15786$14726298@news.sunsite.dk... >> Anyway, my new angry post is this. I think the new version of Chipscope, >> 8.1.03i seems to have worse timing than previous versions. When I have a >> wide capture buffer, say 80 ish, the thing won't place and route at >> 150MHz. > Update: It seems that Chipscope has gone back to changing the names of > nets so that the UCF contraints don't work. > > More soon.... Yeah, my UCF was expecting a net called fast_enable. Sadly it failed to notice Chipscope had changed the name to "ila0_trig0<56>". Grrrrr... Syms.Article: 101660
Antti (Antti.Lukats@xilant.com) wrote: : Hi Tommy, : actually the board is visible in the website header at : http://www.xilant.com Antti, One thing springs immediatly to mind for this - JTAG. More specifically JTAG hardware that can manage Xilinx FPGAs and platform flashes, and has programming software for Windows *and* Mac OS X... The Xilinx tools should run at native speeds under Parallels Workstation on the new MacBook Pros, and add a JTAG solution... Cheers, ChrisArticle: 101661
Ron, We already sponsor this sort of research at many universities and schools. If you want to go play, there are many excellent programs in graduate education on the subject. I am aware of a very active group at UCLA. Austin Ron wrote: > Mike Harrison wrote: > >> Maybe you should talk to XIlinx about lending you a devboard for one >> of their high-end chips, in >> return for some good publicity when you crack it..? > > > Exactly what I was thinking Mike. :-) What's frustrating is that > although I could see spending a thousand or two thousand dollars for a > development board, I simply cannot justify spending $2,495 of my > retirement nest egg for the software tools alone. > > I wonder if Peter Alfke of Xilinx would care to comment on the > possibility of my acquiring a loaner devboard and development s/w? I'm > located in the San Gabriel Valley just North-West of Los Angeles. The > email address I'm using (News5@spamex.com) is valid by the way, at least > until it starts getting too much spam, and then I'll change it to News6, > News7, etc. > > Some of the large computer software makers (MatLab, MapleSoft, etc) > offer non-profit discounts for educational and personal non-commercial > use. It would be wonderful if Xilinx (my favorite) or one of the other > FPGA vendors would offer some sort of low cost alternative to me and > those in my situation who would love to use your high end FPGAs, but > cannot afford the cost of the s/w development tools. > > Thanks, > > RonArticle: 101662
Thanks for the help everyone, I finally fixed the problem. It was an issue with the the asynchronous load line. shawnn@gmail.com wrote: > We are using VHDL on a new design with a Lattice 4256V and are running > into problems with our shift registers. We're using ispLEVER 5.1 trial > along with Synplicity synthesis. Here's our generic 11-bit shift > register with async. parallel load: > > -- > -- 11 bit shifter for data serialization > -- > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.STD_LOGIC_arith.all; > use IEEE.STD_LOGIC_unsigned.all; > > entity shifter11 is > port( > clk:in std_logic; > rst:in std_logic; > data_in:in std_logic_vector(10 downto 0); > shift_load_select:in std_logic; > shift_in:in std_logic; > data_out:out std_logic); > end shifter11; > > architecture bhv of shifter11 is > signal data_latched: std_logic_vector(10 downto 0); > begin > process(clk,rst,data_in,shift_load_select) > begin > if(rst='0') then > data_latched <= "11111111111"; > elsif(shift_load_select = '1') then > data_latched <= data_in; > elsif(clk'event and clk='1') then > data_latched <= shift_in & data_latched(10 downto 1); > end if; > end process; > data_out <= data_latched(0); > end bhv; > > > We have isolated the CPLD completely with nothing but a clock pin + > reset as external input. With hard-coded input to the shift register > and another test entity that does nothing but sniff the ouput and > verify its correctness, we are occasionally running into problems. > After many thousands of shifts + outputs over 20-60 seconds, there will > be one or more bits flipped in the shift register output. 99.999% of > the time the output is correct, we just can't figure out why this thing > is failing. > > The issue seems to only occur when we place multiple shift registers in > our design working in parallel, a single shift register alone will work > error-free. To me this seems to indicate a tool issue when utilizing > resources close to the limits of the chip. > > Another possibility is a hardware problem, however we have double and > triple checked all ground / VCC pins and reduced the external inputs to > the bare minimum. > > I started going through the generated postfit equations, however I > started to get a headache after about the 100th flip flop. > > Any suggestions on how to fix this?Article: 101663
I just spend days debugging an issue and though I fixed the problem, I
don't see why it was an issue in the first place. Here is my shift
register that I implemented on a Lattice LC4256V:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
entity shifter11 is
port(
clk:in std_logic;
rst:in std_logic;
data_in:in std_logic_vector(10 downto 0);
shift_load_select:in std_logic;
shift_in:in std_logic;
data_out:out std_logic);
end shifter11;
architecture bhv of shifter11 is
signal data_latched: std_logic_vector(10 downto 0);
begin
process(clk,rst)
begin
if(rst='0') then
data_latched <= "11111111111";
elsif(clk'event and clk='1') then
if(shift_load_select='0') then
data_latched <= shift_in & data_latched(10
downto 1);
else
data_latched <= data_in;
end if;
end if;
end process;
data_out <= data_latched(0);
end bhv;
It's just an 11 bit shift register with synchronous parallel load. The
load and data signals were generated asynchronously by an external
device on a different clock domain, with the data being valid many
clock cycles before load going high. 99.999% of the time everything
worked, but it was ocassionally loading garbage data that made no
sense. The fix was to clock the load signal on the falling edge of the
CPLD clock.
I just don't understand why having a load input that is generated
asynchronously can cause a problem. The shift register still only
checked the load signal on the rising edge of its clock so I don't see
any error conditions.
What am I missing here?
Article: 101664pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > What kind of cpu resources does fpga "compilation" (Analyse, Synthesis, etc..) > use on a cpu..? I always assumed it was sorting and searching types of operations. But I have no references to back that up. > Integer/Branch/Bitshifting..? > Floating point..? > Will a pipeline cpu greatly improve speed..? Perhaps faster memory or a larger cache would help. Aren't all processors pipelined nowadays? Alan NishiokaArticle: 101665
Austin Lesea wrote: > Ron, > > We already sponsor this sort of research at many universities and schools. > > If you want to go play, there are many excellent programs in graduate > education on the subject. > > I am aware of a very active group at UCLA. > > Austin uh... would you mind giving me a pointer to these guys ? lukaszArticle: 101666
Ok I did some reading and answered my own question. This is a really great article -- http://www.eetimes.com/editorial/2000/design0003.htmlArticle: 101667
Alan Nishioka <alan@nishioka.com> wrote: >pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: >> What kind of cpu resources does fpga "compilation" (Analyse, Synthesis, etc..) >> use on a cpu..? >I always assumed it was sorting and searching types of operations. >But I have no references to back that up. Sounds resonable. The tough task must be to figure out optimal placement of "gates" and how to route switches. And when to relocate and let signals through chained switches (kind of like leased lines in telecomm). Maybe the task is very much similar to BGP (Border Gate Protocoll) in terms of algorithms. >> Integer/Branch/Bitshifting..? >> Floating point..? >> Will a pipeline cpu greatly improve speed..? >Perhaps faster memory or a larger cache would help. >Aren't all processors pipelined nowadays? Proberbly. But if the app is benefitting a lot from pipelineing. Then it might pay to use a cpu with extra long pipeline.Article: 101668
Jan Decaluwe wrote:
> I have added a page about a Cordic-based Sine Computer to
> the MyHDL CookBook:
>
> http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp
Wow. A non-trivial example that works.
Beautiful generated code.
(Ignore the synthesis warnings, I think Jan has it right.)
You may be on to something.
Here's how Quartus sees it:
http://home.comcast.net/~mike_treseler/sinecomputer.pdf
_______________________
Top-level Entity Name : SineComputer
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Total ALUTs : 276 / 12,480 ( 2 % )
Total registers : 107
[vs. 131 in the example -- apples to oranges ]
Actual Time : 141.42 MHz ( period = 7.071 ns )
[ vs 87.385MHz in the example -- apples to oranges ]
-- Mike Treseler
Article: 101669hi, there, I want to set one of I/O pin as 3 state, how can I do this in Xilinx FPGA using Verilog? thanksArticle: 101670
Dear FPGA enthusiast, The offer has just ramped up to another level, but only for 48 hours. We are serious about moving these boards & we are willing to give you even more (bonuses worth AU$151.00 and AU$325.00). Plus find out what this has to do with a home-built, computer controlled, carbon dioxide laser cutter. Read about it at http://www.burched.biz Tony Burch PS. You may need to press the refresh button on your web browser if you have looked at the site recently.Article: 101671
Thank you! Whenever you deal with asynchronous clock domains you really have to be paranoid. Sooner or later, any weird phase relationship between these clocks will occur, and your system must be able to cope with it. Metastability can theoretically last forever, but in practice it very rarely lasts more than 3 ns. Good luck! Peter AlfkeArticle: 101672
Hello, I am new to FPGAs and was wondering, how do fpga store the bitstream? I mean, with CPLD, I don't need any special memory chips to program them and they retain their programming, but for FPGA, I see that they seem to need some flash or prom to store the bitstream, which then loads into the FPGa. Is this the case? If so, what type of memory is used, and how do I use Xilinx webpack to program it? Thanks, JamesArticle: 101673
Jim_L_Williams@hotmail.com wrote: >Hello, > >I am new to FPGAs and was wondering, how do fpga store the bitstream? >I >mean, with CPLD, I don't need any special memory chips to program them >and >they retain their programming, but for FPGA, I see that they seem to >need >some flash or prom to store the bitstream, which then loads into the >FPGa. >Is this the case? If so, what type of memory is used, and how do I use > >Xilinx webpack to program it? > > Many mid-sized Xilinx FPGAs use serial EPROMs, most can also handle a parallel EPROM if you provide an address counter. I've been working with 5 V Spartan devices, and use Xilinx's own 17128 through 17256 and 17S20 and 17S30 serial EPROMs, which use a direct-wired connection to the FPGA. They have some 3.3 V versions that are used with the newer FPGAs that have a 3.3 V interface. This is by far the simplest setup for mid-size FPGAs such as the Spartan series. You can't program these directly with the WebPack software. I use a Xeltek universal device programmer, and it is very good, and pretty cost effective. Xilinx does have a link on their web site to a device programmer that only supports their own PROM products, but the Xeltek is only just a little more expensive and so much more flexible. JonArticle: 101674
Kolja Sulimma wrote:
>>> IMHO it is embarrassing that a 2006 compiler cannot synthesize
>>> if rising_edge(clk) and enable='1' then...
I don't know of a recent release that causes such embarrassment.
The example below works fine on Quartus.
The downside to this template is that it clock enables
everything in the process -- too restrictive for me.
-- Mike Treseler
___________________________
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clk_en is
generic (vec_len : positive := 8);
port (
clk : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
q : out std_logic_vector(vec_len-1 downto 0)
);
end entity clk_en;
architecture synth of clk_en is
begin
clk_en : process(reset, clk) is
subtype vec_t is unsigned(vec_len-1 downto 0);
constant vec_init : vec_t := "10110011";
variable reg_v : vec_t;
begin -- process template
if reset = '1' then
init_regs : reg_v := vec_init;
elsif rising_edge(clk) and enable = '1' then --<
update_regs : reg_v := rotate_left(reg_v, 1);
end if;
update_ports : q <= std_logic_vector(reg_v);
end process clk_en;
end architecture synth;
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