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Dave schrieb: >>If you can live with a few ns jitter you can digitally synthesize the >>clocks from an additional fast clock. > > > Hi Kolja, > > Do you mean take a fast clock and clock some counters to generate > enables or something more fancy? Just like that. You measure the frequency with a counter and use the measured value to generate new clocks. Also: Do you really need a 2x, 4x, 8x clock? Or is it sufficient, to have 2, 4 and 8 clock edges within each cycle of the original clock? As your circuitry is able to run at 240MHz anyway (8x30Mhz) you can have a 240MHz circuit that waits for a rising edge of the input clock and then generates eight pulses set 4ns apart independent of the input frequency. You can only use this if the timing of the results is not important. KoljaArticle: 101576
Hi, does anybody have a list of the unbonded iob's on the lx25? Thanks, AlastairArticle: 101577
>I want to open an ISE 8.1 project in ISE 7.1, but it seems impossible. > and there's even no compatibility property in the save option. > My project has verilog, vhdl, schematic and coregen files. Rainier, Can I ask why you want to do this? I have a project I have to update for a client, I was going to use 8.1, but after all the problems people have posted here I think I might be better sticking to 7.1? Nial.Article: 101578
Dave wrote: > > You have not defined what 'clock rate variations' will be. > > A regular locked multiple is only possible with a regular > > referance IP. Wobble the IPs and the DCMs will chase their tail > > trying to follow.... > > So, you will need to nail down the dF and Slews (dF/dT) and also when > > it does, and does not, have to follow with 8x outputs - and then try > > some designs. > > Hi Jim, > > The input clock may be as low as 200 kHz and as high as 20-30MHz > perhaps. The frequency will be fixed at a certain frequency while the > system runs however (i.e. it is not going to swing around in that > range!). > > The issue is that 2x, 4x and 8x are required. The minimum output of > the DCM when using CLKFX is 24MHz so 12MHz is the minimum input but > downto 200kHz as input is required. Also, 1MHz is min input of DCM and > lower freqs than this may be used. So, DCMs cannot be used. DCM's can be used above 1 MHz with CLKFX only (no DLL outputs). You just need to increase the multiply factor on the first DCM, i.e. start with 32X and divide down to get 8X 4X 2X. Below 1 MHz you'd probably do best to use a constant high-speed clock and digitally generate the clock outputs if you can stand the jitter (1 cycle of the high-speed clock). Its unlikely you'll find a single method to multiply the clock over the entire range of the circuit. Having a constant high-speed clock allows you to determine the input frequency and select the best method. > > Many thanks for your help, > > DaveArticle: 101579
Hi, I use ISE8.1 (webpack) in Verilog. I try to use inout port. Sample code: module ....(... inout wire[7:0] data, ...); reg [7:0] buff; reg hiZ; assign data=hiZ ? 8'bzzzz_zzzz:buff; .... endmodule When I use xst to synthesis, and when I look at RTL logic , I cannot find tristate buffer in the circuit. And when I simulate with ModelSIM XE 6.0d (eval version), I got xxxx instead of zzzz. Thank you, SamArticle: 101580
Hi Nial, dont be so afraid of 8.1 - unless you already know why you should stick with 7.1 or there are constraints from your client to use 7.1 I would say the you should be fairly safe using 8.1 for the project. As 8.x is the latest major version so it is the only one that gets update-patches the issues 7.x had will never get fixed. but of course make FULL PROJECT ZIP file and move it to other computer, CDrom physical location BEFORE updating a client project from 7 to 8 ! just in case, all brakes in 8.x you can revert using the old one AnttiArticle: 101581
thanks to Antti. Nial, I want to do this becasue the project I'm dealing with is a team work. My partner use ISE8.1 while I'm using 7.1 coz it runs faster in my computer. you know, sometimes we have to make a decision between great features and running speed.Article: 101582
You can't have internal tristates, unless you're using old Virtex technology They'll be replaced by equivalent circuits. (like MUXES) (if I recall correctly) Ben "samtee" <samxx@yahoo.com> wrote in message news:4458b047$0$27288$c3e8da3@news.astraweb.com... > Hi, > I use ISE8.1 (webpack) in Verilog. I try to use inout port. Sample code: > module ....(... inout wire[7:0] data, ...); > reg [7:0] buff; > reg hiZ; > > assign data=hiZ ? 8'bzzzz_zzzz:buff; > .... > endmodule > > When I use xst to synthesis, and when I look at RTL logic , I cannot find > tristate buffer in the circuit. And when I simulate with ModelSIM XE 6.0d > (eval version), I got xxxx instead of zzzz. > > Thank you, > SamArticle: 101583
Hi, I have some trouble with the outputs of a Xilinx Virtex-II 1000 FPGA. The pins in question are conencted to a bi-directional data buffer, but a logic analyser tells me that the values are not changing every time they are supposed to. The logic in the FPGA works as expected most of the time, but occasionally screws up. Has anyone expeirenced this before, or shed light on the situation? I've tried two different FPGA chips with the same result, my VHDL is not at fault... Many thanks for your help, Robin University of NewcastleArticle: 101584
Antti Lukats <antti@openchip.org> wrote: >Hi all >I am looking for ideas for: "FPGA Single LED Demos", The requirements for >the demo Application are following: >* Display visible 'sign of live' or 'self-test passed' message >* Impemented in FPGA Vendor neutral HDL >* <= 3000 LUT >* <= 4KB of Block RAM >* uncalibrated (+-50%) high frequency oscillator >* 1 user LED for display I had another idea.. output delta-sigma modulated speech (or sound). Verify it with a simple speaker-ldr-battery device. I know C64 could use very basic speech samples with it's taperecorder. So it should be doable.Article: 101585
What are you writing out? And do you delay the write data?Article: 101586
Falk Salewski wrote: > I am doing some research on the reliability of microcontrollers software in > comparison to hardware description languages for PLDs (CPLD/FPGA). > > Another interesting point is whether there are general benefits of one > hardware regarding reliability, e.g. in an automotive environment. > > > > I read about certification problems if a SRAM based FPGA is programmed every > system start and that Flash or Fuse based systems are preferable. I also > read that CPLDs (Flash) in general are more robust than FPGAs. > > Can you confirm/confute this? What are the allowed failure modes ? All of them ? That includes alpha particles, fast protons, thermal cycles, vibrations, supply and signal issues, electric and magnetic fields, the lot. Plus how failure prof is the design. How can it handle unexpected values. While in some points 90nm technology is more sensitive, it is not that an acre of 2N3055 doing the same would be more reliable. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 101587
> I've tried two different FPGA chips with the same result, my VHDL is > not at fault... Robin, I'm curious, how do you know your VHDL is not at fault? As two separate devices display the same behavior it appears likely the cause is your code or the test setup. Have you ChipScope-ed your design to ensure that the internal signals going to those IOBs are indeed driven at the correct times? StephenArticle: 101588
A speaker can be directly plugged in (there is small extension slot) and it is possibe to send data to the FPGA with up to max 6MByte/s (4 bit SD mode when card clock is 12MHz) for speach way more than required :) of course the audio modulated LED emitted light could be used for audio capture using some photosensor as well AnttiArticle: 101589
hi Xilinx, do you thing i have a chance to buy an ML405 board before i retire ? i saw the first announcement for this board in XCELL first quarter 05. We are in May 06. Any problem with virtex4 FX ?Article: 101590
"David" <david.quinones@imagsa.com> wrote in message news:ee98d76.4@webx.sUN8CHnE... > Hi Marco > > What about the MPMC 2 component? Do you know if the GSRD has been updated? > > Regards Hi David, I'm still waiting that GSRD team will port lwip to plb_temac. It will be available into EDK 8.2 release (not 8.1.2). MarcoArticle: 101591
no problems with V4FX ! (when you are not using them) so whats wrong with early retirenment? Antti PS I have also identified ML405 as the next best thing to buy .. a long time ago and have given up looking for it also a long time ago yes, - I know the problems with V4FX are now all solved as Xilinx can confirm, but it still takes time til the V4Fx based things come really really availableArticle: 101592
The traditional debugging starts with a thermal test (hairdryer and cold spray), then change Vcc up and down, and then (if possible) change the main clock frequency up and down. That should give you a feel for possible timing marginality. If several chips behave the same bad way, the suspicion is on the VHDL side... Peter Alfke Peter Alfke, Xilinx ApplicationsArticle: 101593
Stephen, Thank you for your reply. I am "pretty sure" my VHDL is correct, because the FSMs in the design function correctly most of the time, and do not pre-empt the host computer on the other end of the parallel port I'm using, which the data buffer is connected to. It is as though the latch and/or the IO pin does not respond to a change in an internal signal. From what I can see on the logic analyser, this problem sometimes persists for a long time, or until the board is reset. Unfortunatly, I don't have access to ChipScope, so I cannot observe the internal signals. I am at a loss to explain this behaviour, and of course I am open to accepting that my VHDL is incorrect with some evidence. I am not familiar with the ins and outs of the Virtex-II (or any FPGA really) so there may be some small detail of which I am unaware... The exact problem I am having is that the output enable of the bi-directional buffer is not always set active when it should be. A FSM in the FPGA will then read what appears to be a non-driven input. I am happy that the test setup is OK, as the results I observe are consistent with the behaviour resulting from incorrect data on the data lines from the parallel port. Have you observed similar behaviour on IO pins before? Thanks, Robin University of NewcastleArticle: 101594
Hi Folks,
got interested to test it out, and well I have VERY preliminary results
- all
the test setup was done within 30 minutes, so it's just proof of
concept:
Test setup
1) Xilinx S3 FPGA (a GOP module from oho-elektronik)
2) IOPad oscillator (using 2 io pins, see at the end of posting)
3) green 0805 SMD LED
4) JTAG Frequence meter software and ip-core, one channel connected to
the IOPad oscillator (the frequence meter application is the same as at
gforge.openchip.org)
first I tried to put the LED between the 'diff' outputs of the iopad
oscillator, but that did not have good results, by placing the LED with
one terminal on X2 and other
one just unused (put pullup enable) FPGA pin I was able to see light
influence on the oscillator frequency. the oscillator did run at 35MHz,
light from window or then covered up with paper caused a frequence
change of 80KHz, well that isnt much but I guess my setup wasnt not the
best to get the 'sensor effect' out - still the frequence change was
cleary observable.
of course the current test setup is sensitive also to capacitance so
using your finger to cover up the LED will have more capacitive impact
then light dependant
changes. Anyway with proper bias and (series) resistor the light
dependancy of an normal LED should be very easy to measure with an FPGA
Antti
----------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xti_oco_io2pin is Port (
X1 : inout STD_LOGIC;
X2 : inout STD_LOGIC;
EN : in STD_LOGIC; -- fake always high signal
CLK : out STD_LOGIC
);
end xti_oco_io2pin;
architecture Behavioral of xti_oco_io2pin is
begin
X1 <= X2 when EN='1' else 'Z';
X2 <= not X1 when EN='1' else 'Z';
CLK <= X1;
end Behavioral;
Article: 101595Oh, and just to qualify what I said in the last post... I am able to see which state the FSM is in on the logic analyser, and when the FSM moves from a state in which it will change the value of the output pin into the next, the signal does not change. There is no conditional expression or anything that would prevent it from changing the signal... -------------- Peter, thank you for your suggestion. I'll see what I can do, but I too would expect incorrect VHDL. I am unable to find an error, however! --------------- If you would like some more information, I'll happily post it.Article: 101596
christophe ALEXANDRE wrote: > hi Xilinx, > > do you thing i have a chance to buy an ML405 > board before i retire ? > > i saw the first announcement for this board > in XCELL first quarter 05. > > We are in May 06. > > Any problem with virtex4 FX ? > The first volume production of the ML405 (XC4VFX20-FF672-10CES4) will be available for sale in late June 06. That's less then 2 months from now, so I hope that your nest egg is well funded. :-) All of the initial volume of the XC4VFX20 devices had been prioritized and allocated to customer sockets over the eval boards. Since we are using long lead time manufacturing to keep the costs and prices down it has been longer than expected to get these boards available for sale. We expect to do much better with the next generation. Ed McGettigan -- Xilinx Inc.Article: 101597
Antti wrote: > Hi Folks, > > got interested to test it out, and well I have VERY preliminary results > - all > the test setup was done within 30 minutes, so it's just proof of > concept: > > Test setup > > 1) Xilinx S3 FPGA (a GOP module from oho-elektronik) > 2) IOPad oscillator (using 2 io pins, see at the end of posting) > 3) green 0805 SMD LED > 4) JTAG Frequence meter software and ip-core, one channel connected to > the IOPad oscillator (the frequence meter application is the same as at > gforge.openchip.org) Eh, http://openchip.org: "All Intellectual property right hold by OpenChip have been transferred." It appear to have disappeared. TommyArticle: 101598
"Tommy Thorn" <foobar@nowhere.void> schrieb im Newsbeitrag news:4458DA52.6090803@nowhere.void... > Antti wrote: >> Hi Folks, >> >> got interested to test it out, and well I have VERY preliminary results >> - all >> the test setup was done within 30 minutes, so it's just proof of >> concept: >> >> Test setup >> >> 1) Xilinx S3 FPGA (a GOP module from oho-elektronik) >> 2) IOPad oscillator (using 2 io pins, see at the end of posting) >> 3) green 0805 SMD LED >> 4) JTAG Frequence meter software and ip-core, one channel connected to >> the IOPad oscillator (the frequence meter application is the same as at >> gforge.openchip.org) > > Eh, http://openchip.org: "All Intellectual property right hold by OpenChip > have been transferred." It appear to have disappeared. > > Tommy http://gforge.openchip.org/projects/fpgafreqmeter/ I was referring to that project - its not the latest version but also working one. So for the LED sensor test I created a custom toplevel with iopad oscillator and used the jtag -connected host application to measure the frequency. Any yes all rights to ip-cores and source code tagged as: Copyright XXXX OpenChip are now hold by Xilant Technologies Inc. same goes for ip from Silicon Studio and Case2000 As Xilant website is VERY much work in progress so there is nothing much visible there - yet. SORRY, I am busy working so updating the website is left behind But as example the FPGA Frequency meter IP core and host side software library is used in the Xilinx Spartan3E flash programming tool http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,8/ AnttiArticle: 101599
hi, using verilog how to write a module which has an inpput port for an array of 8 bit signals and how to write a test bench for it. thank you. CMOS
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Compare FPGA features and resources
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