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Do you get DQS from the DDR memory if you send READ commands to the memory ? Rgds Andr=E9Article: 98651
On Fri, 10 Mar 2006 13:35:14 -0800, Austin Lesea <austin@xilinx.com> wrote: >> 2 - If you commit to EasyPath, you can't change your design without >> paying the NRE again. I >Not true: you may change any LUT contents that you already are using, >and you may change any IO standard on any pin you are already using. Point taken. On the other hand, though, how much useful fixing can you do by changing LUT contents? >> 3 - The RapidChip NRE, for a device with about the same capacity as a >> very large Virtex-4, came in at about $100K - $150K, with much smaller >> MOQs. And this is a *small* device. >RapidChip? Oh those guys that just left the business? Oh well. I could >offer you gasoline at 8 cents a gallon, and I am sure I would have a >long line at my station... You have missed my point, which is that your perception of NREs is incorrect (and, by implication, that yours is out of line). LSI have not, AFAIK, withdrawn RapidChip because its NRE was too low. >> 5 - As I said in my other post in this thread, there is no comparison >> between EasyPath and even a 'structured' ASIC when it comes to >> capacity, performance, and power consumption. >Ohe really? I think one can comapre them. Some areas (like leakage) the >ASIC will win. Leakage is irrelevant to me. On my current device, the structured ASIC wins hands-down on capacity, performance, power consumption, and unit cost, as I said. Your implication that my client is incapable of trading off these factors against NRE, delivery schedules, and risk is surprising. That's what we all do in this business, every day. You have your sweet point; the ASIC vendors have theirs. Don't knock it. >Some areas (like 10 Gb/s MGTs and a PPC, and a TEMAC) >the EasyPath will win, as these IPs are not even available all together >in 90nm! How many ASIC vendors have you checked for this stuff? And did you repeat the comparison for other processors? >> 7 - I've seen (in several places) the claim that EasyPath devices are >> cheap because they require less testing. I don't believe it. >Well, I can't convince you without desrcibing why. And in describing >why, I will educate you. And I have no incentive to do that. You may >look up the patent if you wish. Ok, so I'll educate you instead. Xilinx runs at gross margins in the range of 62 - 66%. What that means is that, of every $ I pay, about 35% goes to the fab, and 65% goes to Xilinx. The test is included in that 35%. How much does silicon test cost? Real figures are hard to come by, but a figure of about 10% of silicon cost is generally used. If we're generous, and allow you 20%, that means that only 0.2 x 0.35 - ie. 7c - of every customer dollar goes on test. Of course, you still have to test EasyPath. Let's say that you save 50% of test. This means that the maximum discount that you can offer for a half-test scenario is 3.5%. So where do your claimed figures of 30% - 80% savings come from? The numbers don't add up. You could try to claim that you offer EasyPath only on your more profitable lines, or that you cut gross margins for EasyPath products, but I don't buy it. So, EasyPath devices are *not* cheap because they require less testing; that much is obvious. In fact, there are two ways to look at this: 1 - If the devices actually *have* failed initial testing, and there is a widespread view that they have, then you can offer a large discount because anything is better than nothing; 2 - They're not cheap in the first place, because of the NRE costs. However, we'd need some real numbers from you to decide if this is true or not. >Definitive statement: testing a product for one use saves an incredible >amount of money. Look at ASICs.... No, it doesn't. If the silicon cost you *nothing*, then the biggest discount you could offer would be 35% before eating into your gross margins. And I can't believe that you do that, or that the silicon costs you nothing. Oh, and the unit cost advantage of ASICs has nothing to do with reduced testing. >Oh, I don't know, sounds like you learned something today? And, you and >I agreed on something. Not a bad result for a thread. It's been some years since I was a regular here. However, I do remember that the only Xilinx employee on c.a.f at that time was always courteous and well-informed, and didn't indulge in marketing. Evan -- Riverside emlat riverside-machinesdotcodotukArticle: 98652
There are three sets of holes for accessing signal I/O pins on the altera fpga board ...they are flex_expan_A,B and C on the Altera FPGA board. I don't understand the table that shows all the hole number and the signal/pin connection in flex_expan_A, can anyone explain about that? Thank you very much!! LauraArticle: 98653
On Fri, 10 Mar 2006 20:52:16 GMT, "John_H" <johnhandwork@mail.com> wrote: >> 4 - EasyPath is not 'just the same' as the FPGA you were buying >> before. When I last looked, it was a device that had failed test. >At a structured ASIC presentation, I railed on the guy that said that Xilinx >was selling bad parts. It's been underscored here before that the parts are >*not* rejects from the main testing that get shoved over to the easypath >line in the same sense as harddrives with bad sectors that didn't need >"those" sectors. There's certainly a general impression that the parts have failed test, whatever has been said on c.a.f. I'm pretty sure that I read this in Xilinx literature a couple of years ago, but I can't find it now. I may be wrong. If this is actually the case with Xilinx, then it wouldn't be unusual (or even "bad"). It used to be fairly common to buy memory devices which had failed test in only a part of the die, and I've done this myself. No-one has a problem with this; but, of course, supply will disappear as yields go up. And I didn't have to pay NREs for them. The other thing you have to look at is the economics. If these are good dies, then why are Xilinx selling them cheap? Have a look at my gross margin argument in my reply to Austin's post. Evan -- Riverside emlat riverside-machinesdotcodotukArticle: 98654
I have made a new release of the PacoBlaze module [http://bleyer.org/pacoblaze] considering the bug reports and suggestions I have been receiving. The configuration macros were cleaned and the stack implementation and PC control logic were revised. I also started adding debug signals and a bit of documentation. I think the current result is pretty neat. I have been playing adding a 8x8 MUL instruction that uses a straightforward even/odd model for the register file, plus one multiplier block. With 16-bit add/sub ALU instructions, I think this will be a useful addition to the instruction set utilizing just a few FPGA resources more. I will submit that once I finish testing it. I would also like to make a code repository for Pico/PacoBlaze. If you have code you want/can share I will put it in the web site. Have fun ;o) -- PabloBleyerKocik /"How wonderful it is that nobody need wait a single pablo / moment before starting to improve the world." @bleyer.org / -- Anne FrankArticle: 98655
ALuPin@web.de schrieb: > Do you get DQS from the DDR memory if you send READ commands > to the memory ? >=20 > Rgds > Andr=E9 Ok, you already answered that question.Article: 98656
Somehow mentioning Superscaler just told me your clock is headed down hill. How many LUT levels of logic do you expect and what is your target frequency? Is this a Uni, commercial or hobby project? There are really good reasons to consider time driven ports. A very fast n cycle design can run at the limit of the BRAM or a16b adder or about 3 LUT levels of logic all which are way faster than say a 32b add. This will use about half the total logic and still execute near 150MHz compared to a true simple 1 cycle design. Less logic is much easier to floor plan too. In my processor design I get 4 effective ports out of 1 BRAM (regRR alternates with regW+fetchI) and that runs at +300MHz using 2 clocks per register opcode in V2Pro -5. The datapath combines 2 half 16b results, and the variable length encoded instruction set uses time based muxing to build opcodes rather than lots of mux arrays. The datapath has no register forwarding or hazard logic since the whole thing runs 4 threads. Thats a whole lot of logic not there to slow things down. With 8 clocks per thread opcode, even DRAM cycles don't look so bad provided only 1 thread does a load/store every 16 cycles or so. This is inspired by commutating latency hiding DSP design principles rather than the desire to match current full custom cpus that try (and mostly fail) to get more than 1 opcode per clock. The real problem in computing is not how fast processors might crunch data, but the memory systems ability to feed that. An earlier design that was straight 1 cycle used 3x the logic, 2x the BRAMs and still couldn't get anywhere near 300MHz/2 with all the side control logic stacking up. Time driven logic will always run faster than parallel complex logic, but if you are prototyping or just studying comp architecture, clock performance doesn't really matter so much. FPGAs are good for soft cpu design for true RISC in the John Cocke sense, not the OoO SS VLIW EPIC sense that brute force transister design makes possible. John Jakson Transputer guyArticle: 98657
call your vendor... haha. <langwadt@ieee.org> wrote in message news:1142331145.466345.190480@e56g2000cwe.googlegroups.com... > > Novice wrote: >> I received a design from a vendor, which is designed for Virtex 2 FPGA. >> In the design there are four instances of RAMs, which are of DPRAMs of >> 16bX4096w each. (In fact, there are no WRITE events to these RAMs >> throughout simulations.) >> >> In the test bench, a FOR loop reads in some ASCII files and pumps into >> RAMs at beginning of each simulation. >> >> Now when I convert this portion into ASIC using library RAMs, how should >> I take care of this? >> >> Thank you for your comments. > > If it is never written it is rom not ram .... > > -Lasse >Article: 98658
Avnet provides a test DDR SDRAM controller bit stream with their boards and it works. That's why I'm sure it's my controller problem. But I how could I find out it if even post-place&route simulation works fine? I'm out of ideas.Article: 98659
On a sunny day (13 Mar 2006 19:11:19 -0800) it happened "rickman" <spamgoeshere4@yahoo.com> wrote in <1142305879.517403.68790@e56g2000cwe.googlegroups.com>: > >The FPGA market follows the telecom world, which is where their bread >and butter come from. They can sell their really large parts there >with all the exorbitant markup of the state of the art parts and >telecom needs the flexibility of FPGAs to get state of the art designs >on their boards with a short turn around. Telecom also drives the >speed of the FPGAs which is what makes them use the latest processes >without the mods that the ARM CPU makers use to retain 5 volt >tolerance. So in the end telecom "owns" the FPGA vendors and the rest >of us are just a secondary market. I was reading about new Intel research and they mentioned 200mV processor cores...... It means a lower noise margin, but maybe the low impedances will prevent spikes... or at least external influences. Think this was about indium-antimonide. So, when we get 200mV (100GHz) FPGA then yes, [always drivers] but then perhaps we will have to go optical from the chip.Article: 98660
<langwadt@ieee.org> wrote in message news:1142331145.466345.190480@e56g2000cwe.googlegroups.com... > > If it is never written it is rom not ram .... > > -Lasse > Agree with that, but in the simulations I studied so far, there are R/W data/address and enable connections in the RTL code, and instantiated a coregen DPRAM. Did fair large numbers of coregen RAMs in FPGA before, but now when it comes to ASIC, I am a bit blur. AFAIK, there is no ROM cells in my ASIC library.Article: 98661
>Could someone tell me about data IO's? I read that all data IO's must use >both INFFs, OUTFFs and one of the Tristate-FFs (one could see it in mapper >report). For me all data IO's use only OUTDDR...I am confused. What are you doing with the data you read from the memory ? Could it be that they are not used so that the synthesis tool optimizes the complete read path away ? Rgds Andr=E9Article: 98662
If am running a simulation in modelsim an there is a DCM block with a locked signal. Now because correct me if I am wrong but I would need to stimulate the locked signal myself because the DCM will not set it as this is just a simulation and the DCM is a piece of hardware. Hope that makes sense? Thanks JonArticle: 98663
maxascent wrote: > If am running a simulation in modelsim an there is a DCM block with a > locked signal. Now because correct me if I am wrong but I would need to > stimulate the locked signal myself because the DCM will not set it as this > is just a simulation and the DCM is a piece of hardware. Hope that makes > sense? The DCM model does generate the locked signal. Cheers, JonArticle: 98664
Hello i see your post in a electronic forum and i'm very interested to do the same Can you help me anything? Thanks, sorry my english is very bad _______________________________________________________ José Ángel Domínguez Mateos Laboratorio de Optoelectrónica Área de Cargas Útiles e Instrumentación Departamento de Programas Espaciales y Ciencias del Espacio Instituto Nacional de Técnica Aeroespacial - INTA 28850 Torrejon de Ardoz - Madrid - SPAIN Tel. 91- 520 63 52 Fax. 91- 520 20 94 E-mail dominguezmja@inta.es _______________________________________________________Article: 98665
Bob Perlman wrote:
< snip >
>
> A question for the many folks who use the IDE: what does it really buy
> you that the command tools don't?
>
Memory leaks.
Trashed project files.
Seg faults all over the place.
About 100 major bugs, and about the same amount of bad design.
Then there is the schematic capture, pathetic!
Anyhow:
To stay on subject.
I use ClearCase and cvs/rcs.
Would anyone care to post a Makefile rules template for "ise".
Of the form:
.c.o:
$(CC) $(CFLAGS) -c -o $@ $<
I've been giong to write one but haven't had the chance to sit down
and figure it out yet.
Or just a simple Makefile for some project, would be helpful.
Thanks for any help that can be provided.
--
Gary A. Gorgen | "From ideas to PRODUCTS"
tunxis@comcast.net | Tunxis Design Inc.
| Cupertino, Ca. 95014
Article: 98666I am evaluating them to see if they would be any benifit for a project I am working on. So far I have not been able to run the Xilinx tool because they do not support the current version of Mathworks. From what I can tell it is possible that the whole design could be done in Simulink using the Altera tools, but I find myself asking why. The only real benifit I can see is that the Mathworks tools make a great functional simulation tool. I guess I could see where the wiring could be faster for some people. I am surprized that Altera does not have all of the Simulink functions in the Mega libs. Has anyone used one of these tools? What's your thoughts?Article: 98667
Hello,
I am trying to use altera FIR compiler to design a root
raised cosine filter for a DVB transmitter of HDTV.
However, the FIR coeficients are slightly diferent than the
coeficients I am generating with a mathematical package. Does anyone
knows if this really matters ?
One more thing : I have several diferent symbol rates to
produce my symbols. Should these diferent symbol rates affect my filter
design ? Does anyone knows how to reload the coeficients of a FIR
compiled with an altera FIR compiler ( since I will have diferent
filter for diferent configurations of rool off = 0,20 0,25, and 0,35
and for diferent symbol rates ) ?
Thanks in advance, mel
Article: 98668Novice wrote: > In the test bench, a FOR loop reads in some ASCII files and pumps into > RAMs at beginning of each simulation. > > Now when I convert this portion into ASIC using library RAMs, how should > I take care of this? Depends on the library. Usually ASIC memory models have features to read data in as file images (to speed up the simulations). Or use the same method as in the FPGA. You just have little different memory model to represent the memory. But still at the bottom you have some memory array where the data is stored. In some asic libraries bisr etc. makes the models quite complex but... If that data is static (no writes to the memory) then you have a rom. Pick a rom model from the asic memory generator. If that is not supported directly in the generator, you have to ask from the vendor how they want roms implemented. This all should be covered in the vendor documentation, if you just read it :) --KimArticle: 98669
Hello Ivan, I would like to do a slice-based bus macro. But i don't know how to do. Could you help me or show me the direction? Jean-BaptisteArticle: 98670
I would be very careful of using the "locked" signal in any Spartan-3 based design as it does not always behave in the way that people assume. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development Board. http://www.enterpoint.co.uk "maxascent" <maxascent@yahoo.co.uk> wrote in message news:sMmdnUj9krw4IYvZRVn_vA@giganews.com... > If am running a simulation in modelsim an there is a DCM block with a > locked signal. Now because correct me if I am wrong but I would need to > stimulate the locked signal myself because the DCM will not set it as this > is just a simulation and the DCM is a piece of hardware. Hope that makes > sense? > > Thanks > > JonArticle: 98671
has anybody an example (possibly) written in vhdl of bscan_spartan3 use or similar? thank youArticle: 98672
Hi Laura, Could you please post the product id or name and manufacturer of the board you are using? There are a lot of Altera FPGA boards floating around. Regards, Paul Leventis Altera Corp.Article: 98673
Evan Lavelle wrote: <snip> > No, it doesn't. If the silicon cost you *nothing*, then the biggest > discount you could offer would be 35% before eating into your gross > margins. And I can't believe that you do that, or that the silicon > costs you nothing. Oh, and the unit cost advantage of ASICs has > nothing to do with reduced testing. Gross margins 101: If the part costs you nothing then your gross margins can stay at 65% and be - NOTHING!Article: 98674
Petter Gustad wrote:
> Petter Gustad <newsmailcomp6@gustad.com> writes:
> I forgot to say that I use Linux and write my own Makefiles. It takes
> a little time to set this up for the first time, but after that
> everything is great. Just cvs checkout, make, and your FPGA contains
> the new bitstream some time later...
for vhdl simulation, the emacs command vhdl-generate-makefile
will generate make a Makefile for you. Then
make clean; make;
to get an ordered file list for synthesis.
-- Mike Treseler
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