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Jacques athow wrote: > Is it possible to infer in vhdl, some kind of logic that has the same > property as that of a virtex block ram, but being of size 1 bit (just > using CLB logic) ?? You could use a 1-input lookup-table... http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0283_267.html#wp1001293 But this you'd have to instantiate, I don't know what code you'd use to infer it. As an alternative, you could use a simple flip-flop... those are usually inferred for all signals assigned in a clocked process. Or you can instantiate one: http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0176_160.html#wp1000992 Both the LUT and the register are usually part of a CLB's logic. -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany http://www.iis.fraunhofer.de mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 65476
> If you do NOT use the DCM, you can go as low as you want. > The DCM has a min input frequency of 25 MHz,( except for the FS mode > where the min output frequency is 25 MHz, and the input frequency can > then be significantly lower). FS mode? KenArticle: 65477
Virtex is included in the 6.1 release. Did you install the virtex family when you did the install?. I think it's because I have the webpack as opposed to the full productArticle: 65478
that is not true...bird park asks for a 7$ ticket...and 2$ on petrol...:P "fabbl" <yttt@nukes.com> wrote in message news:2PgSb.1999$ue6.1793@newssvr31.news.prodigy.com... > >And I > > don't want to spend > > more US$50 at all... > > Find another hobby...Bird watching is cheap. > >Article: 65479
Jean: You mentioned sockets are worth $200-$1000...what kind of sockets are those? I think if it is watch-repairing sort of skilled work, maybe it is more interesting than FPGA already... Do you mind give me a example of these expensive sockets? Kelvin "Jean Nicolle" <j.nicolle@sbcglobal.net> wrote in message news:TehSb.7580$jx5.6710@newssvr29.news.prodigy.com... > hum, without changing hobby, you can find some small to medium size FPGAs > without spending too much. > Look for the Xilinx Spartan-2 and the Altera ACEX - small but still usable > devices are in the $10 to $20 range. > > Sockets are expensive though ($200-$1000), so that's not a good solution to > save money. > For boards, look at http://www.fpga-faq.com/FPGA_Boards.shtml > You can find complete boards for less than $50 (most of them CPLD based > though) > The cheapest FPGA board seems to be http://www.fpga4fun.com/board_pluto.html > (10K gates) and doesn't require a parallel cable. > Anybody has other recommendations? > > Jean (fpga4fun) > >Article: 65480
Hi , I am new programmer in VHDL and i have to realize a DLL in an ACTEL ProASIC board. I am using Libero 4.6 and Model Sim 5.6b. I have decided to use as example the 74HC297. I am having problems to implement a Edge Controlled phase detector using a simple SRlatch!(not a doubble SRlatch!) CAn anyone tell me why I got this message on ModelSim: "Iteration limit reached. Possible zero delay oscillation. See the manual." Is not possible to instatiate a simple Latch on Fpga? I am sure to instante a latch because I have veruified on the netlist in Synplify! and on the Designer netlist a Dlatch has been implemented! Is it only a problem in the use of a Simulator? Furthermore I am trying to simulate a simple Dlatch with asyncronous clear with the following testbench: 1) D imput line a signal that represent the frequency I want to lock. 2) Clear input a signal that is opposite to D that represent the frequency that come from the DCO(to "simulate" a phase detector in the case when I am in Lock state ) Thanks for any help! and tips you can suggest! MassimoArticle: 65481
Ron, Check out the PCI app note on the web page. We built it, and it works. Took it to a plug fest. Still works. Customers have built it, and used it, and it works. Xapp 646: "Connecting Virtex II Devices to a PCI 3.3V/5V Bus" Austin Ron Huizen wrote: > One of our guys just returned from a Xilinx training class where a > supposedly informed source stated that the V2Pro somehow breaks PCI support, > i.e. you can't implement a proper PCI interface in them. > > Anyone heard anything about this? > > ------ > Ron Huizen > BittWare > >Article: 65482
Can anyone recommend a firewire link layer IP block that's commercially available? Any information on the FPGA resources taken up by this block would also be appreciated. Thanks, SteveArticle: 65483
On Thu, 29 Jan 2004 21:12:56 -0500, Ray Andraka <ray@andraka.com> wrote: >For example, I used an $18 spartanII chip to demo a shortwave radio implemented >entirely in an FPGA except for the A to D converter and antenna (there is a >block diagram on the front page of my website). Wow, an Ameco preamp--that brings back memories! I once convinced a friend to build an Ameco AC-1 as his first ham transmitter. That was 30 years ago, but I'm still hoping that one of these days he may forgive me. Bob Perlman Cambrian Design WorksArticle: 65484
Hi all, Does the feed back net has to be lock to one of GCLK pads or just normal IO pad is okay? In the past we always lock feed back clock to one GCLK pad, it work fine, but we lose one precious GCLK pads and in VirtexE we have just 4 of those. ThanksArticle: 65485
Austin Lesea <austin@xilinx.com> wrote in message news:<bvc7np$eer1@cliff.xsj.xilinx.com>... > Page 260 of the PowerPC Processor Reference Guide covers JTAG for the > 405PPC. Right, but I think the OP was asking if you could *drive* JTAG from the PPC and I didn't think this was possible (w/o external connections). I want to do this so I can update flash using JTAG and the internal PPC. Alan Nishioka alann@accom.comArticle: 65486
Antti Lukats <antti@case2000.com> wrote: ... : > : at www.ebay.com you can find FPGA BGA pulls at price from : > ^^^^^ : > What do you mean here? : > : > : $9 for 300,000 gates and $49 for 1M Gates FPGA : I got 17pcs of XCV600 for $99 and XCV2000 for $49 : those are all "pulled" and need reballing What reballing service do you use and what price to expect? : > : even if it looks undoable at the first look BGA chips : > : with ball distance of 1mm+ and not full grid are easily : > : used in wire wrap proto boards. : > : > Which FBGA FPGA is not full grid? : http://xilinx.openchip.org/gallery/view_photo.php?set_albumName=album04&id=XCV300_BGA_Proto : sorry I did mean the BGA inner balls are missing, FPGA array is full of Virtex is mostly BGA (1.27 mm ball spacing). That's an easy one to get prototyping boards for at a sensible price, as 0.15mm/0.15mm lines/spaces and 0.3 mm for minimum drill work a long way and the well known prototyping companies ( M&V, PCB Pool) deliver these rules. Also Virtex only occupies four rows from the outside (no full array), while more recent families are mostly FBGA (1.0 mm ball pitch) and those rare in BGA(1.27mm) (BG575/BG728 for Virtex II) are fully occupied... Virtex also has the problem, that it isn't supported by Webpack ... Cyclone in a QFP240 package seems to have the most reachable pins with a recent family. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65487
Dear all
I'm deseprately trying to make an asynchronous counter to count the number
of inputs I have on a pin. I also want a reset input.
I copied the last version of my code at this e-mail .
The synthesis looks good but an error comes at the implementation design. I
don't kow to to do any more.
Thank you for fixing my bugs, Georges.
library ieee;
use ieee.std_logic_1164.all;
entity counter is
port(Load, Rst: in std_logic;
LED: out std_logic_vector(0 to 7)
);
end counter;
architecture behaviour of counter is
signal Qreg: std_logic_vector(0 to 7);
begin
process(Rst, Load)
begin
if Rst = '1' then -- Async reset
Qreg <= "00000000";
elsif Load='1' then
Qreg<=Qreg+1;
end if;
end process;
LED <= Qreg;
end behaviour;
Article: 65488Acronyms.... FS stands for Frequency Synthesis, where the input frequency can be simultaneously multiplied and divided by a range of number choices ( presently 1...32) The other modes are Clock De-skew and Phase Shifting. All this is explained in excruciating detail in the Virtex-II and Virtex-IIPro documentation. Peter Alfke, Xilinx Applications ========= Ken wrote: > > > If you do NOT use the DCM, you can go as low as you want. > > The DCM has a min input frequency of 25 MHz,( except for the FS mode > > where the min output frequency is 25 MHz, and the input frequency can > > then be significantly lower). > > FS mode? > > KenArticle: 65489
Hi, I've worked with ALTERA, XILINX, and ACTEL boards. I really liked the XESS XSA series boards (XILINX). I had the XSA-50 and I actually used it for work, it worked pretty nicely. http://www.xess.com Xess has a big crowd of students and hobbists, and so, you'll find enough info and projects to get started. The xess' boards come with features like LEDS, SRAM, push buttons, Flash, CPLD, and others. If you are looking for just the FPGA with access to as many free I/O pins as you can get, try one of these boards http://www.burched.com.au/ Have fun with whatever you decide to get, David vbetz@altera.com (Vaughn Betz) wrote in message news:<48761f7f.0401202112.526e08bc@posting.google.com>... > x86asm <isaac_8e@hotmail.com> wrote in message news:<45YOb.12249$7JB1.3852@news04.bloor.is.net.cable.rogers.com>... > > Hi guys, I was wondering if there were any good starter kits you know of > > and where I am able to purchase them, I want to dip into VHDL a bit and > > try out my creations on a FPGA, nothing too fancy as I'm no engineer, > > just a hobbyist :) I saw one on Xilinx's online store for ~$50 US is > > that a good choice? > > See http://www.altera.com/products/devkits/kit-dev_platforms.jsp for a > listing of Altera's development boards. The $99 7K board and $195 > Cyclone board are good choices for someone on a budget. The Cyclone > board has a better (bigger & faster) FPGA on it, but for hobby > projects you likely want to focus at least as much on the board I/O > capabilities as you do on the FPGA on the board. So it's good to look > at the list of what's on the board and see if it meets your I/O needs. > > As other posters have pointed out, there's no shortage of dev kits at > pretty low prices out there. > > The cheapest solution of all to get some experience is just to > download a CAD suite and start synthesizing & simulating without a > development kit. > You can get the web edition of Quartus for free from > http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html. > > Regards, > > Vaughn > AlteraArticle: 65490
Your synthesis tool does not synthesize: > process(Rst, Load) > begin > if Rst = '1' then -- Async reset > Qreg <= "00000000"; > elsif Load='1' then > Qreg<=Qreg+1; > end if; But it synthesizes it with a different sensitivity list: process(Rst, Load, QREG) If you simulate (before synthesis) the process with this sensitive list you will notice the loop if LOAD='1' and rst='0'. I'm not sure if you want a latch, but a flipflop solves the problem. Replace > elsif Load='1' then with elsif rising_edge(Load) then Egbert Molenkamp "Georges Konstantinidis" <georges_konstantinidis@hotmail.com> schreef in bericht news:401ab556$0$777$ba620e4c@news.skynet.be... > Dear all > I'm deseprately trying to make an asynchronous counter to count the number > of inputs I have on a pin. I also want a reset input. > I copied the last version of my code at this e-mail . > The synthesis looks good but an error comes at the implementation design. I > don't kow to to do any more. > Thank you for fixing my bugs, Georges. > > > library ieee; > use ieee.std_logic_1164.all; > > entity counter is > port(Load, Rst: in std_logic; > LED: out std_logic_vector(0 to 7) > ); > end counter; > > architecture behaviour of counter is > signal Qreg: std_logic_vector(0 to 7); > > begin > process(Rst, Load) > begin > if Rst = '1' then -- Async reset > Qreg <= "00000000"; > elsif Load='1' then > Qreg<=Qreg+1; > end if; > > end process; > > LED <= Qreg; > > end behaviour; > >Article: 65491
Alan, Since the PPC is all inside the FPGA, and you have to instatiate the JATG to get access to the PPC, I imagine you can wire it anywhere you want in the fabric.... Austin Alan Nishioka wrote: > Austin Lesea <austin@xilinx.com> wrote in message news:<bvc7np$eer1@cliff.xsj.xilinx.com>... > >>Page 260 of the PowerPC Processor Reference Guide covers JTAG for the >>405PPC. > > > Right, but I think the OP was asking if you could *drive* JTAG from > the PPC and I didn't think this was possible (w/o external > connections). > > I want to do this so I can update flash using JTAG and the internal > PPC. > > Alan Nishioka > alann@accom.comArticle: 65492
Does anyone have cpld source code to perform Manchester II encoder/decoder/repeater functions similar to the Harris/Intersil HD-6408 and/or HD-6409 that they are willing to share with me? I will probably have to implement an old combined design that I never tested. I would like to see whether I forgot anything important. Russell MayArticle: 65493
"Georges Konstantinidis" <georges_konstantinidis@hotmail.com> wrote in message news:<401ab556$0$777$ba620e4c@news.skynet.be>... > Dear all > I'm deseprately trying to make an asynchronous counter to count the number > of inputs I have on a pin. I also want a reset input. > I copied the last version of my code at this e-mail . > The synthesis looks good but an error comes at the implementation design. I > don't kow to to do any more. > Thank you for fixing my bugs, Georges. > > > library ieee; > use ieee.std_logic_1164.all; > > entity counter is > port(Load, Rst: in std_logic; > LED: out std_logic_vector(0 to 7) > ); > end counter; > > architecture behaviour of counter is > signal Qreg: std_logic_vector(0 to 7); > > begin > process(Rst, Load) > begin > if Rst = '1' then -- Async reset > Qreg <= "00000000"; > elsif Load='1' then > Qreg<=Qreg+1; > end if; > > end process; > > LED <= Qreg; > > end behaviour; Why do you want to do an async counter? No clock available? What is the implementation error? (Actually, I know what it is -- but I want to know what you think it is.) Think about: What happens if neither Rst nor Load are asserted? --aArticle: 65494
maxaudrito@yahoo.com (Massi) wrote in message news:<abeb94d1.0401300734.68deedbf@posting.google.com>... > Hi , > > I am new programmer in VHDL and i have to realize a DLL in an ACTEL > ProASIC board. > > I am using Libero 4.6 and Model Sim 5.6b. > > I have decided to use as example the 74HC297. > > I am having problems to implement a Edge Controlled phase detector > using a simple SRlatch!(not a doubble SRlatch!) > > CAn anyone tell me why I got this message on ModelSim: > "Iteration limit reached. Possible zero delay oscillation. See the > manual." > > Is not possible to instatiate a simple Latch on Fpga? > > I am sure to instante a latch because I have veruified on the netlist > in Synplify! and on the Designer netlist a Dlatch has been > implemented! > > Is it only a problem in the use of a Simulator? > > Furthermore I am trying to simulate a simple Dlatch with asyncronous > clear with the following testbench: > 1) D imput line a signal that represent the frequency I want to lock. > 2) Clear input a signal that is opposite to D that represent the > frequency that come from the DCO(to "simulate" a phase detector in the > case when I am in Lock state ) Perhaps you can post your code in the appropriate forum: comp.lang.vhdl. --aArticle: 65495
tau14@sussex.ac.uk (Ian) wrote in message news:<63c49b7e.0401290939.274e8b95@posting.google.com>... > Update!! > > I have tried two approaches to solve this problem. > > 1) open the bm_4b.mnc macro with FPGA editor and modify to suit target > architectue (i.e. spartan2) > > Result FPGA editor crashes with message: > > FATAL_ERROR:SpeedData:getspeeds:c:181:1:12 - bad pm for reading speed > file > please refer to answers database > > which obviously has no relevent help at all!! This message is trying to say that the app unexpectedly encountered data from an incorrect architecture (pm=personality module or in this case architecture specific data) which fits your description. The app should have printed a clear user error, but did not. This fatal error is the 2nd line of defense. > > 2) produce my own bus macro design > > Result FPGA Editor crashes whenever I try to relocate a component with > the message > > FATAL_ERROR:GuiUtilities:WinApp.c:$Revision - This application has > discovered an exceptional condition from which it cannot recover. > Process will terminate....Please contact the answers database > > once again the answers database is about as useful as a handbrake on a > canoe. The editor crashed. This message is a generic system crash message equivalent to a unix core dump. I'm not sure what you meant exactly by "relocate". Try an unplace, then manual place from the tools pulldown, if that wasn't what you were doing in the first place. BretArticle: 65496
Philip reminded me that there is a more comprehensive and up to date board list on the FAQ at
http://www.fpga-faq.com/FPGA_Boards.shtml. take a look there and see if there is anything that meets your needs.
dave wrote:
> Hi,
>
> I've worked with ALTERA, XILINX, and ACTEL boards. I really liked
> the XESS XSA series boards (XILINX). I had the XSA-50 and I actually
> used it for work, it worked pretty nicely.
>
> http://www.xess.com
>
> Xess has a big crowd of students and hobbists, and so, you'll find
> enough info and projects to get started. The xess' boards come with
> features like LEDS, SRAM, push buttons, Flash, CPLD, and others. If
> you are looking for just the FPGA with access to as many free I/O pins
> as you can get, try one of these boards http://www.burched.com.au/
>
> Have fun with whatever you decide to get,
>
> David
>
> vbetz@altera.com (Vaughn Betz) wrote in message news:<48761f7f.0401202112.526e08bc@posting.google.com>...
> > x86asm <isaac_8e@hotmail.com> wrote in message news:<45YOb.12249$7JB1.3852@news04.bloor.is.net.cable.rogers.com>...
> > > Hi guys, I was wondering if there were any good starter kits you know of
> > > and where I am able to purchase them, I want to dip into VHDL a bit and
> > > try out my creations on a FPGA, nothing too fancy as I'm no engineer,
> > > just a hobbyist :) I saw one on Xilinx's online store for ~$50 US is
> > > that a good choice?
> >
> > See http://www.altera.com/products/devkits/kit-dev_platforms.jsp for a
> > listing of Altera's development boards. The $99 7K board and $195
> > Cyclone board are good choices for someone on a budget. The Cyclone
> > board has a better (bigger & faster) FPGA on it, but for hobby
> > projects you likely want to focus at least as much on the board I/O
> > capabilities as you do on the FPGA on the board. So it's good to look
> > at the list of what's on the board and see if it meets your I/O needs.
> >
> > As other posters have pointed out, there's no shortage of dev kits at
> > pretty low prices out there.
> >
> > The cheapest solution of all to get some experience is just to
> > download a CAD suite and start synthesizing & simulating without a
> > development kit.
> > You can get the web edition of Quartus for free from
> > http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html.
> >
> > Regards,
> >
> > Vaughn
> > Altera
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65497yes. I wasn't sure how to put that, so I signed with fpga4fun. Thanks for the link. Looks like www.andraka.com has quite some resource too, that should make a good cross-link. I tried to email optimagic a while back, but got no answer. Yes, $100 is reasonable for an FPGA demo board. Unfortunately, there are not many choices below that, and too many choices above...Article: 65498
Try http://www.yamaichi.us/ I'll let you look for distributors and prices.Article: 65499
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:bvd9bc$u0k$1@news.tu-darmstadt.de... > Antti Lukats <antti@case2000.com> wrote: > : "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<bvc3td$7h7$1@reader01.singnet.com.sg>... > : > I have found that FPGA's and cables can be easily built for fun and hobby, > : > but that will break my wallet... > : > but I don't want to buy a demo board at US$45 and pay 50US$ for UPS...And I > : > don't want to spend > : > more US$50 at all... > : > > : > JTAG cable can be built with a parallel cable...but where can I find the > : > FPGA devices and socket for them? > : > > : > Kelvin > > : be smart. be smarter. > > : at www.ebay.com you can find FPGA BGA pulls at price from > ^^^^^ > What do you mean here? > > : $9 for 300,000 gates and $49 for 1M Gates FPGA I got 17pcs of XCV600 for $99 and XCV2000 for $49 those are all "pulled" and need reballing > : even if it looks undoable at the first look BGA chips > : with ball distance of 1mm+ and not full grid are easily > : used in wire wrap proto boards. > > Which FBGA FPGA is not full grid? http://xilinx.openchip.org/gallery/view_photo.php?set_albumName=album04&id=XCV300_BGA_Proto sorry I did mean the BGA inner balls are missing, FPGA array is full of course antti xilinx.openchip.org
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