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> You could use a 1-input lookup-table... > > http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0283_267.html#wp1001293 > > But this you'd have to instantiate, I don't know what code you'd use to > infer it. > > As an alternative, you could use a simple flip-flop... those are usually > inferred for all signals assigned in a clocked process. Or you can > instantiate one: > > http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0176_160.html#wp1000992 > > Both the LUT and the register are usually part of a CLB's logic. Ok thanks for the ideas. For the simple flip-flop, It would need to be clocked by two clock domains. Is it possible to do this in a Virtex FPGA?? and for the LUT alternative, i will try it soon. JacArticle: 65501
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:bve9ca$86p$1@news.tu-darmstadt.de... > Antti Lukats <antti@case2000.com> wrote: > ... > : > : at www.ebay.com you can find FPGA BGA pulls at price from > : > ^^^^^ > : > What do you mean here? > : > > : > : $9 for 300,000 gates and $49 for 1M Gates FPGA > > : I got 17pcs of XCV600 for $99 and XCV2000 for $49 > : those are all "pulled" and need reballing > > What reballing service do you use and what price to expect? sorry, I said "need reballing" not that I have done that reballing I specially selected FPGAs in packages that can be used in wire wrap protos without any need of reballing well I would also like to know what a cheap reballing price is :) > : > : even if it looks undoable at the first look BGA chips > : > : with ball distance of 1mm+ and not full grid are easily > : > : used in wire wrap proto boards. > : > > : > Which FBGA FPGA is not full grid? > > : http://xilinx.openchip.org/gallery/view_photo.php?set_albumName=album04&id=XCV300_BGA_Proto this BGA has not been reballed it is in an condition as I got it from ebay auction > : sorry I did mean the BGA inner balls are missing, FPGA array is full of > > Virtex is mostly BGA (1.27 mm ball spacing). That's an easy one to get > prototyping boards for at a sensible price, as 0.15mm/0.15mm lines/spaces > and 0.3 mm for minimum drill work a long way and the well known prototyping > companies ( M&V, PCB Pool) deliver these rules. Also Virtex only occupies > four rows from the outside (no full array), while more recent families are > mostly FBGA (1.0 mm ball pitch) and those rare in BGA(1.27mm) (BG575/BG728 > for Virtex II) are fully occupied... I think you read my comments wrong I did not mention FBGA at all, so you messed with F - sure most fine grid BGAs are full array and 0.8 mm thats way more complicated for hand made wire wrap - tried once with TMS320C6205 and failed, well could have succeeded also but did it in a rush :) I mostly wanted to have one 2Million gates test platform so obtained a few XCV2000 chips and a XCV300 for getting warm to solder the 2000"s... > Virtex also has the problem, that it isn't supported by Webpack ... yes, as I said too, thats the catch here :( it is supported by free JBits 2.8 but that is not longer officially obtainable :( > Cyclone in a QFP240 package seems to have the most reachable pins with a > recent family. well yes, but that is not easy to get in 1 off quantity :( > Bye > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65502
Khim Bittle wrote: > thanks for the response , you are correct , the problem is not how the > memory chips work but how to manipulate dclk/data0 without nios ... ( > i don't think quartus will let me at them ?) ... i haven't given up > yet .. KB > > If you have a pre-made board then I can see how this can be a problem. However if you are developing a custom board it is not two difficult to multiplex the dclk/data0 pins with user I/O pins to have full control over the serial memory devices.Article: 65503
kkrishnan@wisc.edu (KaRtiK) wrote in message news:<11510c1b.0401292116.28e83545@posting.google.com>... > Is there some way I can generate a physical layout (using Cadence) of > a design written in Verilog and synthesized using Synopsys design > compiler. > I heard there was provision in Cadence for this.. > Any one tried this before? Yes, Cadence provides tools for th entire full custom/std. cell chip design flow. But I'll bet neither one of us (as an individual)can afford them ! Also look at Magma, they have a single tool solution ... Cheers, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 65504
"Marcus Schaemann" <Marcus.Schaemann_invalid@mez.rub.de> wrote in message news:bv5vc2$pvr$1@sunu789.rz.ruhr-uni-bochum.de... > Hello, > > I'm supposed to set up a new VHDL/FPGA lab at our university. But I'm > unsure which operation system and programming solution to use. > Maybe some of you have experience setting up a lab and can answer some > questions. > > We already have the Xilinx ISE Software 6.1i for PC/Solaris/Linux and > Synopsys Software for Solaris and Linux through a Europractice license. > We also have an "old" DLC4 and XC4005, but I guess it's not worth trying > to make that work. (As far as I could find out, DLC4 is not supported > anymore even for ISE 4.2.) > > So here are my questions: > > 1. Which operating system supplies the best performance/environment for > Xilinx development? > I read that the supplied ModelSim II XE works only on PCs, not on > Solaris or Linux. So would you prefer a PC, because of the included > simulation environment? > > 2. If a Solaris/Linux environment is concerned, which simulator is > available/usable? Is Synopsys' scirocco usable? > > 3. Which Download Cable would you recommend? Does the Parallel Cable > only work with a PC (I read that somewhere)? > Or would you prefer the Multilinx Cable? (If so, why?) > > 4. Regarding the programming of the FPGA, would you recommend a separate > design/program environment (e.g. Some Solaris Workstations for > design, and one PC just for programming and testing on a FPGA)? > > I hope someone can enlighten me a bit! > > Regards, > > Marcus I tutor and do some lab support . We are just upgrading from windows nt4 to windows xp. What os depends on what hardware you have and what software is supported and what licenses you get for free. Also if students can get themselves copies of the software for use on their own machines. That is why we use xilinx webpack on windows for students and full ise version in the labs(xilinx university program). We are still using version 5 as haven't received 6 yet, doesn't make much difference as most students don't use fpgas. (Xilinx seems rather slow sending things to non-US uni's, unless its due to the local distributor who is still annoyed at us for buying cplds direct from xilinx due to them being a good bit cheaper ). For introductory digital systems we are still using schematic entry. For advanced digital systems vhdl. Linux version of the webpack isn't out so this isn't an option for the labs yet. P3 1GHz (256MB ram min) and below windows 2000 or linux P3 1GHz 256MB ram and above windows 2000, windows xp or linux Which os depends on the software you can get for that os and how easy it is for students to use. Students buy a kit from the uni, then assemble it. Has experimenter and programmer boards and all components. Programmer board connects to a pc via parallel port and programs both cplds and pic microprocessors on the experimenter board. Using a pic12F675 as a programmable oscillator for the cpld. This way the uni doesn't need to look after the hardware and each student has their own. Gives more chance for hands on debugging. You can put additional boxed programmer boards in the lab but we are removing them as they usually get damaged. (Get some idiot who thinks if the lab programmers or computers don't work they can get an extension on their assignment, so actively disables the lab thats why video surveillance is going in). Which download cable ? Which ever you have.Or get one of the students or support staff to design a programmer and get the pcbs made. We may possibly switch to altera as a couple of the lecturers prefer the quartus software with inbuilt simulation. Also looks like some time in the next year or so Advanced digital systems will switch to fpgas. So we are going to have to come up with a decent student proof fpga design. Thinking about using dip modules for fpga and cplds on the experimenter board, that way we can still have a common board design for both subjects. Current programmer board can already program fpgas. Also want to switch to a usb based programmer due to the fast disappearing parallel port situation. Alex GibsonArticle: 65505
"bob" <kmart@nospam.com> wrote in message news:gb3d105893fkahc14d6eh0veh62frit83g@4ax.com... > Hi I want to make a project that uses an image sensor (any perhaps a > low power cmos from Micron or Kodak) connected to a FPGA (or CPLD). > with the apropriate VHDL or Veralog code. > > Has anyone done this who would be willing to share there hardware > and/or software designs to get me started? > Or is there any examples on the web that I can explore? > > Martin > mart NO inb SPAM AT magma DOT ca > > Remove the NO SPAM and put no spaces. Also replace the AT for @ and > the > DOT for . > > or post replies > > Thanks Have a look at cmucam and similar links for sensors and ideas. cmucam uses a scenix micro http://www.cs.cmu.edu/~cmucam http://www-2.cs.cmu.edu/~cmucam/ http://www-2.cs.cmu.edu/~cmucam/cmucam2/ http://www-2.cs.cmu.edu/~cmucam2/ also look for omnivision.They make and sell cmos sensors http://www.ovt.com/ http://www.ovt.com/i_products.html also http://direct.xilinx.com/bvdocs/appnotes/xapp172.pdf may be of use AlexArticle: 65506
Ben Popoola <b.popoola@ntlworld.com> wrote in message news:<bvftk5$s0mpb$1@ID-207836.news.uni-berlin.de>... > Khim Bittle wrote: > > > thanks for the response , you are correct , the problem is not how the > > memory chips work but how to manipulate dclk/data0 without nios ... ( > > i don't think quartus will let me at them ?) ... i haven't given up > > yet .. KB > > If you have a pre-made board then I can see how this can be a problem. > However if you are developing a custom board it is not two difficult to > multiplex the dclk/data0 pins with user I/O pins to have full control > over the serial memory devices. Ben there is no need to modify the board, see my posting a special cyclone primitive "amsiblock" can be instantiated and that gives full control as needed to read write the config memory. no separate wiring needed AnttiArticle: 65507
New 3rd generation USB interface chip FT2232C has special high speed sync serial modes that allow very fast 1Mbit+ downloads of FPGA configuration streams. there are lots of FPGA boards that use similar feature with old (second generation) FTDI chips, the new chip looks pretty much better specially for FPGA designs as also interfacing to FPGA logic fabric can be implemented more efficiently. hope this is not out of topic, at least I was almost going to design a similar FPGA board (with FT245BM as bootloader), now I would defenetly use the FT2232C. the chips seems to be very new, so the best is to search google on FT2232C at least one supplier promises samples from stock already. anttiArticle: 65508
"Alex Gibson" <me@privacy.net> wrote in message news:bvgehd$rqstt$1@ID-140944.news.uni-berlin.de... > > "bob" <kmart@nospam.com> wrote in message > news:gb3d105893fkahc14d6eh0veh62frit83g@4ax.com... > > Hi I want to make a project that uses an image sensor (any perhaps a > > low power cmos from Micron or Kodak) connected to a FPGA (or CPLD). > > with the apropriate VHDL or Veralog code. > > > > Has anyone done this who would be willing to share there hardware > > and/or software designs to get me started? > > Or is there any examples on the web that I can explore? > > > > Martin > > mart NO inb SPAM AT magma DOT ca > > > > Remove the NO SPAM and put no spaces. Also replace the AT for @ and > > the > > DOT for . > > > > or post replies > > > > Thanks > > Have a look at cmucam and similar links for sensors and ideas. > cmucam uses a scenix micro > > http://www.cs.cmu.edu/~cmucam > http://www-2.cs.cmu.edu/~cmucam/ > http://www-2.cs.cmu.edu/~cmucam/cmucam2/ > http://www-2.cs.cmu.edu/~cmucam2/ > > > also look for omnivision.They make and sell cmos sensors > http://www.ovt.com/ > http://www.ovt.com/i_products.html > > also http://direct.xilinx.com/bvdocs/appnotes/xapp172.pdf > may be of use > > Alex found the other link I was looking for http://www.electronics123.com/amazon/catalogue/c3-1-5.htm for other cmos sensorsArticle: 65509
Antti Lukats wrote: > Ben Popoola <b.popoola@ntlworld.com> wrote in message news:<bvftk5$s0mpb$1@ID-207836.news.uni-berlin.de>... > >>Khim Bittle wrote: >> >> >>>thanks for the response , you are correct , the problem is not how the >>>memory chips work but how to manipulate dclk/data0 without nios ... ( >>>i don't think quartus will let me at them ?) ... i haven't given up >>>yet .. KB >> >>If you have a pre-made board then I can see how this can be a problem. >>However if you are developing a custom board it is not two difficult to >>multiplex the dclk/data0 pins with user I/O pins to have full control >>over the serial memory devices. > > > Ben there is no need to modify the board, see my posting a special > cyclone primitive "amsiblock" can be instantiated and that gives > full control as needed to read write the config memory. no separate > wiring needed > > Antti I have now seen your posting and you are right. However, how widely available is this information? BenArticle: 65510
On 29 Jan 2004 21:54:31 -0800, antti@case2000.com (Antti Lukats) wrote: >khimREMOVEbittle@cliftonREMOVEsystems.com (Khim Bittle) wrote in message >> >> Khim Bittle wrote: >> >> > hi folks ... when using the Cyclones with the EPCS4 flash >> >> > configuration chip and active serial mode ... I'd like to use the >> >> > extra memory space to store a memory image ... so all I need to do is >[snip] >> thanks for the response , you are correct , the problem is not how the >> memory chips work but how to manipulate dclk/data0 without nios ... ( >> i don't think quartus will let me at them ?) ... i haven't given up >> yet .. KB > >http://wiki.openchip.org/index.php/ASMI > >instantiating ASMI Block from VHDL code :) >Antti >xilinx.openchip.org antti ... thanks for the link , KBArticle: 65511
On Sat, 31 Jan 2004 09:59:59 +0000, Ben Popoola <b.popoola@ntlworld.com> wrote: >Khim Bittle wrote: > >> thanks for the response , you are correct , the problem is not how the >> memory chips work but how to manipulate dclk/data0 without nios ... ( >> i don't think quartus will let me at them ?) ... i haven't given up >> yet .. KB >> >> > >If you have a pre-made board then I can see how this can be a problem. >However if you are developing a custom board it is not two difficult to >multiplex the dclk/data0 pins with user I/O pins to have full control >over the serial memory devices. > yes my fall back plan was to use two additional pins ... but for the smaller cost critical cyclone designs using the 144 pins package I/O pins are gold and not having to waste two pins is a big deal to me ... thanks anyway, regards, KBArticle: 65512
Antti Lukats <antti@case2000.com> wrote: : New 3rd generation USB interface chip FT2232C : has special high speed sync serial modes that allow very fast 1Mbit+ : downloads of FPGA configuration streams. : there are lots of FPGA boards that use similar feature with old : (second generation) FTDI chips, the new chip looks pretty much better : specially for FPGA designs as also interfacing to FPGA logic fabric : can be implemented more efficiently. : hope this is not out of topic, at least I was almost going to design a : similar FPGA board (with FT245BM as bootloader), now I would defenetly : use the FT2232C. : the chips seems to be very new, so the best is to search google on : FT2232C : at least one supplier promises samples from stock already. Before you doing so, look around on www.comsec.com/usrp/ There already is a solution with the CY7C68013 and a cyclone for PC configuration download and Usb communication with a complete toolchain. The site seems not to be linked, so look also at http://www.comsec.com/wiki and http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65513
Hi All, In my work, I develop high speed counting and measuring systems. Our systems typically use FPGAs for high speed digital logic and a microcontroller for control and calibration. To reduce costs, power and space, I have been looking at the idea of implementing the microcontroller function into the FPGA using either Microblaze or Nios. Does anyone have experience with these two products? Have you used them in a commercial product? Are these IP cores and the software to implement them mature enough to be practical and reliable? How good is the software development environment for code that runs on the synthesized microcontroller. Do it include breakpoints, single stepping and examination of register and memory variables? I would like to hear anyones experience with Microblaze and Nios. Thanks, Bob DavisArticle: 65514
While waiting for the next announcement.... perhaps some Xilinx person could answer these questions? Crista Souza's and Ron Wilson's piece in EETimes says in the final paragraph: The column-based approach means that IP companies that either license to Xilinx or want to be acquired will **now have precise physical constraints for how to incorporate their IP into Xilinx FPGAs**. Initially, that will whittle down the field of qualified vendors, but ultimately it will result in higher-quality IP, analysts said. Whom should one contact to find out more about these precise physical constraints? Will it require the IP companies to work with expensive ASIC design and verification software, or will there be some new software which has the parameters which the designers can use already set up for the base platform and taking into account these constraints? Thanks Shiraz.Article: 65515
What do you mean by saying "asserted"? "Andy Peters" <Bassman59a@yahoo.com> a écrit dans le message de news:9a2c3a75.0401301451.70df14a6@posting.google.com... > "Georges Konstantinidis" <georges_konstantinidis@hotmail.com> wrote in message news:<401ab556$0$777$ba620e4c@news.skynet.be>... > > Dear all > > I'm deseprately trying to make an asynchronous counter to count the number > > of inputs I have on a pin. I also want a reset input. > > I copied the last version of my code at this e-mail . > > The synthesis looks good but an error comes at the implementation design. I > > don't kow to to do any more. > > Thank you for fixing my bugs, Georges. > > > > > > library ieee; > > use ieee.std_logic_1164.all; > > > > entity counter is > > port(Load, Rst: in std_logic; > > LED: out std_logic_vector(0 to 7) > > ); > > end counter; > > > > architecture behaviour of counter is > > signal Qreg: std_logic_vector(0 to 7); > > > > begin > > process(Rst, Load) > > begin > > if Rst = '1' then -- Async reset > > Qreg <= "00000000"; > > elsif Load='1' then > > Qreg<=Qreg+1; > > end if; > > > > end process; > > > > LED <= Qreg; > > > > end behaviour; > > Why do you want to do an async counter? No clock available? > > What is the implementation error? (Actually, I know what it is -- but > I want to know what you think it is.) > > Think about: > > What happens if neither Rst nor Load are asserted? > > --aArticle: 65516
"Andrew Greensted" <ajg112@ohm.york.ac.uk> wrote in message news:bv5bp6$8i1$1@pump1.york.ac.uk... > Hi All, > Has anyone had any success using a Parallel Cable III (PC3) under Linux > to program a Xilinx FPGA using JTAG? > > I know that Impact (from ise 6.1) does not support the cable (Which is > totally absurd). But is there some other software that I can use? What's your basis for saying that? Impact from 6.1 has check boxes for PC-III as well as IV. We've used it sucessfully for programming both a flash part and Spartan2 parts, then it suddenly stopped working on the Spartan2. Went from totally reliable to never works. We just ordered a PC-IV because of the chronic problems we've had with the -III. Maybe you need a new cable worse than you need new software. Dave KinsellArticle: 65517
David Kinsell <kinsell@poboxyz.com> wrote: : "Andrew Greensted" <ajg112@ohm.york.ac.uk> wrote in message news:bv5bp6$8i1$1@pump1.york.ac.uk... : > Hi All, : > Has anyone had any success using a Parallel Cable III (PC3) under Linux : > to program a Xilinx FPGA using JTAG? : > : > I know that Impact (from ise 6.1) does not support the cable (Which is : > totally absurd). But is there some other software that I can use? : What's your basis for saying that? Impact from 6.1 has check boxes for PC-III : as well as IV. We've used it sucessfully for programming both a flash part and : Spartan2 parts, then it suddenly stopped working on the Spartan2. Went from : totally reliable to never works. We just ordered a PC-IV because of the chronic : problems we've had with the -III. Maybe you need a new cable worse than you : need new software. Dave, you missed the title! We are talking about JTAG download under Linux. Or do you succeed in running ISE6.1 on Linux and download with the JTAG cable? Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65518
Hi Just wanted to here if anyone has an idea to what I am doing wrong. I can not get the integrator and delay components to work in the DSP builder. All the Arithmetic and gates blocks I use, works well, and the FIFO storage element workd well too. Any suggestions are most welcome. /Jacob -- Msg. From Jacob Soerensen jacob@jacob-s.net http://jacob-s.net Nothing in nature is random ... A thing appears random only through the incompleteness of our knowledge. Spinoza, Ethics IArticle: 65519
Is that $18.00 per single piece or $18.00 per 250,000 pieces? Ray Andraka <ray@andraka.com> wrote: : Jean, neat website. In your post you should probably have said that the pluto : board is your board. I added a link from my links page to your site. : The Burch board is also one of the lower cost ones, but is still beyond the $50 : budget. There is a fairly comprehensive list of boards at www.optimagic.com. : Jean, you may want to send them a note with details and a link to your board. : : The Xilinx spartan2 and altera acex parts can be had for not much more than a : song ($10-20 USD), and these have enough gates to do some pretty cool things. : For example, I used an $18 spartanII chip to demo a shortwave radio implemented : entirely in an FPGA except for the A to D converter and antenna (there is a : block diagram on the front page of my website). Unfortunately, it does cost a : bit of money to make a board that is going to be robust enough to work under : hobbyist conditions and provide all the hooks to make it useful. The insight : spartan2 board I used ran a tad over $100 USD, which is more or less the low : end. The Burch board, and Jean's Pluto boards are about all that you'll find : cheaper. :Article: 65520
"Ben Popoola" <b.popoola@ntlworld.com> wrote in message news:bvgj7v$sbhnf$1@ID-207836.news.uni-berlin.de... > > Ben there is no need to modify the board, see my posting a special > > cyclone primitive "amsiblock" can be instantiated and that gives > > full control as needed to read write the config memory. no separate > > wiring needed > > > > Antti > > I have now seen your posting and you are right. However, how widely > available is this information? it is available to ANYONE who has installed Quartus on their machine just look at the libraries - I needed some 30 minutes to "derive" this information. as I dont have any Cyclone device or board, I can not verify in the hardware what the asmiblock ports actually do, but this is the way NIOS does it, and it is available for user logic, so it should be used. A promise - if any one is kind to support openchip with Cyclone target board I will instantly check it out how to access the ASMI port from user logic and publish this information, keeping special "thanks" notice to the donator of the board - dallaslogic are you listening ? :) ok, promise is promise, I possible do it sooner or later, if I dont have board handy then possible later as I have some other things also in que. anttiArticle: 65521
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:bvgoec$p3u$1@news.tu-darmstadt.de... > Antti Lukats <antti@case2000.com> wrote: > : New 3rd generation USB interface chip FT2232C > : has special high speed sync serial modes that allow very fast 1Mbit+ > : downloads of FPGA configuration streams. > Before you doing so, look around on www.comsec.com/usrp/ > > There already is a solution with the CY7C68013 and a cyclone for PC > configuration download and Usb communication with a complete toolchain. > > The site seems not to be linked, so look also at > http://www.comsec.com/wiki > and > http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral thanks this site is really interesting when you get into the non-linked pages :) well CY7C68013 is already "old player" in the field, and I sure know it, my arguments for FT2232C are * smaller package 48 vs 128 TQFP * NO FIRMWARE * NO DRIVERS (all free and available win+linux+mac) * Cheaper so depending what you are doing you have to choose. in cases where today FT245BM is used as FPGA downloader use of FT2232C would bring new advantages. antti PS I am actually not very much fan of FTDI I would prefer to see the new functions of FT2232C in http://www.silabs.com/products/microcontroller/interface.asp or use http://www.silabs.com/products/microcontroller/usb_matrix.asp F320 as bootloader that is very tiny chip MLP28 and includes onchip USB clock generator!!! it mounts completly below the USB connector :)Article: 65522
"Robert Davis" <rkd0930@comcast.net> wrote in message news:5HSSb.150064$sv6.835853@attbi_s52... > Hi All, > > In my work, I develop high speed counting and measuring systems. Our > systems typically use FPGAs for high speed digital logic and a > microcontroller for control and calibration. To reduce costs, power and > space, I have been looking at the idea of implementing the microcontroller > function into the FPGA using either Microblaze or Nios. Does anyone have > experience with these two products? Have you used them in a commercial > product? Are these IP cores and the software to implement them mature > enough to be practical and reliable? How good is the software development > environment for code that runs on the synthesized microcontroller. Do it > include breakpoints, single stepping and examination of register and memory > variables? I would like to hear anyones experience with Microblaze and > Nios. well I am doing exactly this kind of system with MicroBlaze, special cores and peripherals to take care of high speed and Microblaze doing the rest. so what I can say (applies to Xilinx ISE /EDK Microblaze) * useable yes * development environment, useable actually version 6 quite good * break points single stepping all is available you can write custom peripheral cores, and custom logic cores integrate it into the MicroBlaze system and then use it as super-component in toplevel normal FPGA design. You change some C source, compile and merge with bitstream download run debug. It all works. A nice thing is also ChipScope logic analyzer - you can use it also in MicroBlaze design, at the moment I only use the logic analyzer cores in toplevel only but should also be possible to use them inside the MicroBlaze system (or use special OPB Bus Analyzer core). another nice thing is that all this could be done over JTAG port only so if nothing works except JTAG port you can get the MicroBlaze working and examine the program, peripherals, etc.. As of NIOS I assume pretty similar things should be possible as well but I can not comment as so far all attempts to install NIOS license have been failed :( One BIG comment - dont expect always a cost reduction, both MB and NIOS take up FPGA resources and in most cases they need external memory so the cost is relative - if your FPGA is already relativly large then having MB/NIOS is probably very cheap as it takes small % of the FPGA, if your current FPGA is small then adding MB/NIOS would require larger FPGA, possible BGA package, more complex PCB board, etc.. probably a cheapest MB solution is XC2S300E + 16 Bit Flash memory + XC9536XL that downloads the bitstream into FPGA and serves as main code memory later. smallest Xilinx FPGA that is reasonable for MB useage is Spartan 200 (minimal system fits int XC2S100 too, but almost no peripherals). NIOS has more options to choose, some of them should have lower resource need than MB so it could be cheaper in relative FPGA resource terms. Optionally you can use some other more suitable FPGA processor for your system, something that uses less resources. antti xilinx.openchip.orgArticle: 65523
Thank you Antti. You have given me a lot of useful information. We currently use the XC2S200, but I am looking at moving to a larger part, maybe a Spartan 3 when the becomes available. Anyway thanks again. Can any one else share your experience with Microblaze or NIOS. RKD "Antti Lukats" <antti@case2000.com> wrote in message news:bvgvqd$tnc$02$1@news.t-online.com... > "Robert Davis" <rkd0930@comcast.net> wrote in message > news:5HSSb.150064$sv6.835853@attbi_s52... > > Hi All, > > > > In my work, I develop high speed counting and measuring systems. Our > > systems typically use FPGAs for high speed digital logic and a > > microcontroller for control and calibration. To reduce costs, power and > > space, I have been looking at the idea of implementing the microcontroller > > function into the FPGA using either Microblaze or Nios. Does anyone have > > experience with these two products? Have you used them in a commercial > > product? Are these IP cores and the software to implement them mature > > enough to be practical and reliable? How good is the software development > > environment for code that runs on the synthesized microcontroller. Do it > > include breakpoints, single stepping and examination of register and > memory > > variables? I would like to hear anyones experience with Microblaze and > > Nios. > > well I am doing exactly this kind of system with MicroBlaze, special cores > and > peripherals to take care of high speed and Microblaze doing the rest. > > so what I can say (applies to Xilinx ISE /EDK Microblaze) > * useable yes > * development environment, useable actually version 6 quite good > * break points single stepping all is available > > you can write custom peripheral cores, and custom logic cores integrate it > into the > MicroBlaze system and then use it as super-component in toplevel normal FPGA > design. You change some C source, compile and merge with bitstream download > run debug. It all works. A nice thing is also ChipScope logic analyzer - you > can > use it also in MicroBlaze design, at the moment I only use the logic > analyzer cores > in toplevel only but should also be possible to use them inside the > MicroBlaze > system (or use special OPB Bus Analyzer core). > another nice thing is that all this could be done over JTAG port only so if > nothing > works except JTAG port you can get the MicroBlaze working and examine > the program, peripherals, etc.. > > As of NIOS I assume pretty similar things should be possible as well but I > can > not comment as so far all attempts to install NIOS license have been failed > :( > > One BIG comment - dont expect always a cost reduction, both MB and NIOS > take up FPGA resources and in most cases they need external memory so the > cost is relative - if your FPGA is already relativly large then having > MB/NIOS > is probably very cheap as it takes small % of the FPGA, if your current FPGA > is small then adding MB/NIOS would require larger FPGA, possible BGA > package, more complex PCB board, etc.. > > > probably a cheapest MB solution is XC2S300E + 16 Bit Flash memory + XC9536XL > that downloads the bitstream into FPGA and serves as main code memory later. > > smallest Xilinx FPGA that is reasonable for MB useage is Spartan 200 > (minimal system fits int XC2S100 too, but almost no peripherals). > > NIOS has more options to choose, some of them should have lower > resource need than MB so it could be cheaper in relative FPGA resource > terms. > > Optionally you can use some other more suitable FPGA processor for your > system, something that uses less resources. > > antti > xilinx.openchip.org > >Article: 65524
antti@case2000.com (Antti Lukats) writes: > New 3rd generation USB interface chip FT2232C > has special high speed sync serial modes that allow very fast 1Mbit+ > downloads of FPGA configuration streams. If they went to the trouble of designing a new generation USB-serial chip with a high-speed sync mode, why didn't they make it capable of at least 8 Mbps? :-(
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