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Hi,
this is my code. all components are synthesizing individually.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity totaldecoder is
Port ( s1 : in std_logic_vector(2 downto 0);
s2 : in std_logic_vector(2 downto 0);
T3 : in std_logic_vector(3 downto 0);
clk : in std_logic;
clk1 : in std_logic;
reset : in std_logic;
val : out std_logic );
end totaldecoder;
architecture Behavioral of totaldecoder is
component BMUnew
port ( S1 : in std_logic_vector(2 downto 0);
S2 : in std_logic_vector(2 downto 0);
BM0 : out std_logic_vector(3 downto 0);
BM1 : out std_logic_vector(3 downto 0);
BM2 : out std_logic_vector(3 downto 0);
BM3 : out std_logic_vector(3 downto 0));
end component;
component comparatortreenew
port( k1 : in std_logic_vector(5 downto 0);
k2 : in std_logic_vector(5 downto 0);
k3 : in std_logic_vector(5 downto 0);
k4 : in std_logic_vector(5 downto 0);
k5 : in std_logic_vector(5 downto 0);
k6 : in std_logic_vector(5 downto 0);
k7 : in std_logic_vector(5 downto 0);
k8 : in std_logic_vector(5 downto 0);
k9 : in std_logic_vector(5 downto 0);
k10 : in std_logic_vector(5 downto 0);
k11 : in std_logic_vector(5 downto 0);
k12 : in std_logic_vector(5 downto 0);
k13 : in std_logic_vector(5 downto 0);
k14 : in std_logic_vector(5 downto 0);
k15 : in std_logic_vector(5 downto 0);
k16 : in std_logic_vector(5 downto 0);
address : out std_logic_vector(3 downto 0);
min : out std_logic_vector(5 downto 0));
end component;
component TOTALACSUNITS
port( B0 : in std_logic_vector(3 downto 0);
B1 : in std_logic_vector(3 downto 0);
B2 : in std_logic_vector(3 downto 0);
B3 : in std_logic_vector(3 downto 0);
clk : in std_logic;
T : in std_logic_vector(3 downto 0);
reset : in std_logic;
minimum : in std_logic_vector(5 downto 0);
d16 : out std_logic_vector(15 downto 0);
re_traceback,re_counter : out std_logic;
com_smu,com_traceback : in std_logic;
IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7,IN8,
IN9,IN10,IN11,IN12,IN13,IN14,IN15 : out std_logic_vector(5 downto
0));
end component;
component tracebackunitnew
port( clk1 : in std_logic;
decisionbits : in std_logic_vector(15 downto 0);
address : in std_logic_vector(3 downto 0);
output : out std_logic;
complete_smu : out std_logic;
complete_traceback : out std_logic;
reset_traceback : in std_logic;
reset_counter : in std_logic);
end component;
signal B0,B1,B2,B3 : std_logic_vector(3 downto 0);
signal addre : std_logic_vector(3 downto 0);
signal d116 : std_logic_vector(15 downto 0);
signal minimm : std_logic_vector(5 downto 0);
signal r_traceback,r_counter,co_smu,co_traceback : std_logic;
signal YN0,YN1,YN2,YN3,YN4,YN5,YN6,YN7,YN8,YN9,YN10,YN11,YN12,YN13,YN14,YN15
: std_logic_vector(5 downto 0);
begin
BMU1 : BMUnew port map ( S1 => s1,
S2 => s2,
BM0 => B0,
BM1 => B1,
BM2 => B2,
BM3 => B3);
TREE : comparatortreenew port map ( k1 => YN0,
k2 => YN1,
k3 => YN2,
k4 => YN3,
k5 => YN4,
k6 => YN5,
k7 => YN6,
k8 => YN7,
k9 => YN8,
k10 => YN9,
k11 => YN10,
k12 => YN11,
k13 => YN12,
k14 => YN13,
k15 => YN14,
k16 => YN15,
address => addre,
min => minimm );
TRACEBACK : tracebackunitnew port map ( clk1 => clk1,
decisionbits => d116,
address => addre,
output => val,
complete_smu => co_smu,
complete_traceback => co_traceback,
reset_traceback => r_traceback,
reset_counter => r_counter);
TACS : totalacsunits port map( B0 => B0,
B1 => B1,
B2 => B2,
B3 => B3,
clk => clk,
T => T3,
reset => reset,
minimum => minimm,
d16 => d116,
re_traceback => r_traceback,
re_counter => r_counter,
com_smu => co_smu,
com_traceback => co_traceback,
IN0 => YN0,
IN1 => YN1,
IN2 => YN2,
IN3 => YN3,
IN4 => YN4,
IN5 => YN5,
IN6 => YN6,
IN7 => YN7,
IN8 => YN8,
IN9 => YN9,
IN10 =>YN10,
IN11 => YN11,
IN12 => YN12,
IN13 => YN13,
IN14 => YN14,
IN15 => YN15);
end Behavioral;
I am giving the error again.
FATAL_ERROR:HDLParsers:vhptype.c:270:$Id: vhptype.c,v 1.1 2001/03/22
18:59:29 kingsley Exp $:200 - INTERNAL ERROR... while p
arsing G:/sunil/totaldecoder.vhd line 108. Contact your hot line.
Process will terminate. To resolve this error, please con
sult the Answers Database and other online resources at
http://support.xilinx.com
EXEWRAP detected a return code of '1' from program
'F:/Xilinx/bin/nt/xst.exe'
Done: failed with exit code: 0001.
Article: 67151Target chip: XCV600e and later XC2V1000 (>1000 units) This is a very large SOC design that is in its final design and implementation stages. It is basically a video game on a chip. Now we are using distributed ram (64Kb) as asynch ROM memory. With this configuration, the compile time goes up to 30 minutes. Without the ROM, compilation time is a descent 7 minutes. we tried to remove the rom component, while having before compiled it into an NGC file without IO buffers, thinking that XST will take it as a black box and would eventually run the whole process faster, but the process time dropped by about 4 minutes. I wanted to know.. 1) is there a way of making the compilation faster, without changing computer. 2) is there an actual design methodology that could be applied in order to save time (Im thinking of incremental or modular design) Thanks for any suggestionsArticle: 67152
Hello, I am using ISE Foundation 5.2i with a Spartan2 and am running into the following problems: 1. I would like to utilize input/output pads to denote the FPGA I/Os. I typically have been using Schematic Entry and then specify the corresponding pins for the I/O Markers in "Assign Package Pins" (or similar). 2. For this design, I would like to use a 32 bit input bus and 32 bits of output. Rather than placing all 32 on my toplevel schematic, it would be cleaner to use a macro to represent a 32 bit Input pad. However, each time I create said macro with 32 I/O Markers going to a bus, it results in a macro block with 32 input leads (one for each marker). Is there a way to create a macro such that the leads only show on the macro level schematic and the toplevel schematic just has the macro form with desired bus32 output designator? 3. Is an IPAD (IOPAD,OPAD) of any benefit here? I see them mentioned in the ISE5.2i Libraries Guide (IPAD-primitive,IPAD8-macro) but they do not show up as a selectable part in "Select Part-> I/O' of the Schematic utility. Why? 4. Can PACE (Pinout and Constraints Editor) be used to achieve this by creating a UCF for the lowlevel macro? Or is FPGA Editor-> "Add Macro External Pin" better? Thank you for any help you can provide. DurwardArticle: 67153
Being using Quatus 3 for few hours...Compiled a USB phy and a DES without any problem, but where are the manuals for Quatus 3? I used XST user manual/Development system reference/ Constraints Guide/Libraries Guide/Synthesis & sim user guide in Xilinx ISE...what are their equivalent manuals in Altera? Thanks. KelvinArticle: 67154
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Xref: newsmst01.news.prodigy.com comp.arch.fpga:69371
Hi,
i have wrote a VHDL code as below.
i use Xilinx foundation platform.
The situation is:
syntax check --> Check Successful
Synthesis --> Error: HDL translation aborted. =
(HDL-105)
Is there anybody can help me ?
The problem confuse me for long time.
Thanks, Gilbert
-- begin my code
library IEEE;
use IEEE.std_logic_1164.all;
entity Buff is
port (
Data_in: in STD_LOGIC_VECTOR (3 downto 0 );
Data_flag: in STD_LOGIC;
Reset: in STD_LOGIC;
Addr: in STD_LOGIC_VECTOR(7 downto 0); =20
We: in STD_LOGIC; =20
data_out: out STD_LOGIC_VECTOR(3 downto 0)
);
end Buff;
architecture Buff_arch of Buff is
begin
process (Data_flag )
begin =20
if Reset=3D '1' then =20
elsif Rising_Edge(Data_flag) then =20
if We=3D'1' then
case data_in(3 downto 0) is
when "1000" =3D> =20
data_out <=3D "1111"; =20
when others=3D> =20
data_out <=3D "1111"; =20
end case;
end if;=20
end if;
if We=3D'0' then =20
case Addr(3 downto 0) is=20
when "0001" =3D> =20
data_out <=3D "ZZZZ";=20
when others =3D>
data_out <=3D "1111"; =20
end case;
end if;
end process;=20
end Buff_arch;
-- end my code
Article: 67155Hi All, Greetings, I am a student. I found Xilinx 2.1i version software but I think Licence is expired. Can anybody give me the information from where I can get the licence (preferably free because as student I don't have much funds) regards and thnaksArticle: 67156
Typical bus interface consists of CS, ADDR, DATA, RD and WR signals. The bus transfer type designator may be whether read or write, not both simulataneously. That is, RD and WR are mutually exclusive. Why do most bus interfaces separate read and write signals?Article: 67157
On Sun, 07 Mar 2004 06:38:15 -0800, manmohan singh wrote: > Hi All, > Greetings, > > I am a student. I found Xilinx 2.1i version software but I think > Licence is expired. Can anybody give me the information from where I > can get the licence (preferably free because as student I don't have > much funds) > > regards and thnaks You don't want to use 2.1 for anything it's an antique. Xilinx offers webpack which is a free version of their tools. Webpack is a subset but it's probably sufficient for your needs. If you want to use the full set of tools you should have your EE department contact the local Xilinx sales office, I suspect that they would be happy to provide a free or discounted version of their tools to you University.Article: 67158
Hi Kelvin, If you are new to Quartus II and want a quick description of the capabilities present in the Quartus II tool, read the Quartus II Manual first. The manual is available at: http://www.altera.com/literature/manual/intro_to_quartus2.pdf Before reading the Quartus II Handbook you may want to look at the Quartus Online demos. These links will point you to the movie piece (listed under the Self running Documentation column for each topic) as well as the relevant section in the Quartus II handbook (under the Documentation column for each topic). These require a browser and are available at: http://www.altera.com/education/online_demo/onl-index.html?f=dshp&k=g3 The Quartus II Handbook addresses, how to use the Quartus II tools for design entry, synthesis, place and route, simulation, timing analysis, device programming , and interfacingwith other EDA tools like Modelsim, VCS, Synplify. Sections 7 and 8 of the Quartus II Handbook should address most of your questions about Quartus Integrated synthesis for VHDL and Verilog. This handbook document is located at: http://www.altera.com/literature/lit-qts.jsp A quick summary of Quartus II and the Xilinx tools is available at: http://www.altera.com/products/software/pld/design/qts-x2a_migration.html Finally if you are familiar with the Xilinx flow, read App Note 307, about how to convert a Xilinx design into Altera. It has examples how to convert designs constraints and with with Coregen modules (e.g. memory, dll's, multipliers, DDR designs ...). It also covers the command line tools for synthesis, place and route and timing analysis and their switches for the equivalent Quartus II tools, quartus_map, quartus_fit, quartus_tan. App Note 307 is available at: http://www.altera.com/literature/an/an307.pdf Hope this helps. - Subroto Datta Altera Corp. "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:c2f0p2$85k$1@mawar.singnet.com.sg... > Being using Quatus 3 for few hours...Compiled a USB phy and a DES without > any problem, but > where are the manuals for Quatus 3? I used XST user manual/Development > system reference/ > Constraints Guide/Libraries Guide/Synthesis & sim user guide in Xilinx > ISE...what are their > equivalent manuals in Altera? > > Thanks. > Kelvin > > >Article: 67159
William Wallace wrote:
> THE IMPORTANCE OF PROVIDING A RESET THAT LEAVES THE RESET
> SYNCHRONOUSLY EVEN IF IT DRIVES THE ASYNCHRONOUS RESET...
You cannot rely on async reset at startup for initializing one hot state
machines and the like. You need to do something like generate your own
sync reset from some flip flops at startup as in your code example. If
you are using DLLs you also might want to factor the lock output into
your synch reset. This has been discussed here before, you might search
the ng archive. I have been burnt by this bug before, i.e. state
machines starting up 0-hot. This works for me:
-- synchronous part of state machine
process(clk,asynch_rst)
begin
if asynch_rst = '1' then -- the startup global async reset.
state <= idle;
elsif rising_edge(clk) then
if synch_rst = '1' then -- my own synch reset signal.
state <= idle;
else
state <= next_state; -- from combinatorial part of s.m.
end if;
end if;
end process;
-JC
Article: 67160>Typical bus interface consists of CS, ADDR, DATA, RD and WR signals. The bus >transfer type designator may be whether read or write, not both >simulataneously. That is, RD and WR are mutually exclusive. Why do most bus >interfaces separate read and write signals? It's probably left over from directly interfacing to ROMs or SRAMs or Flash chips. It's easy to build small/simple logic if you use the trailing edge of RD or WR as the clock. Think of something like a printer port and look in your old (ancient) data books for TTL/LS era parts. If you only have one of RD and WR, then you also need a clock. You might try to use CS as the clock, but the access time on ROM/RAMs from CS is usually (much) longer than the access time from RD. (CS typically shifts the whole chip into low power mode. It takes a while to wake up again.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67161
The idea is to read a stream of words from a single address location. This demands a mechanism to recognoze that a read cycle has finished. Is it possible? As far as I understand, SDRAM is an asynchronous device. However, 4-way handshaking is not used, so it is not possible to mark the end of transfer. Thanks.Article: 67162
Jeff Cunningham wrote: > > William Wallace wrote: > > THE IMPORTANCE OF PROVIDING A RESET THAT LEAVES THE RESET > > SYNCHRONOUSLY EVEN IF IT DRIVES THE ASYNCHRONOUS RESET... > > You cannot rely on async reset at startup for initializing one hot state > machines and the like. You need to do something like generate your own > sync reset from some flip flops at startup as in your code example. If > you are using DLLs you also might want to factor the lock output into > your synch reset. This has been discussed here before, you might search > the ng archive. I have been burnt by this bug before, i.e. state > machines starting up 0-hot. This works for me: > > -- synchronous part of state machine > process(clk,asynch_rst) > begin > if asynch_rst = '1' then -- the startup global async reset. > state <= idle; > elsif rising_edge(clk) then > if synch_rst = '1' then -- my own synch reset signal. > state <= idle; > else > state <= next_state; -- from combinatorial part of s.m. > end if; > end if; > end process; This is correct. The async global reset is not designed to be fast. So you have to make sure that your design will work if the FFs come out of reset on different clock cycles. There are other ways to do this than using a sync reset. If your design is large, a sync reset may be hard to route to all the FFs that need it within a single clock cycle as well. For state machines, you can use a few prior states to assure that the reset has been released before the FSM gets to "critical" states. For example, if your machine is one hot, you can use a few states that are not one hot, e.g. 000 -> 100 -> 110 -> 111 before your FSM can operate (any gray code will do). Of course, this is really the same as having a "local" sync reset which is another way of doing this. Or if your logic does not have an immediate transition then you don't need to do anything. For example, if your FSM depends on an external signal such as a write strobe, if you have time before the write strobe comes along to let the global reset settle, a separate sync reset is not needed. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67163
I'll definetly keep that in mind. We have a lot coming up over the next few months. Please provide me with additional info privately. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "William Wallace" <msm30@yahoo.com> wrote in message news:7e4865b7.0403052155.49009db7@posting.google.com... > Well, if it makes economic sense to hire a consultant, let me know, > the firm I work at can help. > > "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<oNk0c.18489$jR7.10085@newssvr29.news.prodigy.com>... > > William Wallace wrote: > > > > > He didn't say how many frequencies he was going to use, or what kind > > > of FPGA, or how many bits in the samples. > > > > A few frequencies. Not enough data yet. > > Samples can be up to 16 bits wide x 3 (RGB image processing). > > Virtex 2V1000. > > > > Had to put the project on the shelf for a few days. I'm very tempted to run > > the whole thing at the highest possible frequency (in the context of what > > needs to be done, not the highest attainable by the FPGA) and use clock > > enables. It would seem to me that this is the easiest way to stay out of > > trouble. I like that.Article: 67164
valentin tihomirov wrote: > > The idea is to read a stream of words from a single address location. This > demands a mechanism to recognoze that a read cycle has finished. Is it > possible? As far as I understand, SDRAM is an asynchronous device. However, > 4-way handshaking is not used, so it is not possible to mark the end of > transfer. Thanks. No, SDRAM *is* synchronous, hence the name SDRAM, "Synchronous DRAM". Every cycle on the SDRAM bus is determined by the state of the five chip wide control signals plus the byte specific DQM signal. To find the end of a cycle, I think you only need to consider the chip wide signals since the DQM only controls the enable for a transfer and does not change the FSM. To make this work you will need to either know exactly how your controller operates, or you will need to study the SDRAM data sheets and model the FSM of the SDRAM. It should be simpler to model the controller since it is not likely to use every feature of the SDRAM. But you may not have enough detail to know what it does and does not use. Modeling the SDRAM will take a lot of reading to make sure you have not missed anything, but it will work with all controllers. So either approach has its problems. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67165
"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in message news:c2fodt$1t9i88$1@ID-212430.news.uni-berlin.de... > The idea is to read a stream of words from a single address location. This > demands a mechanism to recognoze that a read cycle has finished. Is it > possible? As far as I understand, SDRAM is an asynchronous device. However, > 4-way handshaking is not used, so it is not possible to mark the end of > transfer. Thanks. > > It's really not obvious what you're trying to accomplish, but the 'S' in SDRAM stands for "Synchronous". "Syncronous Dynamic Random Access Memory", to be complete. SDRAM needs a clock, and all transfers in and out of the device are commanded from the controller and synchronized from the clock. When you do burst reads/writes there is an internal counter in the chip that keeps track.Article: 67166
On Paul Leventis' additional info that the TWOLF Benchmark was also a P&R app I went back and nabbed those results as well for just the 64bit vs. 32bit AMD cases: 2.0 GHz Opeteron time 186, score 1611 2.2 GHz Athlon XP (32bit) time 304, score 929 2.0 GHz Athlon 64 time 204, score 1468 Same story as VPR. New 64 bit processors trounce 32 bit processor even with higher clock. Ken "Kenneth Land" <kland1@neuralog1.com1> wrote in message news:104f0nlms2b281e@news.supernews.com... > On Paul Leventis' info that the VPR Benchmark (Part of SPEC) is an FPGA > Place and Route program I went and looked at a few results at www.spec.org. > > The interface is hideous, but I managed to ferret out a few results: > > 2.0 GHz Opteron time 115, score 1215 > 2.0 GHz Athlon 64 time 127, score 1102 > 2.2 GHz Athon XP (32bit) time 182, score 768 > 3.2 GHz Xeon (1MB cache) time 129, score 1085 > > > I started out looking for a 32bit Athlon vs. 64bit, but couldn't find any > exact matches on a GHz vs. GHz, but the slower 64bit cpu's trounced the 32 > bit XP's even given its faster clock. > > Interesting also that the super Xeon couldn't best the Opteron even with > over a GHz clock advantage. > So if VPR is any indication then a 64 bit AMD system looks very promising. > > Ken > >Article: 67167
Hello, I have been simulating a simple 1-bit register using Xilinx XST tools and ModelSim. The VHDL code implements a register with asynchronous reset (clear). The register gets mapped on to the Virtex-II IOB input FF. When I run the Post- Place and Route simulation, for some reason the FF output remains cleared for more than 100 ns before it starts to work properly. I am clocking the FF at 25 MHz. Changing the clock speed does not change this behaviour. The reset line is only asserted for one clock cycle during start up. Also, changing the implementation to synchronous reset makes no difference. Does anybody have any explanation for this behaviour?Article: 67168
you missed bus idle... "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in message news:c2fed6$1rrsjl$1@ID-212430.news.uni-berlin.de... > Typical bus interface consists of CS, ADDR, DATA, RD and WR signals. The bus > transfer type designator may be whether read or write, not both > simulataneously. That is, RD and WR are mutually exclusive. Why do most bus > interfaces separate read and write signals? > >Article: 67169
Thank you Subroto, these documents are useful. Best Regards, Kelvin Subroto Datta <sdatta@altera.com> wrote in message news:nKH2c.32623$Ld6.6791@newssvr16.news.prodigy.com... > Hi Kelvin, > > If you are new to Quartus II and want a quick description of the > capabilities present in the Quartus II tool, read the Quartus II Manual > first. The manual is available at: > http://www.altera.com/literature/manual/intro_to_quartus2.pdf > > Before reading the Quartus II Handbook you may want to look at the Quartus > Online demos. These links will point you to the movie piece (listed under > the Self running Documentation column for each topic) as well as the > relevant section in the Quartus II handbook (under the Documentation column > for each topic). These require a browser and are available at: > http://www.altera.com/education/online_demo/onl-index.html?f=dshp&k=g3 > > The Quartus II Handbook addresses, how to use the Quartus II tools for > design entry, synthesis, place and route, simulation, timing analysis, > device programming , and interfacingwith other EDA tools like Modelsim, VCS, > Synplify. Sections 7 and 8 of the Quartus II Handbook should address most of > your questions about Quartus Integrated synthesis for VHDL and Verilog. This > handbook document is located at: > http://www.altera.com/literature/lit-qts.jsp > > A quick summary of Quartus II and the Xilinx tools is available at: > http://www.altera.com/products/software/pld/design/qts-x2a_migration.html > > Finally if you are familiar with the Xilinx flow, read App Note 307, about > how to convert a Xilinx design into Altera. It has examples how to convert > designs constraints and with with Coregen modules (e.g. memory, dll's, > multipliers, DDR designs ...). It also covers the command line tools for > synthesis, place and route and timing analysis and their switches for the > equivalent Quartus II tools, quartus_map, quartus_fit, quartus_tan. App Note > 307 is available at: > http://www.altera.com/literature/an/an307.pdf > > Hope this helps. > > - Subroto Datta > Altera Corp. > > "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message > news:c2f0p2$85k$1@mawar.singnet.com.sg... > > Being using Quatus 3 for few hours...Compiled a USB phy and a DES without > > any problem, but > > where are the manuals for Quatus 3? I used XST user manual/Development > > system reference/ > > Constraints Guide/Libraries Guide/Synthesis & sim user guide in Xilinx > > ISE...what are their > > equivalent manuals in Altera? > > > > Thanks. > > Kelvin > > > > > > > >Article: 67170
Tim Wescott wrote: > > "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in > message news:c2fodt$1t9i88$1@ID-212430.news.uni-berlin.de... > > The idea is to read a stream of words from a single address location. This > > demands a mechanism to recognoze that a read cycle has finished. Is it > > possible? As far as I understand, SDRAM is an asynchronous device. > However, > > 4-way handshaking is not used, so it is not possible to mark the end of > > transfer. Thanks. > > > > You think he's got a memory mapped input port?Article: 67171
On Sun, 7 Mar 2004 14:38:04 -0800, Sudhir Singh wrote: >Content-Type: text/html; charset="ISO-8859-1" Please don't post in HTML. Many people either can't or won't read your post, and the charters for the comp hierarchy call for plain text postings only. -- MaxArticle: 67172
"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in message news:<c2fodt$1t9i88$1@ID-212430.news.uni-berlin.de>... > The idea is to read a stream of words from a single address location. This > demands a mechanism to recognoze that a read cycle has finished. Is it > possible? As far as I understand, SDRAM is an asynchronous device. However, > 4-way handshaking is not used, so it is not possible to mark the end of > transfer. Thanks. visit www.micron.com or any no of other sources and get a boatload of details on how SDRAM works, waveforms etc. But its not as easy as old style async srams for sure, but then modern FPGAs have special features in their IOs to support the DDR clocking requirments and bus reversal timings to make it all work. Look forward to doing it myself some time. NOT. You might have been thinking of the much earlier DRAMs prior to the clocked designs that have replaced them all. The only other DRAMs that still exist that are async are really the self timed pseudo statics pretending to be static ram used in cell phones and the like. regards johnjakson_usa_comArticle: 67173
I see lattice have just posted a Metastable document. I recall Peter A. made some Virtex measurements, but looking back at the Xilinx web, I can only find the venerable XAPP 096. - is there anything more up to date / based on newer silicon ? -jgArticle: 67174
I got burned by this area many years ago, so I pay attention when it gets discussed. >Two flip flops are hot. This is bad. That's what bit me. I added a hack/patch so that the 1100... state would shift to 0010... rather than 0110... It's easy if you have a spare LUT input. But that's only one of the screwup patterns. The other one is that it starts in state 0000... Is there any simple way out of that? (I can't see one.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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