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Hal Murray wrote: > I got burned by this area many years ago, so I pay attention > when it gets discussed. > > >>Two flip flops are hot. This is bad. > > > That's what bit me. I added a hack/patch so that the > 1100... state would shift to 0010... rather than 0110... > It's easy if you have a spare LUT input. > > But that's only one of the screwup patterns. The other one is > that it starts in state 0000... > Is there any simple way out of that? (I can't see one.) You can make 0000 a valid state, if it is important that reset recovery delays are minimised. (It is then not strictly one-hot any more...) Gray code and twisted ring/johnson counters are also usefull for state engines. I think some SW allows you to specify what form the underlying HW takes.Article: 67176
> You can make 0000 a valid state, if it is important that >reset recovery delays are minimised. >(It is then not strictly one-hot any more...) I can make 0000 be a valid state with a couple of inverters before and after some FF and maybe using a reset rather than preset on the initial FF. But if you ignore complications like that, and think in terms of a "one" hot state machine that has only one bit on, there are two failure modes - 2 bits on and 0 bits on. The anync reset mess can easily make two bits on. They are adjacent to eachother, so it's easy to filter them out with only local logic. I'm looking for a similar neat/simple way to catch the no bits on case. Or a way to convince myself that it won't happen. >Gray code and twisted ring/johnson counters are also >usefull for state engines. > I think some SW allows you to specify what form the >underlying HW takes. But they give up the simple decoding which is usually the reason I'm using one-hot state machines. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67177
Hal Murray wrote:
> But that's only one of the screwup patterns. The other one is
> that it starts in state 0000...
> Is there any simple way out of that? (I can't see one.)
I don't know a *simple* one.
The *stress-less* one is
binary encoding.
-- Mike Treseler
Article: 67178
gabor@alacron.com (Gabor Szakacs) wrote in message news:<8a436ba2.0403020727.1461694f@posting.google.com>...
> ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0403010655.5c61c49b@posting.google.com>...
> > Dear Sir or Madam,
> >
> > when you go to the linked site you see the simulation plots
> > (functional simulation) of the SRAM controller
> > which I am designing for the SRAM CY7C1399B.
> > There are shown the sram_address, sram_data and the control signals
> > Oe_bar, Cs_bar, We_bar
> > for writing to a location and reading from this location later.
> > But when trying to read from that location the data bus is in
> > undefined state ('U').
> > The reasons could be:
> > 1. writing to that address was not done correctly so that the written
> > data is corrupted.
>
> It's hard to tell from the screen dump, but it looks like you
> might not be meeting the data hold time on writes (from the
> datasheet it is minimum 0 nS after rising edge of write enable,
> but in the simulation it might require nonzero hold time to first
> register the rising edge event. This time would then depend on
> the simulation resolution)
>
> > 2. reading is not done correctly
> > Where could be the problem?
> > I would be very thankful for some useful hint..
> > Andrés Vázquez
> >
> > p.s. Do the changed timing constants in CY7C199.vhd take affect when
> > doing a functional simulation ?
> >
> >
> > http://mitglied.lycos.de/vazquez78/
How can I change that simulation resolution?
Article: 67179hello! As part of my final year project ,Iam working on LOOP filter Design which is 3rd order low pass filter .. this loop filter is a module in costas loop in all digital QPSK demodulation.. Can any of u all help in this design.. Iam coding in VHDL.. Iam using MAX+PLUSII software.. thanx in advance..Article: 67180
Hal Murray wrote: >> You can make 0000 a valid state, if it is important that >>reset recovery delays are minimised. >>(It is then not strictly one-hot any more...) > > > I can make 0000 be a valid state with a couple of inverters > before and after some FF and maybe using a reset rather than > preset on the initial FF. > > But if you ignore complications like that, and think > in terms of a "one" hot state machine that has only one > bit on, there are two failure modes - 2 bits on and > 0 bits on. > > The anync reset mess can easily make two bits on. They > are adjacent to eachother, so it's easy to filter them > out with only local logic. > > I'm looking for a similar neat/simple way to catch the > no bits on case. Or a way to convince myself that it > won't happen. Seems to be equally likely as 'double ones' ? The effect that can cause the upstream Q to miss loading a '0', ( so gives two 1's adjacent) can equally load a '0', but have the downstream reg miss 'passing on' the '1' ( so gives all 0's ) > >>Gray code and twisted ring/johnson counters are also >>usefull for state engines. >> I think some SW allows you to specify what form the >>underlying HW takes. > > > But they give up the simple decoding which is usually > the reason I'm using one-hot state machines. Agreed. I don't think there is any 'silver bullet', but you can design a state engine that has differing start and spin paths. If it's built using D registers, then any illegal states will likely trend to 0000H, even with minimal gating. Covering all illegal states in a One-hot is more a challenge - I can see the potential to use more layers of logic doing this, than decoding a Gray Code design. If you can accept longer to escape to legal states, then logic layers can be reduced. Of course, drastically illegal states (many HI bits) _should_ never happen, provided a reset occurs. -jgArticle: 67181
A couple of things to check. First check that your design is correctly constrained and the timing constraints are meet. Second, check if you have inputs that are asynchronous to the clock used for any internal state machines etc. If you do then you might be in the classic situation where one flip-flop "sees" a change in an input and another does not. This type of timing race will have dependency on temperature, voltage (noise etc) and a variation due to silicon batch. Minor pcb variations could also play a part in this type of problem. John Adair Enterpoint Ltd. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Masoud Naderi" <naderimisc@yahoo.com> wrote in message news:2ba3bbea.0403051417.5f36d35f@posting.google.com... > Hi all, > I have two boards with the exactly same fpga (spartanIIE) and same > code inside them. One of the boards hangs 2~10 minute after power on. > I want to find out the reason. Is it due to power problem on one of > the boards? grouding or ...? > please let me know your ideas. > regards.Article: 67182
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:4046B350.6A5BD112@yahoo.com... > "Paul Leventis (at home)" wrote: > > > > I agree. That's why my original posting makes reference to some SPEC > > results showing that 64-bit code on Athlon64 is ~5% slower than the same > > programs compiled in 32-bit code. One specific SPEC sub-component is a tool > > called VPR, which is an academic place & route tool for FPGAs. It shows a > > 8% slow-down. While by no means comprehensive, I think this gives an idea > > of how much speed to expect out of 64-bit vs. 32-bit code, at least for now. > > > > I've forwarded your comments on how nice it would be to see some results for > > different system configurations on to the relevant groups in Altera. My > > personal experience (going from PII to PIII to P4) has been that SPEC2000 is > > a pretty good proxy for Quartus performance, especially for place & route > > limited designs. > > That is very interesting information. I was not aware of the AMD 64-bit > code was running slower than 32-bit code. I am sure that you won't see > much of that on the AMD web site. I may check in the PC building > newsgroups to see what results they are finding. They seem to be a > bunch that get to the skinny of things like this. > You can find a certain amount of information comparing 32-bit and 64-bit code on the Athlon/Opterons, but a lot of the commonly-used benchmark programs are windows-based, 32-bit only, making them fairly useless. Basically, 64-bit mode has several advantages, but being 64-bit wide isn't really one of them for most software. The width for pointers has great advantages for code that handles huge data structures, and the width for integers is great for applications that can use such large integers. However, the main benifits are almost coincidental to the register width - the AMD64 cpu has many more registers (twice as many?), more SIMD instructions, and a few other bits and pieces. Until we see more code written to really take advantage of these, however, the performance benifits will be small (for example, lots of code with SSE acceleration will test for an Intel chip, and if it finds an AMD chip, runs with "normal" code instead of the faster SIMD code). Critical loops are also often designed with the target architecture in mind - if you know you have more registers to play with, you write it a bit differently to take advantage of them. The big disadvantage of 64-bit mode is that data, especially pointers, is twice as wide - and therefore takes up twice the bandwidth and twice the cache space.Article: 67183
Markus wrote: > Sean and Kelvin, > > I had the same problem (Fatal Errors due to logic0/logic1 on signals). The > logic0/logic1 doesn't seem the problem itself but it leads in the right direction. > > In my case, the error was mostly caused by unconstraint top level logic.If the > logic was moved into a module, the final par was successful. However, I still > have trouble setting constant '0' and '1' on the bus macro inputs, which also > causes your problem even if no real logic is involved. What puzzles me is that > it works for the tutorial (xapp290). > > Please correct me if I am wrong. Yes, you are right. I've opened a WebCase with Xilinx for this, and they too stated that in all cases where this happens, it is in some way related to the top level, as you said. But apparently in some cases it happens even when there is no unplaced or wrongly placed top-level logic, as in my case (I get this error even if I don't have any top-level logic or bus macro connections at all). Plus they told me that there is a bug in par ISE6.1, that too can cause this error. This will probably be fixed in one of the first Service Packs for ISE6.2. -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany http://www.iis.fraunhofer.de mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 67184
"Max" <mtj2@btopenworld.com> wrote in message news:pjbc40d78brb677kje8hhofktn20412et5@4ax.com... > On 03 Mar 2004 18:46:34 +0100, Petter Gustad wrote: > > >I would like to get see synthesis and place and route tools I could > >run on a cluster of cheap PC's. I would be happy with less than linear > >speedups, e.g. using a 16-node cluster to get a 8x speedup. > > I doubt you'd get anywhere near. Trying to implement those algorithms > efficiently on the sort of loosely-coupled architecture you propose > would be nigh-on impossible. It's not easy on a single SMP box, but > it's doable. > > A quad Xeon (8 x CPU) box would cost less than four single decent-spec > machines anyway. > A quad Xeon box has 4 CPUs (hyperthreading only pretends to have 2 cpus), and it will cost a good deal more than 2 dual Xeon boxes would, and certainly far more than a dual or quad Opteron box. Of course, it still doesn't help when the tools are basically single-threaded :-(Article: 67185
"Petter Gustad" <newsmailcomp5@gustad.com> wrote in message news:m3hdx3lhfj.fsf@scimul.dolphinics.no... > Max <mtj2@btopenworld.com> writes: > > > On 04 Mar 2004 22:48:21 +0100, Petter Gustad wrote: > > > > >I hardly ever use Windows so I haven't had a chance to observe this. I > > >don't have a HT system at hand now, but what does > > > > > >grep ^processor /proc/cpuinfo > > > > > >return on a Linux based HT system? > > > > Sorry, don't know from personal experience. I don't use Linux much, > > and when I do, I run it under VMware, which emulates a uniprocessor. > > I got the answer from a local Linux group. It appears as 4 processors: > > $ grep ^processor /proc/cpuinfo > processor : 0 > processor : 1 > processor : 2 > processor : 3 > > So it will be difficult to distinglish between two physical CPU > packages, dual-core and HT... > A Xeon with hyperthreading is a single CPU, which partially emulates two CPUs. It's a good idea, and will speed up some types of applications, but it is very, very far from being a dual-core CPU. You only have one CPU, but two sets of registers - the processor swaps between them, which lets one thread run while another thread is waiting for memory, which reduces waste cycles somewhat. But the result is seldom more than 20% speed increase compared to a single-threading Xeon, and that is only with suitable loads (i.e., two cpu-instensive, low-memory processes running at once), and for many loads, performace will be faster with hyperthreading turned off. If the OS knows that hyperthreaded processors are not really two CPUs, and takes that into account while scheduling tasks, then you get a bit better results. As far as I know, this applies to linux 2.6 kernels, but not 2.4 kernels or any current fork of windows.Article: 67186
Hi, When bypassing both the 8B/10B and 64B/66B encoder and decoders, while otherwise configuring the Rocket I/O similar to the 64B/66B setup (i.e. use 64B/66B scrambler), where do my additional 2 data bits show up in RX and TX direction. The 64B/66B encoder/decoder does not fit my needs, and the 8B/10B is too much waste of the baudrate. I naturally assume that the use of scrambler is sufficient for line-code properties and I view the 64B/66B stuff as specific application encoding stuff which just happends to not be usefull to me for my intended application. PS. Yes, I have been reading the latest UG. Cheers, MagnusArticle: 67187
CS is used to put memory device into IDLE to save power. On the other hand, it can be always active. This is relevation for me. Thanks. I was thinking that CS is used to select between chips that a system wants to talk to. Can you recommend any valuable internet resourse about the topic worth for reading?Article: 67188
Hi, I'm trying to use altera's flex10k with ftdi245bm chip. My software application i write with c++builder. Why in header Ftd2xx.h and library Ftd2xx.lib for usb chip ftdi245bm there is no function FT_ListDevices in C++Builder version? (lib files taken from: http://www.ftdichip.com/Files/D2XXAPP.ZIP) Is this only subset of VC++ ftd2xx functions? (eg. lib files in d2xx driver directory) Does anybody have full library for c++builder? Or have any idea how to generate this from VC++ version? Version for C++Builder are: header Ftd2xx.h 4895 bytes long and library Ftd2xx.lib 2560 bytes long, but version for VC are header Ftd2xx.h 14 464 bytes long and library Ftd2xx.lib 15 188 bytes long Regards, Pawel T.Article: 67189
Hey, I already used some IPCORES from Xilinx but this time i got an error i can't seem to solve and find how it happend. I made a DA FIR core and it generated perfectly but then when i want to synthesize it, it gives me the following error: ERROR:HDLParsers:164 - C:/Xilinx/Projects/stereo_decoder/da_fir.vhd Line 109. parse error, unexpected $ the strange part is don't have that dollar sign in the source code (even when i check with a program to look for hidden signs) so i really don't see what's the problem and how to solve it... if someone can help me, please let me know! thanx in advance, kind regards, Tim (my email is Yttrium@pandora.be)Article: 67190
Everybody else has provides ideas to check with regard to board level hardware problems. What if the problem is a functional problem or a timing problem in the fpga. You have two identical boards but the "stimulus" could very well be different or the order of events could be different. One thing I really hate is when someone says ... I have a problem, the thing "hangs". What does that mean? Maybe if you dig deeper to find out why it "hangs" you can solve your problem. What is happening when it "hangs"? What is it that "hangs"? The thing that "hangs" ... what things could make it "hang"? Mike "Masoud Naderi" <naderimisc@yahoo.com> wrote in message news:2ba3bbea.0403051417.5f36d35f@posting.google.com... > Hi all, > I have two boards with the exactly same fpga (spartanIIE) and same > code inside them. One of the boards hangs 2~10 minute after power on. > I want to find out the reason. Is it due to power problem on one of > the boards? grouding or ...? > please let me know your ideas. > regards.Article: 67191
You have no code between >if Reset= '1' then > elsif Rising_Edge(Data_flag) then You need to set some signals here or get rid of the Reset if you are not resetting anything. Hope this helps. gilbert wrote: > Hi, > > i have wrote a VHDL code as below. > i use Xilinx foundation platform. > The situation is: > > syntax check --> Check Successful > Synthesis --> Error: HDL translation aborted. > (HDL-105) > > Is there anybody can help me ? > > The problem confuse me for long time. > > Thanks, Gilbert > > > > -- begin my code > library IEEE; > use IEEE.std_logic_1164.all; > entity Buff is > port ( > Data_in: in STD_LOGIC_VECTOR (3 downto 0 ); > Data_flag: in STD_LOGIC; > Reset: in STD_LOGIC; > Addr: in STD_LOGIC_VECTOR(7 downto 0); > We: in STD_LOGIC; > data_out: out STD_LOGIC_VECTOR(3 downto 0) > ); > end Buff; > > architecture Buff_arch of Buff is > begin > process (Data_flag ) > begin > if Reset= '1' then > elsif Rising_Edge(Data_flag) then > if We='1' then > case data_in(3 downto 0) is > when "1000" => > data_out <= "1111"; > when others=> > data_out <= "1111"; > end case; > end if; > end if; > if We='0' then > case Addr(3 downto 0) is > when "0001" => > data_out <= "ZZZZ"; > when others => > data_out <= "1111"; > end case; > end if; > > end process; > end Buff_arch; > > -- end my code > > > > >Article: 67192
hello currently latest device supports partial configuration and software does not support it, as far as I know. In that case, we have to do it manually. So could anyone point me out the material, document on - how to implement (realize) partial (re)configuration (for examlple, Virtex )? - are there any previous work on implementation of partial reconfiguration? - are there any previous work on implementation of multi context reconfiguration? thankyou from fpga noviceArticle: 67193
hurjy wrote: > hello > > currently latest device supports partial configuration and software does not > support it, as far as I know. It is supported, there's just a lot of extra steps that have to be taken. Take a look at xapp290: http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany http://www.iis.fraunhofer.de mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 67194
I would suggest the simple way out is synchronous reset. By the way you probably don't need a multi-stage synchronizer for reset unless you're running a very fast clock. Also note that not only reset but *any* input to a one-hot that appears in the state transition logic needs to be synchronous to avoid going "zero-hot." Mike Treseler <mike_treseler@comcast.net> wrote in message news:<Nu6dnWfcBajbg9HdRVn-ig@comcast.com>... > Hal Murray wrote: > > > But that's only one of the screwup patterns. The other one is > > that it starts in state 0000... > > Is there any simple way out of that? (I can't see one.) > > I don't know a *simple* one. > The *stress-less* one is > binary encoding. > > -- Mike TreselerArticle: 67195
The Quartus II 4.0 Web Edition Software with support for the new Stratix II (90 nm FPGA's) and Max II (lHigh density, low power CPLD's) device families is available for download at: http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html For Max+Plus II users, Quartus II 4.0 (Subscription and Web Edition) includes a Max+Plus II look and feel option that can be chosen from the Tools->Customize->General Page. ------------------------------------- The Quartus II 4.0 Documentation includes the following resources : 1. The Quick Start guide covers the basic steps: creating a project, setting device and timing constraints, compilation, walking through the tutorial. This is available at http://www.altera.com/literature/manual/mnl_qts_quick_start.pdf 2. If you are new to Quartus II and want a quick description of all the capabilities present in the Quartus II tool, read the Quartus II Manual first. The manual is available at: http://www.altera.com/literature/manual/intro_to_quartus2.pdf 3. Before reading the Quartus II Handbook you may want to look at the Quartus Online demos. These links will point you to the Flash movie piece (listed under the Self running Documentation column for each topic) as well as the relevant section in the Quartus II handbook (under the Documentation column for each topic). These are available at: http://www.altera.com/education/online_demo/onl-index.html?f=dshp&k=g3 4. The Quartus II Handbook addresses, how to use the Quartus II tools for design entry, synthesis, place and route, simulation, timing analysis, device programming , and interfacing with other EDA tools like Modelsim, VCS, Synplify. Sections 7 and 8 of the Quartus II Handbook should address most of your questions about Quartus Integrated synthesis for VHDL and Verilog. This handbook document is located at: http://www.altera.com/literature/lit-qts.jsp 6. The Quartus II Online Help available from the Quartus Help menu or by clicking F1 inside Quartus on a message or in a dialog box. 7. A quick summary of Quartus II and the Xilinx tools is available at: http://www.altera.com/products/software/pld/design/qts-x2a_migration.html 8. Finally if you are familiar with the Xilinx flow, read App Note 307, about how to convert a Xilinx design into Altera. It has examples how to convert designs constraints and with with Coregen modules (e.g. memory, dll's, multipliers, DDR designs ...). It also covers the command line tools for synthesis, place and route and timing analysis and their switches for the equivalent Quartus II tools, quartus_map, quartus_fit, quartus_tan. App Note 307 is available at: http://www.altera.com/literature/an/an307.pdf - Subroto Datta Altera Corp.Article: 67196
I am trying to find an efficient and simple way to protect prototypes from cloning. One idea relies on using the serial number of the FPGA device, because in any prototyping phase only a hand full devices are present. But is there an embedded hardware register in the FPGA device, which contains a unique serial number? regardsArticle: 67197
Hi, Is somebody know how to increase the jitter in a PLL integrated in a FPGA ?? Thanks in advance...Article: 67198
John, They have designed this for minimum jitter, but I would guess that you could modulate the power and ground dedicated pins for the PLL and make as much jitter as you please. Austin john wrote: > Hi, > > Is somebody know how to increase the jitter in a PLL integrated in a FPGA ?? > > Thanks in advance...Article: 67199
Floorplan the RAMs. The placer goes much quicker if you've directed
placement, and the router is quite a bit faster if it has a good floorplan
to work from. The automatic placement generally does not result in a good
floorplan.
Jacques athow wrote:
> Target chip: XCV600e and later XC2V1000 (>1000 units)
>
> This is a very large SOC design that is in its final design and
> implementation stages. It is basically a video game on a chip. Now we
> are using distributed ram (64Kb) as asynch ROM memory. With this
> configuration, the compile time goes up to 30 minutes. Without the
> ROM, compilation time is a descent 7 minutes.
>
> we tried to remove the rom component, while having before compiled it
> into an NGC file without IO buffers, thinking that XST will take it as
> a black box and would eventually run the whole process faster, but the
> process time dropped by about 4 minutes.
>
> I wanted to know..
> 1) is there a way of making the compilation faster, without changing
> computer.
> 2) is there an actual design methodology that could be applied in
> order to save time (Im thinking of incremental or modular design)
>
> Thanks for any suggestions
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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