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Hi guys, I got a Insight "Virtual Workbench" for Xilinx XCV300 dev.kit board + User Guide. I would like to know if someone has used this kit before and if they have any sample code that I could use for testing my Development Environment. Thanks in advance :-) MarcosArticle: 66951
It's nice to see comp.arch.fpga getting back to its roots. ;-) --MikeArticle: 66952
On Sat, 28 Feb 2004 13:19:13 GMT, "Yttrium" <Yttrium@pandora.be> wrote: >hey, for now i just use > >AREA_GROUP "AreaGroupName" RANGE = SLICE_X0Y79:SLICE_X27Y54 ; >INST "/" AREA_GROUP = " AreaGroupName " ; > >as area constraint but i can't really find how you can place your individual >components? > >let's say you have a root component A which is composed by components B and >C how can you say that you want > >B in the range X0Y0:X10Y10 >C in the range X11Y0:X20Y10 >and if possible A in the range X0Y0:X30Y30 > >i thought it should be something like > >INST "/B" ... or INST "/A/B"... but it all gives an error ... > >btw i'm using xst (ise6.1) ... > >thanx in advance for you comments, > >kind regards, > >Y You may want to read: http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0058_11.html but more importantly: http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0028_6.html and http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0128_81.html The key to your problem is that the INST object selector selects primitive objects such as gates, flipflops, memories, I/O . It does not select clouds of logic, such as a section of HDL hierarchy. When synthesis processes your HDL, it turns it into named gates, ff, .... but these named items are not predictable, so even if you read the netlist (EDIF) (Which XST stupidly does not make available anymore), you would have to create an INST line for each gate, FF, ... . And then when you re-synthesize, all these names would change if you made any change to your source code. The situation is not hopeless though. As you will see in the second reference above, you are allowed to use the "*" wild card. So .... >let's say you have a root component A which is composed by components B and >C how can you say that you want > >B in the range X0Y0:X10Y10 >C in the range X11Y0:X20Y10 >and if possible A in the range X0Y0:X30Y30 The doc says that the top level is ignored: "Top-level block names (design names) are ignored when searching for instance name matches." INST "B/*" LOC = SLICE_X0Y0:SLICE_X10Y10; INST "C/*" LOC = SLICE_X11Y0:SLICE_X20Y10; I don't think another costraint that specifies your top level block "*" and constains to X0Y0:X30Y30 is going to help you, as it will also apply this constraint to the B and C block as well as to the desired stuff that is in A but not B or C. You may have to take this A logic and put it in a new sub block D, which could be constrained to the overlapping region X0Y0:X30Y30 . You will note that the above examples did not require AREA_GROUPS, but could have been rewritten to use that form. I don't guarantee that the above is correct, but I think it should be a good direction for you to proceed. Philip =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 66953
It works, Thanks!
Terrence
"Gabor Szakacs" <gabor@alacron.com> wrote in message
news:8a436ba2.0403010757.4be8c3b7@posting.google.com...
> "Terrence Mak" <stmak@se.cuhk.edu.hk> wrote in message
news:<c1u8a3$24vn$1@justice.itsc.cuhk.edu.hk>...
> > Hi,
> >
> > I am new in using the embeded device (VirtexII-Pro) to implement an
> > algorithm.
> > As I want to count the cpu time of the algorithm , I use the
> > XTime_GetTime(starttime) in the the xtime_l.h library.
> > Also I need to print out the result to a uart by using xil_printf. But
the
> > result did not displayed successfully.
> > Please find the program as follows.
> >
> > Is there any step missed?
> >
> > Many thanks,
> > Terrence
>
> The following statements only allocate pointers, not a memory
> array or structure pointed to. I'm not sure if the XTime_GetTime()
> function allocates memory for you, but I'm sure than sprintf does not.
>
> Thus you're calling functions with uninitialized pointers and
> the result is stored (probably at location zero) where the
> pointers were at the time of call.
>
> > XTime *starttime, *endtime;
> > char *output;
>
> if instead you wrote:
>
> XTime starttime, endtime;
> char output[16]; // or as large as the largest message
>
> xil_printf("start\n");
> XTime_GetTime(&starttime);
>
> // Start computation
>
> ...
>
> //End computation
>
> XTime_GetTime(&endtime);
>
> //convert the long long to a string
> sprintf(output, "%llu", endtime);
>
> ...
>
> you should have better results
Article: 66954
Why you need follow 2 attribute?
// synthesis attribute keep of e is "true"
// synthesis attribute keep of f is "true"
e and f are not flip-flop.
Remove them should be OK
"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> дÈëÓʼþ
news:16s640hupdiocn3a94shc4oid0cdrdu4p8@4ax.com...
> Hi,
> I'm trying to code this structure in Verilog. There are two flip
> flops (c and d) that are identical. XST 6.1.3 wants to merge them
> together. I want to stop it from doing that.
>
> e .---. c
> +-----|D Q|-----
> | +-|>C |
> a .---. b | | | |
> ----|D Q|-----+ | '---'
> +--|>C | | |
> | | | | |
> | '---' | f | .---. d
> | +-----|D Q|-----
> clk-+----------------+-|>C |
> | |
> '---'
>
> created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de
>
>
> I am giving the -equivalent_register_removal YES option to XST (it's
> needed elsewhere in the design) so I have to use attributes to stop
> XST from merging these particular ffs, since I don't wish to
> instantiate unisim components.
>
> When I use the keep attribute on all of c, d, e and f, XST still
> merges the ffs, and comes back with this warning:
>
> WARNING:Xst:638 - in unit foo Conflict on KEEP property on signal e
> and f f signal will be lost.
>
> [ Warning 638 isn't in the Xilinx documentation or the answers
> database. ]
>
> Here's the Verilog:
>
> module foo
> (
> input wire clk,
> input wire a,
> output reg c,
> output reg d
> );
>
> reg b;
>
> wire e = b;
> wire f = b;
>
> // synthesis attribute keep of c is "true"
> // synthesis attribute keep of d is "true"
> // synthesis attribute keep of e is "true"
> // synthesis attribute keep of f is "true"
>
> always @(posedge clk)
> begin
> b <= a;
> c <= e;
> d <= f;
> end
>
> endmodule
>
>
> I have a working solution: add BUFs as follows:
>
> BUF buf_e (.I(b), .O(e));
> BUF buf_f (.I(b), .O(f));
>
> This produces the correct result after synthesis, but I wish to avoid
> using unisim components, because (1) they slow my simulation (even BUF
> contains a specify block!), (2) they aren't portable, and (3) I
> shouldn't have to.
>
>
> Questions:
> - What am I doing wrong? ("Expecting too much from XST" is not an
> acceptable answer.)
> - How can I write the Verilog such that I get the correct result after
> synthesis without needing to instantiate unisim components?
>
> Hint to Xilinx: a "preserve" attribute would be really handy. The
> other synthesis vendors have it. Why doesn't XST?
>
> Thanks,
> Allan.
Article: 66955
Hi all,
I have no idea how big this community is, but I've been trying to set
up a mailing list for people who hack the Altera NIOS kits
(APEX/Cyclone/Stratix) and especially using the Lancelot boards from
www.fpga.nl.
This may sound rather restrictive, but the hope is that there will be
enough of a group that we can trade designs around.
The subscription/archives page is at:
http://www.zytor.com/mailman/listinfo/lancelot
I hope we can get some people together, at least.
-hpa
--
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
If you send me mail in HTML format I will assume it's spam.
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64
Article: 66956The JTAG Standard defines a JTAG reset pin, TRST. This pin is little used. All Altera docs (Datasheets, ANs) define this pin but write nothing about its usage. Therefore we did not connect it at all. But we experience problems in the JTAG chain: some EPC chips (especially big ones, like EPC8) almost never finish the Verification phase. I am wondering if this can be due to the unconnected TRST pins? Janos Ero CERN Div. EPArticle: 66957
Prabhat Gupta wrote: > No I haven't. I do not have their email addresses. You might consider emailing postmaster@mentor.com, briefly explain your situation and ask nicely if they would forward your request to one of the individuals concerned... It's worked for me before! Regards, JohnArticle: 66958
erojr wrote: > The JTAG Standard defines a JTAG reset pin, TRST. This pin is little > used. All Altera docs (Datasheets, ANs) define this pin but write > nothing about its usage. Therefore we did not connect it at all. But we > experience problems in the JTAG chain: some EPC chips (especially big > ones, like EPC8) almost never finish the Verification phase. I am > wondering if this can be due to the unconnected TRST pins? > MaxPlus2 and Quartus produce those *.rpt files. They include an ASCII diagramm showing how the pins are to be connected. Some families don't like open input pins. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 66959
Hi I would like to take the CLK2X output of DCM and give it to the CLKIN pin of 2(TWO) DCM'S.Is it possible to do so. Does this result in more jitter. regards vivekArticle: 66960
I tried once, cascading did not function in simulation. 2nd DCM complained the jitter of its input clock being higher than 1ns. Why not just use CLKFX instead of X2X2... Kelvin "vivek" <vivek_vt@hotmail.com> wrote in message news:e139d08b.0403020140.28fd83c8@posting.google.com... > Hi > I would like to take the CLK2X output of DCM and give it to the > CLKIN pin of 2(TWO) DCM'S.Is it possible to do so. Does this result in > more jitter. > > regards > vivekArticle: 66961
rickman <spamgoeshere4@yahoo.com> wrote in message news:<4043A88D.34C9A526@yahoo.com>... > Ok, thanks. But I am still a bit confused about how to get a FF > preset. Even if this uses the inverter method, how does the synthesis > tool know my FF output is active low vs. active high? Everything I read > seems to indicate that this is only controled if you are using explicit > signals to preset/clear the FF and the chipwide reset will operate the > same way this explicit signal works. I don't want to use an explicit > reset signal, I only want to use the chipwide signal, but I still want > to make some FFs presettable. Do I have to make my HDL code reflect > this explicitly by making every signal default state a '0'? Rick, for what it's worth: I got totally screwed by this. I implemented what I thought was a pretty simple four-state one-hot machine. Leonardo and Precision Synthesis did the right thing with it, and Quartus told me I met timing -- yet in the real hardware the state machine hung in an illegal state. The good thing was that the back-annotated timing simulation using my test bench failed in the same way as the real hardware, but it wasn't clear why until I spoke with an Altera FAE. Yeah, my one-hot state machine came out of reset in an illegal state: 4'b0000. So I haven't quite figured out how to fix this. I was going to try a couple of the fitter magic switches, and maybe force it to use binary encoding, but I've been busy with something else. --aArticle: 66962
"H. Peter Anvin" <hpa@zytor.com> wrote in message news:c216d8$cq5$1@cesium.transmeta.com... > Hi all, > > I have no idea how big this community is, but I've been trying to set > up a mailing list for people who hack the Altera NIOS kits > (APEX/Cyclone/Stratix) and especially using the Lancelot boards from > www.fpga.nl. > > This may sound rather restrictive, but the hope is that there will be > enough of a group that we can trade designs around. > > The subscription/archives page is at: > > http://www.zytor.com/mailman/listinfo/lancelot > > I hope we can get some people together, at least. > I'll join, since I have a Cyclone NIOS kit and a Lancelot card. I haven't done so much with the Lancelot so far, other than getting the demo program up and running. It's a nice system.Article: 66963
Hi Brian, thanks for your answer. Now, it works fine. Regards Jürgen foag@iti.uni-luebeck.de (J?rgen) wrote in message news:<e86d1366.0402230840.5a23f98b@posting.google.com>... > I like to simulate our design by using Xilinx library elements > (RAMB16_s4_s4) with ModelSim SE plus 5.7d (on PC). While using the > downloaded xilinx_lib_4.tcl file I obtain the following error > messages: > > # Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003 > # -- Loading package standard > # -- Loading package std_logic_1164 > # -- Loading package vital_timing > # -- Loading package vital_primitives > # -- Loading package textio > # -- Compiling package vpackage > # -- Compiling package body vpackage > # -- Loading package vpackage > # Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003 > # -- Loading package standard > # -- Loading package std_logic_1164 > # -- Loading package vital_timing > # -- Compiling package vcomponents > # Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003 > # -- Loading package standard > # -- Loading package std_logic_1164 > # -- Loading package std_logic_arith > # -- Loading package std_logic_unsigned > # -- Loading package vital_timing > # -- Loading package vital_primitives > # -- Loading package textio > # -- Loading package vpackage > # -- Compiling entity x_and16 > # -- Compiling architecture x_and16_v of x_and16 > # -- Compiling entity x_and2 > # -- Compiling architecture x_and2_v of x_and2 > # -- Compiling entity x_and3 > # -- Compiling architecture x_and3_v of x_and3 > # -- Compiling entity x_and32 > # -- Compiling architecture x_and32_v of x_and32 > # -- Compiling entity x_and4 > # -- Compiling architecture x_and4_v of x_and4 > # -- Compiling entity x_and5 > # -- Compiling architecture x_and5_v of x_and5 > # -- Compiling entity x_and6 > # -- Compiling architecture x_and6_v of x_and6 > # -- Compiling entity x_and7 > # -- Compiling architecture x_and7_v of x_and7 > # -- Compiling entity x_and8 > # -- Compiling architecture x_and8_v of x_and8 > # -- Compiling entity x_and9 > # -- Compiling architecture x_and9_v of x_and9 > # -- Compiling entity x_bpad > # -- Compiling architecture x_bpad_v of x_bpad > # -- Compiling entity x_buf > # -- Compiling architecture x_buf_v of x_buf > # -- Compiling entity x_buf_pp > # -- Compiling architecture x_buf_pp_v of x_buf_pp > # -- Compiling entity x_bufgmux > # -- Compiling architecture x_bufgmux_v of x_bufgmux > # -- Compiling entity x_bufgmux_1 > # -- Compiling architecture x_bufgmux_1_v of x_bufgmux_1 > # -- Compiling entity x_ckbuf > # -- Compiling architecture x_ckbuf_v of x_ckbuf > # -- Compiling entity x_clkdll_maximum_period_check > # -- Compiling architecture x_clkdll_maximum_period_check_v of > x_clkdll_maximum_period_check > # -- Compiling entity x_clkdll > # -- Compiling architecture x_clkdll_v of x_clkdll > # -- Loading entity x_clkdll_maximum_period_check > # -- Compiling entity x_clkdlle_maximum_period_check > # -- Compiling architecture x_clkdlle_maximum_period_check_v of > x_clkdlle_maximum_period_check > # -- Compiling entity x_clkdlle > # -- Compiling architecture x_clkdlle_v of x_clkdlle > # -- Loading entity x_clkdlle_maximum_period_check > # -- Compiling entity dcm_clock_divide_by_2 > # -- Compiling architecture dcm_clock_divide_by_2_v of > dcm_clock_divide_by_2 > # -- Compiling entity dcm_maximum_period_check > # -- Compiling architecture dcm_maximum_period_check_v of > dcm_maximum_period_check > # -- Compiling entity dcm_clock_lost > # -- Compiling architecture dcm_clock_lost_v of dcm_clock_lost > # -- Compiling entity x_dcm > # -- Compiling architecture x_dcm_v of x_dcm > # -- Loading entity dcm_clock_divide_by_2 > # -- Loading entity dcm_maximum_period_check > # -- Loading entity dcm_clock_lost > # -- Compiling entity x_fddrcpe > # -- Compiling architecture x_fddrcpe_v of x_fddrcpe > # -- Compiling entity x_fddrrse > # -- Compiling architecture x_fddrrse_v of x_fddrrse > # -- Compiling entity x_ff > # -- Compiling architecture x_ff_v of x_ff > # -- Compiling entity x_ibufds > # -- Compiling architecture x_ibufds_v of x_ibufds > # -- Compiling entity x_inv > # -- Compiling architecture x_inv_v of x_inv > # -- Compiling entity x_ipad > # -- Compiling architecture x_ipad_v of x_ipad > # -- Compiling entity x_keeper > # -- Compiling architecture x_keeper_v of x_keeper > # -- Compiling entity x_latch > # -- Compiling architecture x_latch_v of x_latch > # -- Compiling entity x_latche > # -- Compiling architecture x_latche_v of x_latche > # -- Compiling entity x_lut2 > # -- Compiling architecture x_lut2_v of x_lut2 > # -- Compiling entity x_lut3 > # -- Compiling architecture x_lut3_v of x_lut3 > # -- Compiling entity x_lut4 > # -- Compiling architecture x_lut4_v of x_lut4 > # -- Compiling entity x_lut5 > # -- Compiling architecture x_lut5_v of x_lut5 > # -- Compiling entity x_lut6 > # -- Compiling architecture x_lut6_v of x_lut6 > # -- Compiling entity x_lut7 > # -- Compiling architecture x_lut7_v of x_lut7 > # -- Compiling entity x_lut8 > # -- Compiling architecture x_lut8_v of x_lut8 > # -- Compiling entity x_mult18x18 > # -- Compiling architecture x_mult18x18_v of x_mult18x18 > # -- Compiling entity x_mult18x18s > # ** Error: > C:/Programme/FPGAdv61/Modeltech/xilinx/vhdl/unisim/ramb4_s16_s16/vhdl/src/simpri > ms/simprim_VITAL.vhd(9368): VITAL TISD timing generic must be a scalar > form of > VITAL > # delay type > # (1076.4 section 4.3.2.1.3.13) > # ** Error: > C:/Programme/FPGAdv61/Modeltech/xilinx/vhdl/unisim/ramb4_s16_s16/vhdl/src/simpri > ms/simprim_VITAL.vhd(9369): VITAL TISD timing generic must be a scalar > form of > VITAL > # delay type > # (1076.4 section 4.3.2.1.3.13) > # ** Error: > C:/Programme/FPGAdv61/Modeltech/xilinx/vhdl/unisim/ramb4_s16_s16/vhdl/src/simpri > ms/simprim_VITAL.vhd(9391): VHDL Compiler exiting > > What can I do/where can I obtain already compiled Xilinx library > elements for simulation ? > > JürgenArticle: 66964
dear all Let me put a few questions.... During reading XAPP151, the length of frame (Xilinx Virtex) is unclear for me. (2 IOB each 18 bit, each CLB 18 bit ---> then how many CLB in each frame, and how long is each frame?.... 2nd thing is how many padding bits are attached into each frame? 3rd thing unclear is the addressing .... it will be great if there is document (or web) which comprehensively explains how the addressing (via frame) works... Thankyou from fpga noviceArticle: 66965
On Mon, 1 Mar 2004 11:11:47 -0000, Ken Hagan wrote: >> There's also a massive security hole there, though I don't think I'll >> go into detail. It's only one such flaw amongst a multitude, however. > >The hole is smaller than you think, since the "attachment" is empty. >Presumably OE didn't find the end of the attachment so just threw >the contents away. :) Yes, but what if it really WAS a valid script? Like to bet that no-one would open it? And normal Usenet protections don't apply here. According to all relevant RFCs, such a message doesn't contain an attachment at all, so no NNTP server will strip it (I don't count the news server in IIS, obviously). I don't know of any AV software that intercepts NNTP, traffic either, though that could of course be done. OE is simply an incident waiting to happen. It would still be over-priced junk if it was $100 cheaper ;o) -- MaxArticle: 66966
hurjy wrote: > dear all > > Let me put a few questions.... > > During reading XAPP151, the length of frame (Xilinx Virtex) is unclear for > me. (2 IOB each 18 bit, each CLB 18 bit ---> then how many CLB in each > frame, and how long is each frame?.... cite xapp151 p.5: "The number of configuration bits in a frame is 18 × (# CLB_rows+2)... " # CLB_rows depends on which (virtex)device you are using... see Table 3 in xapp151. > > 2nd thing is how many padding bits are attached into each frame? cite again xapp151 p.5: "...and is padded with zeroes on the right (bottom) to fit in 32-bit words." > > 3rd thing unclear is the addressing .... it will be great if there is > document (or web) which comprehensively explains how the addressing (via > frame) works... well, besides it is only for virtex (until now! update to xapp138 is announced maybe some updates to xapp138 will appear there) xapp151 is not that bad, maybe you should spend some more minutes reading it... > > Thankyou > from fpga novice simonArticle: 66967
It sounds like you want to somehow feed the contents of this RAM back into a simulation to reproduce all of the design internals? "T. Irmen" <tirmen@gmx.net> wrote in message news:<c1vft3$a2m$1@nets3.rz.RWTH-Aachen.DE>... > Hi Matt, > > I mean: > You have a board with a few fpga´s running your partinioned design. You > record all IO´s into RAM on the fastes clock (how much depends on your RAM > size). After a trigger you stop and download the RAM. With this information > you step into the netlists, to explore the internal signals. I think every > boolean equation could be calculated, so every signal is visible - 100%. > > clear? > kind regards, > thomasArticle: 66968
Yep, the idea is to record this and use the netlists in the simulation. Is there a way to use edif netlists in modelsim, with usable signal names? What is the preferred way (performance): record first and then watch or record and watch on the fly? thomas "Gabor Szakacs" <gabor@alacron.com> schrieb im Newsbeitrag news:8a436ba2.0403020625.29f249f7@posting.google.com... > It sounds like you want to somehow feed the contents of this > RAM back into a simulation to reproduce all of the design internals? > > "T. Irmen" <tirmen@gmx.net> wrote in message news:<c1vft3$a2m$1@nets3.rz.RWTH-Aachen.DE>... > > Hi Matt, > > > > I mean: > > You have a board with a few fpga´s running your partinioned design. You > > record all IO´s into RAM on the fastes clock (how much depends on your RAM > > size). After a trigger you stop and download the RAM. With this information > > you step into the netlists, to explore the internal signals. I think every > > boolean equation could be calculated, so every signal is visible - 100%. > > > > clear? > > kind regards, > > thomasArticle: 66969
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0403010655.5c61c49b@posting.google.com>...
> Dear Sir or Madam,
>
> when you go to the linked site you see the simulation plots
> (functional simulation) of the SRAM controller
> which I am designing for the SRAM CY7C1399B.
> There are shown the sram_address, sram_data and the control signals
> Oe_bar, Cs_bar, We_bar
> for writing to a location and reading from this location later.
> But when trying to read from that location the data bus is in
> undefined state ('U').
> The reasons could be:
> 1. writing to that address was not done correctly so that the written
> data is corrupted.
It's hard to tell from the screen dump, but it looks like you
might not be meeting the data hold time on writes (from the
datasheet it is minimum 0 nS after rising edge of write enable,
but in the simulation it might require nonzero hold time to first
register the rising edge event. This time would then depend on
the simulation resolution)
> 2. reading is not done correctly
> Where could be the problem?
> I would be very thankful for some useful hint..
> Andrés Vázquez
>
> p.s. Do the changed timing constants in CY7C199.vhd take affect when
> doing a functional simulation ?
>
>
> http://mitglied.lycos.de/vazquez78/
Article: 66970
Hello Terrece,
Try the following:
#include <stdio.h>
#include <math.h>
#include "xgpio.h"
#include "xparameters.h"
#include "xtmrctr.h"
#define TIMER_COUNTER_0 0
main(){
int start, end;
XTmrCtr timer;
// Initialize the External Timer
// XPAR_Timer_DEVICE_ID value below is found in Xparameters.h
// for my design it was #define XPAR_OPB_TIMER_1_DEVICE_ID 0
XTmrCtr_Initialize(&timer, XPAR_Timer_DEVICE_ID);
XTmrCtr_Reset(&timer, TIMER_COUNTER_0);
start = XTmrCtr_GetValue(&timer, TIMER_COUNTER_0);
// Start timer
XTmrCtr_Start(&timer, TIMER_COUNTER_0);
// Start computation
...
//End computation
// Stop timer
XTmrCtr_Stop(&timer, TIMER_COUNTER_0);
end = XTmrCtr_GetValue(&timer, TIMER_COUNTER_0);
// Print out value to stdio (RS-232)
xil_printf("Timer Start value = %d Timer end value = %d \n\r", start,
end);
Regards,
Larry
Terrence Mak wrote:
> Hi,
>
> I am new in using the embeded device (VirtexII-Pro) to implement an
> algorithm.
> As I want to count the cpu time of the algorithm , I use the
> XTime_GetTime(starttime) in the the xtime_l.h library.
> Also I need to print out the result to a uart by using xil_printf. But the
> result did not displayed successfully.
> Please find the program as follows.
>
> Is there any step missed?
>
> Many thanks,
> Terrence
>
> #include "xgpio.h"
> #include "xparameters.h"
> #include "math.h"
> #include "xtime_l.h"
>
>
>
> main() {
> XGpio gpio_reset, gpio_addr, gpio_data;
> int i,j=0, count=0,k, site=0;
> double likelihood[12], probability=0.0, lnL=0.0;
> XTime *starttime, *endtime;
> char *output;
>
>
> xil_printf("start\n");
> XTime_GetTime(starttime);
>
> // Start computation
>
> ...
>
> //End computation
>
> XTime_GetTime(endtime);
>
> //convert the long long to a string
> sprintf(output, "%llu", *endtime);
>
>
> //print the result
> while(*output){
> xil_printf("%c", *output);
> ++output;
> }
>
> }
>
>
>
>
Article: 66971Philip wrote : > but these named items are not predictable, so even if you read the netlist > (EDIF) (Which XST stupidly does not make available anymore) Although not perfect, NGC2EDIF works well enough to unravel any XST net renaming, inspect user applied attributes, etc. http://www.fpga-faq.com/archives/58175.html#58181 Brian p.s. Thanks for your effort in maintaining the fpga-faq archive and board list, those fpga-faq links are much shorter than google'sArticle: 66972
I went from a 2.5GHz Pentium to a 3GHz Xeon and got a very consistent 33% speed increase in Stratix compiles and SOPC Builder generation. I suspect the increased cache size is the most critical thing, since clock rate increased by only 20%, but I'm only speculating. Both machines ran XP and RAM was 1GB in both machines. I'm curious to hear how your compiles improve with AMD/Linux. -- Pete "Pete Fraser" <pete@rgb.com> wrote in message news:<103vj8jovcv761e@news.supernews.com>... > We're currently running a 3 GHz Pentium with 2 GB > memory under Windows 2000. > > We hope to speed things up by 15-20%, by going > to AMD X86-64 and / or Linux. > > Has anybody tried this? > Any feedback?Article: 66973
erojr wrote: > > The JTAG Standard defines a JTAG reset pin, TRST. This pin is little > used. All Altera docs (Datasheets, ANs) define this pin but write > nothing about its usage. Therefore we did not connect it at all. But we > experience problems in the JTAG chain: some EPC chips (especially big > ones, like EPC8) almost never finish the Verification phase. I am > wondering if this can be due to the unconnected TRST pins? Absolutely. TRST will reset the JTAG state machine when it floats high. In addition, you should *never* leave a CMOS input floating. When at an intermediate voltage CMOS will draw large currents through the two FETs between power and ground. This can create voltage transients on the power rail inside the chip which can upset other circuits. TRST should either be driven by the JTAG cable, if the emulator supports it, or pulled to Vdd via a resistor; or both actually, so that the input does not float when the cable is not connected. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66974
Andy Peters wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<4043A88D.34C9A526@yahoo.com>... > > > Ok, thanks. But I am still a bit confused about how to get a FF > > preset. Even if this uses the inverter method, how does the synthesis > > tool know my FF output is active low vs. active high? Everything I read > > seems to indicate that this is only controled if you are using explicit > > signals to preset/clear the FF and the chipwide reset will operate the > > same way this explicit signal works. I don't want to use an explicit > > reset signal, I only want to use the chipwide signal, but I still want > > to make some FFs presettable. Do I have to make my HDL code reflect > > this explicitly by making every signal default state a '0'? > > Rick, for what it's worth: I got totally screwed by this. I > implemented what I thought was a pretty simple four-state one-hot > machine. Leonardo and Precision Synthesis did the right thing with > it, and Quartus told me I met timing -- yet in the real hardware the > state machine hung in an illegal state. > > The good thing was that the back-annotated timing simulation using my > test bench failed in the same way as the real hardware, but it wasn't > clear why until I spoke with an Altera FAE. Yeah, my one-hot state > machine came out of reset in an illegal state: 4'b0000. So I haven't > quite figured out how to fix this. > > I was going to try a couple of the fitter magic switches, and maybe > force it to use binary encoding, but I've been busy with something > else. This is exactly what I am talking about. Even though the synthesis tool is capable of inverting a FF input and output in the logic equations so that a reset to zero operates as a preset to one, there has to be a way to tell the tool in your HDL that it needs to do this on a given FF. *That* is what I am asking about. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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