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Just a small warning to anyone who may be considering making a purchase from Amontec (they seem to use these lists as free advertising to promote their Chameleon POD JTAG interface unit). DON'T RISK IT !! I ordered a POD in August 2003. Although the unit itself arrived in reasonable time, it did not come with an invoice (which is a big problem for me as I need to claim back the cost as a work expense !). Even worse, the total changed to my credit card was 33 euros more than I had been quoted by the Amontec online store. Although I have sent numerous emails to laurent.gauch@amontec.com / info@amontec.com over the past months and used the online 'contact form' on the Amontec website _all_ my requests for an invoice have so far been completely ignored (and there is no telephone number anywhere on the Amontec website). Come on guys... all I want is a !*$%ing invoice !! (and maybe an explanation of where the extra 33 euros I was charged mysteriously came from...) It surely can't be that hard ?? (I'm sorry for such an off topic post - but hopefully it might prevent others from suffering the same problems I have had).Article: 66476
Andre wrote: > Just a small warning to anyone who may be considering making a > purchase from Amontec (they seem to use these lists as free > advertising to promote their Chameleon POD JTAG interface unit). > > DON'T RISK IT !! > > I ordered a POD in August 2003. Although the unit itself arrived in > reasonable time, it did not come with an invoice (which is a big > problem for me as I need to claim back the cost as a work expense !). > > Even worse, the total changed to my credit card was 33 euros more than > I had been quoted by the Amontec online store. > > Although I have sent numerous emails to laurent.gauch@amontec.com / > info@amontec.com over the past months and used the online 'contact > form' on the Amontec website _all_ my requests for an invoice have so > far been completely ignored (and there is no telephone number anywhere > on the Amontec website). > > Come on guys... all I want is a !*$%ing invoice !! (and maybe an > explanation of where the extra 33 euros I was charged mysteriously > came from...) It surely can't be that hard ?? > > (I'm sorry for such an off topic post - but hopefully it might prevent > others from suffering the same problems I have had). Have you tried his ISP: Domain name: bisolution.ch Holder of domain name: Business & Internet Solution Philippe Pharisa Ch de Clos-Regots 30 CH-1630 Bulle Switzerland philippe@pharisa.ch Technical contact: Business & Internet Solution Philippe Pharisa Ch de Clos-Regots 30 CH-1630 Bulle Switzerland philippe@pharisa.ch Name servers: dns1.bisolution.ch [82.146.192.163] dns2.bisolution.ch [82.146.192.162] Tauno Voipio tauno voipio @ iki fiArticle: 66477
Just wondering...how susceptible are these RAM based FPGA devices to power supply transients, brownouts, etc? I am looking on Altera's website and have not found much yet. Thanks, JeffArticle: 66478
I'm working on a design using an Altera Cyclone and a NIOS processor. I'm having a little trouble working out exactly where things stand for copyrights and licenses for the code, especially the NIOS software. As I understand it, the intention of the Altera licensing is that I can use the design and my code, along with the NIOS libraries, on any system I want as long as the programable logic is an Altera device (which is fair enough). However, I have a couple of questions about the details: Each vhdl file generated from a schematic block has an Altera copyright notice. I presume I am free to add our my copyright notice to cover my own additions to the module? I presume I am free to use my own closed-source license on any software modules I write, and link them to the NIOS libraries (including the plugs libraries). Am I able to include parts of Altera's example code in these, and if so, do I need to add copyright clauses there? What about using an open-source license (GPL in particular)? Can I use GPL'ed code in my software? I am well aware that I would have to GPL my own code that uses it, but what about the library code that is generated for the NIOS? Presumably I could not GPL that - is it okay to just make my own code available as GPL'ed? Thanks, David -- David "I love deadlines. I love the whooshing noise they make as they go past." Douglas AdamsArticle: 66479
rickman wrote: > > It's a matter of the business equation more than a technical > > rationalization. FORTH is very cryptic for non-FORTH programmers and > > finding skilled FORTH programmers is not as easy as C programmers. And, > > while productivity with FORTH can be substantially greater than with C or > > Assembly, you are, eventually, forced to contend with code maintenance, > > reuse and changes in design teams (Oh, no! Our only FORTH guy left!). > > You had to go and say that, didn't you! This is being posted to the > Forth newsgroup and you will hear a few comments about this... ;) I realize that. No flames please. I have two decades of Forth experience. I'm from the days when you built your own computer from chips, wrote a monitor, got Forth in there, wrote your own editor and then developed your apps. I enjoy and love Forth. I truly do. I also love a language called APL. I think it should rule the World. Hoewever, when all the smoke and bullshit clears out, you have to run a business, hire people, survive design team changes, hire consultants, maintain code, etc. and the "business equation" I refer to can take precedence. C is pretty hard to avoid. I have a current project that I did in Assembler out of being a snob and not a day goes by that I don't wish I had done it in C. We'll have to re-write it eventually, I already know that. I also draw from the experience of a good friend who started a biotech company about fifteen years ago with a product done entirely in Forth. It worked great. He developed it on his own. Made tons of money. And then, he got stuck with it. He couldn't find decent Forth programmers to remove himself from that position. Anyone can write programs in Forth. Not everyone can write efficient, well engineered programs tough. And, not everyone can walk-up to hundreds of screens of source code and figure it out without lots of coaching. He eventually hired me to convert the whole thing to C. After that he could hire just about anyone to support and expand the product. The only reason I could see to do a Forth machine in an FPGA is that you might have valuable Forth code that needs to run 100x faster than the microprocessor curretly hosting it. So, you do a 6502 (or whatever) on steroids or a true Forth machine in a fast FPGA and solve your problem. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 66480
Goran Bilski <goran@xilinx.com> wrote in message news:<c12r85$l611@cliff.xsj.xilinx.com>... > Hi, > > The multicycle instruction always take multiple cycles. > This is due to the pipeline of MicroBlaze. > MicroBlaze has only 3 pipestages, Instruction Fetch (IF), Operand Fetch > (OF) and Execution Stage (EX) Thanks for the explaination. > The current MicroBlaze is a good tradeoff between area and performance. Sure. > The 950 LUT figure includes the basic features no caches or debug. > The caches is quite cheap on LUTs, around 50 LUTs for the instruction cache. > The cost is that BRAM is needed to handle the caches. Does "basic features" include the h/w divider? I've been trying to reproduce the quoted Dhrystone figures on the simulator, and only get 0.63 MIPS/MHz without it. If I add it, I can get 0.77. It seems strange that on the Web page (http://www.xilinx.com/ipcenter/processor_central/microblaze/performance.htm), the Spartan 3 is rated at 0.8 and the Spartan II is rated at 0.65, yet they are both listed as requiring the same number of logic cells. I would presume that either the performance figure for the Spartan II is too low, or the number of logic cells required by the Spartan 3 and Virtex II's to acheive the quoted figure is actually higher. Incidentally, I've been trying to get the Dhrystone numbers for NIOS as well. Can anybody clarify if their instruction set simulator is cycle accurate? If it is, the figures appear to be 0.64 for a 32-bit implementation and 0.15 for a 16-bit implementation, but I have a feeling that this should be lower. Cheers, JonBArticle: 66481
Anybody knows the specs of the power supply for the Xilinx HW-AFX-FF1152-300 board? The mannual doesn't provide information that how much current consumed for the 5V power connected to the powr brick. JY.Article: 66482
Florian-Wolfgang Stock <f.stock@tu-bs.de> wrote in message news:<40334504$0$17577$9b4e6d93@newsread4.arcor-online.net>... > Hello, > > lenz19@gmx.de (lenz) writes: > > > Which lossless compression algorithms are suited for fpga > > implementation. > > If you know in advance information on the type of data (e.g. english > language) then a Huffman Coding could be a quick and small > solution. It could be e.g. easily done with Lookuptable. Here is an implementation from 2000. http://www.sulimma.de/prak/ss00/projekte/huffman/Huffman.html It was a student project for my lab course. Kolja SulimmaArticle: 66483
Got it. It was testbench problem. His mixed edge module is working fine. Tungsten-W <kelvin8157@hotmail.com> wrote in message news:40357855@news.starhub.net.sg... > Hi, group: > > I use only rising edge and global buffers, but this oddball handed me a > module with a mixed clock design, > it uses both rising & falling edge of same clock. How come the P&Red netlist > and RTL simulation didn't > match. It seems the falling edge register has been removed. > > The registers can be found in the netlist, but in gatelevel simulation, the > data is fed through with a small > wire delay only. > > Is this the right behavior of mixed edge designs? > > Best Regards, > Kelvin > > >Article: 66484
Try open it with FPGA Editor or Floorplanner and see where are all the clock buffers. I think timing report only reports the number of clocks you defined in the UCF plus the clocks derived from DCM...i am also new fpga user so i may not be correct... Kelvin QiDaNei <black@hotmail.com> wrote in message news:403545C8.9252BD05@hotmail.com... > Hi, > I have a V2P7 design going through ISE 6.1, in checking out the PAR > report, it tells me in the device utilization section of this, > > Number of BUFGMUXs 8 out of 16 50% > > But go to timing report table, > > +-------------------------+----------+------+------+------------+----------- --+ > > | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max > Delay(ns)| > +-------------------------+----------+------+------+------------+----------- --+ > > |opb_bram_if_cntlr_1_port | | | | > | | > | _BRAM_Clk | BUFGMUX4S| No | 2300 | 0.626 | > 1.763 | > +-------------------------+----------+------+------+------------+----------- --+ > > | MHz33 | BUFGMUX5P| No | 560 | 0.168 | > 1.310 | > +-------------------------+----------+------+------+------------+----------- --+ > > | ddr_clk_90 | BUFGMUX2P| No | 166 | 0.059 | > 1.307 | > +-------------------------+----------+------+------+------------+----------- --+ > > | clk_90 | BUFGMUX1P| No | 12 | 0.048 | > 1.298 | > +-------------------------+----------+------+------+------------+----------- --+ > > | ppc_clk_s | BUFGMUX6S| No | 2 | 0.000 | > 1.784 | > +-------------------------+----------+------+------+------------+----------- --+ > > | JTGC405TCK | Local | | 1 | 0.000 | > 2.514 | > +-------------------------+----------+------+------+------------+----------- --+ > > you can see that only 5 BUFGMUX are report here. I wonder where are > the other 3 BUFGMUX consumed? > Could you give me some clue? > > Thanks. >Article: 66485
my FPGA experience for two months has shown to me PC was much much more faster than Sun. While I was impressed by the speed of Sun when it was handling digital ASIC layout data...I can't test the speed of the FPGA Editor on Sun as I use Exceed... Kelvin jtw <wrightjt@hotmail.com> wrote in message news:E24Zb.25925$su6.3379@newssvr27.news.prodigy.com... > My experience from ~4-5 years ago was that the PII ran the precursor to ISE > about twice as fast as the unix machines I had access to. Of course, if > someone else was doing anything intensive on the unix machine, it went > further downhill. (Yes, if I ran other apps on the PC, things slowed down, > too... but I could choose whether to run them or not.) I've seen similar > results more recently with Spectrum and ModelSim (i.e., running > significantly faster on what PC I had available versus the unix box I had > available.) > > Jason > > "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message > news:c12art$hg4$1@reader01.singnet.com.sg... > > Hi, there: > > > > I don't understand why a big chunk Sun workstation runs ISE 6 much slower > > than a P3-1GHz!!! > > Is this the right behavior or my workstation is lousy? I remembered my Sun > > was bought 2 years ago, > > over 10K US$... > > > > Anybody use ISE on Unix? > > > > Thanks for your reply... > > Kelvin > > > > > > > >Article: 66486
On Fri, 20 Feb 2004 09:32:49 GMT, "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote: >I also draw from the experience of a good friend who started a biotech >company about fifteen years ago with a product done entirely in Forth. It >worked great. He developed it on his own. Made tons of money. And then, >he got stuck with it. ... >And, not >everyone can walk-up to hundreds of screens of source code and figure it out >without lots of coaching. ... >The only reason I could see to do a Forth machine in an FPGA is that you >might have valuable Forth code that needs to run 100x faster than the >microprocessor curretly hosting it. What a lot of interesting points! The first paragraph is IMHO about the cost of converting (competent) programmers to Forth. MPE almost never hires Forth programmers as permanent staff. In general, learning the business takes much longer than learning a new programming language. The second paragraph illustrates that learning two new things at the same time is vastly more difficult than learning one. Screens so often trigger "corporate immune syndrome" that we gave them up long ago regardless of their technical merit. The quality of the code is a management issue, not a technical issue. The third paragraph illustrates what I consider to be a fallacy these days. Forgive me if I have drawn a wrong inference. With modern optimising Forth compilers such as MPE's VFX, code quality for performance is as good as the ouput of compilers for any other language. The limiting factor is then to find hardware (with the right price/performance ratio) to run the application. Stephen -- Stephen Pelc, stephenXXX@INVALID.mpeltd.demon.co.uk MicroProcessor Engineering Ltd - More Real, Less Time 133 Hill Lane, Southampton SO15 5AF, England tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691 web: http://www.mpeltd.demon.co.uk - free VFX Forth downloadsArticle: 66487
Dear all,
I am trying to do floating point addition, subtraction, multiplication
and division in Microblaze.
According to the specification, it is possible to do so as EDK
included the required library automatically
But after verifying that the library libc.a, libm.a and libxil.a are
included and math.h is also included in the source C program, I still
cannot perform the calculation.
float a=6.4;
float b=7.2;
float c=3.4;
printf("%f, %f, %f", a,b,c);
c=a+b;
printf("%f, %f, %f", a,b,c);
i can print out the result correctly the first time, but in the second
time, the value of c becomes 0? 00000000...
Is there any more stuff I need to do to solve the problem.
Thanks
Article: 66488
In article <pan.2004.02.20.00.04.34.373349@gurney.reilly.home>,
Andrew Reilly <andrew@gurney.reilly.home> wrote:
<SNIP>
>
>Well if you were happy with 64k, then the segmentation wasn't a problem:
>you could be in "tiny" mode all the time (which is how the CP/M converters
>worked, I believe.) The x86 had some more instructions and better
>addressing modes than either the 8085 or Z80. Probably not necessarily
>nicer than the 6809 though (but I only read about the latter: never got to
>actually play with one.)
I can. I've recently been involved in getting two Forths working on
6809 boards (for fun and education). Where the 6502 is the nicest
true 8 bit processor, the 6809 is the nicest 8/16 hybrid processor.
Its reputation is well deserved, it really is a brilliant design
and a joy to program for.
(If you ever manage find the description of the 8086 by its designer
Morse. It is actually not such a bad design.)
Last saturday I gave a talk for the Dutch fig chapter about assembly
programming in Forth. I shaved off 16 states from the 44 states inner
cycle of UM/MOD (Camelforth version). I would be interested if an
optimising compiler could get UM/MOD down to that ...
We (=Dutch Fig chapter) got those boards for free. (Still plenty left
to dole out.) See also http:/home.hccnet.nl/p.c.wiegmans/6809werkgroup
In principle this is a Dutch page, however all programs and most
downloads are in English.
Coming up next are those 68020 VME crates. Studying the addressing
modes (18 in total!) gives the same feeling as the 80386.
It is going overboard with indirect base register with scaled offset
register plus internal and outside offset and such (I don't claim
to get that one right but you get the drift.)
>Idle curiosity: why pick the 8085 over the Z80, in that time frame?
Built in serial port. I like the Z80 but its serial companion chip was
a great pain.
>
>Cheers,
>
>--
>Andrew
>
--
--
Albert van der Horst,Oranjestr 8,3511 RA UTRECHT,THE NETHERLANDS
One man-hour to invent,
One man-week to implement,
One lawyer-year to patent.
Article: 66489You can now download a free preview version of our graphical testbench design tool at: http://www.gmhdl.com --Scott Thibault Green Mountain Computing Systems, Inc. http://www.gmvhdl.comArticle: 66490
Scott Thibault wrote: > You can now download a free preview version of our graphical testbench > design tool at: > http://www.gmhdl.com > > --Scott Thibault > Green Mountain Computing Systems, Inc. > http://www.gmvhdl.com > > I think you mean gmvhdl.com in the first part, non? SalmanArticle: 66491
Absolutely: http://www.gmvhdl.com/ "salman sheikh" <sheikh@pop500.gsfc.nasa.gov> wrote in message news:c155ui$3ut$1@skates.gsfc.nasa.gov... > Scott Thibault wrote: > > You can now download a free preview version of our graphical testbench > > design tool at: > > http://www.gmhdl.com > > > > --Scott Thibault > > Green Mountain Computing Systems, Inc. > > http://www.gmvhdl.com > > > > > > I think you mean gmvhdl.com in the first part, non? > > SalmanArticle: 66492
The largest set of IDT models I know of are at the Free Model Foundry: http://www.eda.org/fmf/wwwpages/model_list.html Unfortunately I don't see your part # there. Maybe you can find a model that is close to your part there? -- Pete ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0402190121.6e44f4c5@posting.google.com>... > Dear Sir or Madam, > > I want to design an SRAM controller for the asynchronous SRAM > IDT71V256SA. > > Can somebody tell me if there is such a VHDL simulation model available? > > Thank you very much. > > Kind regards > > A.Vazquez > G&D > SystemDevelopmentArticle: 66493
? Don't know. There may be a service pack for 4.2 that has the speed files for -6, and then again, you may have to upgrade. If you do, your designs will probably run twice as fast, as every major release has been ~ 50% faster by improvements in the software, mapping, and place and route. Austin ccon wrote: > Hi Austin, > > Thanks for info. But I can't see the -6 option in my old 4.2i fndtn > software. Does that mean I have to upgrade to latest ISE if I want to > use those part? Or is there anyway to get around with my favorite SW ??? >Article: 66494
Jeff, If the transient is long enough, and large enough to upset a configuration latch, the power on reset circuit will see it first, and reset the device, cleaning it out, and preparing for a new configuration load. Since we have been doing FPGAs for 20 years now, that is one basic we had to get right a long long time ago..... The latches themselves maintain their storage down to ~ 300 mV, so anything that dips that low, trips the reset. Austin Jeff wrote: > Just wondering...how susceptible are these RAM based FPGA devices to power > supply transients, brownouts, etc? I am looking on Altera's website and > have not found much yet. > > Thanks, > > Jeff > >Article: 66495
news@sulimma.de (Kolja Sulimma) writes:
> Florian-Wolfgang Stock <f.stock@tu-bs.de> wrote in message
> news:<40334504$0$17577$9b4e6d93@newsread4.arcor-online.net>...
>> Hello,
>>
>> lenz19@gmx.de (lenz) writes:
>>
>> > Which lossless compression algorithms are suited for fpga
>> > implementation.
>>
>> If you know in advance information on the type of data (e.g. english
>> language) then a Huffman Coding could be a quick and small
>> solution. It could be e.g. easily done with Lookuptable.
>
> Here is an implementation from 2000.
> http://www.sulimma.de/prak/ss00/projekte/huffman/Huffman.html
> It was a student project for my lab course.
Exactly something like that I had in mind as I talked from it. The
Restriction with with the advance information could be circumvent by
dynamic generating the Lookuptable (here is the drawback, that you
need 2 Passes over the stuff you want to code).
Florian
--
int m,u,e=0;float l,_,I;main(){for(;1840-e;putchar((++e>907&&942>e?61-m:u)
["\t#*fg-pa.vwCh`lwp-e+#h`lwP##mbjqloE"]^3))for(u=_=l=0;79-(m=e%80)&&
I*l+_*_<6&&26-++u;_=2*l*_+e/80*.09-1,l=I)I=l*l-_*_-2+m/27.;}
Article: 66496Florian-Wolfgang Stock wrote: > > news@sulimma.de (Kolja Sulimma) writes: > > > Florian-Wolfgang Stock <f.stock@tu-bs.de> wrote in message > > news:<40334504$0$17577$9b4e6d93@newsread4.arcor-online.net>... > >> Hello, > >> > >> lenz19@gmx.de (lenz) writes: > >> > >> > Which lossless compression algorithms are suited for fpga > >> > implementation. > >> > >> If you know in advance information on the type of data (e.g. english > >> language) then a Huffman Coding could be a quick and small > >> solution. It could be e.g. easily done with Lookuptable. > > > > Here is an implementation from 2000. > > http://www.sulimma.de/prak/ss00/projekte/huffman/Huffman.html > > It was a student project for my lab course. > > Exactly something like that I had in mind as I talked from it. The > Restriction with with the advance information could be circumvent by > dynamic generating the Lookuptable (here is the drawback, that you > need 2 Passes over the stuff you want to code). Isn't there a variation that generates the table on the fly? I don't know any details, but wouldn't they have this same problem in modem compression, you can only see the data once? Or do they buffer up a block before compressing? Back in the early days, an engineer talked to me about the possibility of patenting a method that worked like this. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66497
Andre wrote: > Just a small warning to anyone who may be considering making a > purchase from Amontec (they seem to use these lists as free > advertising to promote their Chameleon POD JTAG interface unit). > > DON'T RISK IT !! > > I ordered a POD in August 2003. Although the unit itself arrived in > reasonable time, it did not come with an invoice (which is a big > problem for me as I need to claim back the cost as a work expense !). > > Even worse, the total changed to my credit card was 33 euros more than > I had been quoted by the Amontec online store. > > Although I have sent numerous emails to laurent.gauch@amontec.com / > info@amontec.com over the past months and used the online 'contact > form' on the Amontec website _all_ my requests for an invoice have so > far been completely ignored (and there is no telephone number anywhere > on the Amontec website). > > Come on guys... all I want is a !*$%ing invoice !! (and maybe an > explanation of where the extra 33 euros I was charged mysteriously > came from...) It surely can't be that hard ?? > > (I'm sorry for such an off topic post - but hopefully it might prevent > others from suffering the same problems I have had). Hi Andre, Hi Tauno, Do you form a *SPAM* consortium ? TEDArticle: 66498
> Incidentally, I've been trying to get the Dhrystone numbers for NIOS > as well. Can anybody clarify if their instruction set simulator is > cycle accurate? If it is, the figures appear to be 0.64 for a 32-bit > implementation and 0.15 for a 16-bit implementation, but I have a > feeling that this should be lower. > > Cheers, > JonB Jon, RTL simulation in Nios of instruction execution (using ModelSim or similar) is cycle accurate. This is true for whether you're executing out of on-chip memory, SRAM (via simulation model), or SDRAM (we include a simulation model in the latest Nios kit). For Dhrystone, you can just run in hardware (much faster than running a long simulation) to compare slight changes you make to Nios. That said, I agree what you're seeing is a bit high - we've seen 0.4 (SDRAM + cache) to 0.5DMips/mhz (on-chip mem) for 32-bit "classic" Nios. It makes me wonder if there is some difference in code? I would also recommend that in what ever benchmark you do, to have the memory (program/data/cache) as you will have it in your final application to get the most realistic results possible. Finally, while Dhrystone is pretty popular, the biggest advantage of going with a soft-core CPU (regardless of whose it is) is that you're in an environment where things can be tweaked to make your application much faster. Custom instructions & peripherals can do wonders depending on what your code looks like. One of my colleagues has a cover article in Embedded Systems Programming this month that you may find useful (sorry for the shameless plug..): http://www.embedded.com/showArticle.jhtml?articleID=17500157 ...of course, you can also wait a bit for Nios II :) Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 66499
praveenkn123@yahoo.com (prav) wrote in message news:<863df22b.0402172352.5886ed1c@posting.google.com>... > hi all, > > I have a counter running at 50 Mhz . Now i have to sample that counter > at 77 Mhz. > > My question is can i sample the counter running at 50 mhz directly > with 77 mhz clock or should i synchronize the 50 mhz counter to 77 mhz > clock domain and then only sample it. > > what are the effects if i don't the sample the 50 Mhz counter and i > directly sample with 77 Mhz. > > rgds, > prav Hello, Prav. The best way is to go with gray code conversion before sampling it with 77 MHz. Vladislav
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