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In article <nvdZb.27841$A72.20220@newssvr25.news.prodigy.com>,
Martin Euredjian <0_0_0_0_@pacbell.net> wrote:
>Jon Harris wrote:
>
>> Ctrl-End. I guess it's 2 key strokes, and you still have to click within
>> the message, though Tab will also move the focus from the tree view to the
>> preview pane.
>
>If focus is in the preview pane just "End" will get you to the bottom.
>
>Sorry for the off-topic nature of this. I scan-through and read hundreds of
>emails and newsgroup posts per day and just a few extra keystrokes can be a
>pain in the you-know-what.
Bottom posting is bad. It lures Windows Lusers into not snipping anything.
If a post doesn't fit on a screen (this one does) you are supposed to
warn [LONG] in the subject line.
What is a pain to you is not bottom posting but the people that are
in the habit of not snipping.
<SNIP>
--
Albert van der Horst,Oranjestr 8,3511 RA UTRECHT,THE NETHERLANDS
One man-hour to invent,
One man-week to implement,
One lawyer-year to patent.
Article: 66501I have read several posts here about the difficulties to get Spartan 3 parts in small quantities. Is it realistic to start a project using spartan 3 (actually the XC3S50 in the VQ100 package is what I probably want to use) when I only need small quantities - starting with getting some 10 samples, in full production lets say 100 to 500 pieces per year? Thanks for opinions, ThomasArticle: 66502
Hi ... Xilinx still claims in various documents that you could use RocketIOs for Serial ATA. Half a year ago there was the same question - the problem seems to be with the "Out-of-Bound" (OOB) message creation and detection ... has anyone found a solution yet? bye, MichaelArticle: 66503
Hello,
rickman <spamgoeshere4@yahoo.com> writes:
> Florian-Wolfgang Stock wrote:
>>
>> news@sulimma.de (Kolja Sulimma) writes:
>>
>> > Here is an implementation from 2000.
>> > http://www.sulimma.de/prak/ss00/projekte/huffman/Huffman.html
>> > It was a student project for my lab course.
>>
>> Exactly something like that I had in mind as I talked from it. The
>> Restriction with with the advance information could be circumvent by
>> dynamic generating the Lookuptable (here is the drawback, that you
>> need 2 Passes over the stuff you want to code).
>
> Isn't there a variation that generates the table on the fly? I don't
> know any details, but wouldn't they have this same problem in modem
> compression, you can only see the data once? Or do they buffer up a
> block before compressing? Back in the early days, an engineer talked to
> me about the possibility of patenting a method that worked like this.
That isnt possible. At least not with Normal Huffman Coding. With the
ZIP Alogrithm it is possible to build a dictonary on the fly, so you
need only one pass.
The Huffman coding bases on the fact that it replaces often appearing
characters with short bitstrings, seldom ones with long bitstrings. To
know which character is often/seldom you need to count it. There are
some ways you can reduce this problem - most often used is just a
precomputed dictonary. The is the distribution of an average
english text used. This works good if you want to encode normal
text (or if you know what to expect, make some distribution analysis
on some data and make your dictonary on it).
Another approach could be, to use an internal buffer from a given
size, and build just on that distribution your dictonary.
Florian
--
int m,u,e=0;float l,_,I;main(){for(;1840-e;putchar((++e>907&&942>e?61-m:u)
["\t#*fg-pa.vwCh`lwp-e+#h`lwP##mbjqloE"]^3))for(u=_=l=0;79-(m=e%80)&&
I*l+_*_<6&&26-++u;_=2*l*_+e/80*.09-1,l=I)I=l*l-_*_-2+m/27.;}
Article: 66504
John Black <black@eed.com> wrote in message news:<40356AB3.B17C8147@eed.com>...
> But I wonder how come sys_rst is assigned LVCMOS25? Note that
> ddr_feedback_clock is at different bank of sys_rst.
http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0124_77.html
says:
The default is LVTTL (except Virtex-II Pro and Virtex-II Pro X) if
no IOSTANDARD constraint is specified. The default for Virtex-II Pro
and Virtex-II Pro X is LVCMOS25.
Alan Nishioka
alann@accom.com
Article: 66505
You can also use a dynamic dictionary that uses only past history to determine
the contents. Here you would start with a default dictionary, and over time
new entries for frequently occuring phrases would replace ones in the
dictionary that are used less frequently. The first occurrences of such
phrases in the text won't get replaced (unless that phrase is already in the
dictionary), but once enough of them occur any subsequent ones do get
replaced.
Florian-Wolfgang Stock wrote:
> Hello,
>
> rickman <spamgoeshere4@yahoo.com> writes:
>
> > Florian-Wolfgang Stock wrote:
> >>
> >> news@sulimma.de (Kolja Sulimma) writes:
> >>
> >> > Here is an implementation from 2000.
> >> > http://www.sulimma.de/prak/ss00/projekte/huffman/Huffman.html
> >> > It was a student project for my lab course.
> >>
> >> Exactly something like that I had in mind as I talked from it. The
> >> Restriction with with the advance information could be circumvent by
> >> dynamic generating the Lookuptable (here is the drawback, that you
> >> need 2 Passes over the stuff you want to code).
> >
> > Isn't there a variation that generates the table on the fly? I don't
> > know any details, but wouldn't they have this same problem in modem
> > compression, you can only see the data once? Or do they buffer up a
> > block before compressing? Back in the early days, an engineer talked to
> > me about the possibility of patenting a method that worked like this.
>
> That isnt possible. At least not with Normal Huffman Coding. With the
> ZIP Alogrithm it is possible to build a dictonary on the fly, so you
> need only one pass.
> The Huffman coding bases on the fact that it replaces often appearing
> characters with short bitstrings, seldom ones with long bitstrings. To
> know which character is often/seldom you need to count it. There are
> some ways you can reduce this problem - most often used is just a
> precomputed dictonary. The is the distribution of an average
> english text used. This works good if you want to encode normal
> text (or if you know what to expect, make some distribution analysis
> on some data and make your dictonary on it).
>
> Another approach could be, to use an internal buffer from a given
> size, and build just on that distribution your dictonary.
>
> Florian
> --
> int m,u,e=0;float l,_,I;main(){for(;1840-e;putchar((++e>907&&942>e?61-m:u)
> ["\t#*fg-pa.vwCh`lwp-e+#h`lwP##mbjqloE"]^3))for(u=_=l=0;79-(m=e%80)&&
> I*l+_*_<6&&26-++u;_=2*l*_+e/80*.09-1,l=I)I=l*l-_*_-2+m/27.;}
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 66506
It'll do a full reset long before it corrupts individual cells. The voltage
range is pretty wide, so this really should not be a concern with a proper
power supply.
Jeff wrote:
> Just wondering...how susceptible are these RAM based FPGA devices to power
> supply transients, brownouts, etc? I am looking on Altera's website and
> have not found much yet.
>
> Thanks,
>
> Jeff
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 66507
Depends on whether you want to pay for it or not...
Tracy wrote:
> Hi,
> I was wondering if anyone had the VHDL code for an array divider
> (16-bit). I can't seem to find any help on this on the web, and need
> it as a component in my design.
>
> Any help would be appreicated
>
> Thanks
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 66508Hello all, We are developing some design in FPGA XC2V2000, did not decide regarding the speed grade yet. The design is simple, except the fact that it has many clocks (more than 16), as a result of many interfaces, some of them NCO-generated, some are slow, and some are fast. So, i have two questions. Question #1: Say, i have a number of interfaces, which give me nothing but clock and serial data. The corresponding clock is used for only one purpose: writing this serial data into FIFO; that's all. Can i put this clock on a global I/O (not global clock) pin and simply direct it to the closest RAM block, even if this clock is up to 52 MHz? I have done it once for slightly slower clocks in Virtex-E and it was working fine. Question #2: There are 2 high speed clocks which we must feed into the design, 2x~156 MHz and one generated internally, 160 MHz. Each one of these clocks is going to clock a simple one-hot state machine and a read FIFO port. Could you give any recommendations on speed grade (and may be different part) selection, if the approximation of resource usage is about ~30%, where about ~10% are gonna be clocked with high speed clock? It's just that I have used before Virtex-E 1000 with 50, 82 and 125 MHz (interface only), as well as XC2V6000-4 and XC2V4000-5 running at 7/19/77 (STS-N), 92 and 125 MHz (GMII). Everything was perfectly working but i am afraid that due to multiplication of FFs, the resources usage can start growing and we are not going to be able to achieve such a frequency. Sorry for long poem and thank you in advance. Sincerely, Vladislav.Article: 66509
On 20 Feb 2004 10:26:53 -0800, muravinv@advantech.ca (Vlad) wrote: > >Hello, Prav. > >The best way is to go with gray code conversion before sampling it with 77 MHz. > >Vladislav Converting to Gray code will work, although I think it's overkill. When I do this kind of thing, I use the holding register/semaphore approach mentioned by Ray. However, if you do decide to use the Gray code approach, BE CAREFUL! Yes, successive Gray codes differ by only one bit. But if you feed a binary counter into a combinatorial binary-to-Gray-code converter, you may see decoding glitches at the output of the converter when the counter increments. Take a look at the typical binary-to-excess-3-gray-code converter--which is just a bunch of XORs of successive binary bit pairs--and it's easy to see how glitches can happen. For example, the LSB of the Gray code is the XOR of binary bits 0 and 1. What happens to the Gray code LSB if the binary LSBs change from 01 to 10, or from 11 to 00? (As I write this, I'm looking at a diagram of the converter on page 5-44 of National's 1987 FAST Applications Handbook, based on material written by one Mr. P. Alfke. The man is everywhere.) There are any number of ways to get around the problem, such as using a Gray code counter in the first place, or clocking the converted value into a 50 MHz register before sampling it with the 77 MHz register. The take-home point is this: unless you've done something very clever, a binary-to-gray-code converter driven by a binary counter is not guaranteed to be glitchless, and you cannot safely sample it with an asynchronous clock. Bob Perlman Cambrian Design WorksArticle: 66510
>We are developing some design in FPGA XC2V2000, did not decide >regarding >the speed grade yet. The design is simple, except the fact that it has >many clocks (more than 16), as a result of many interfaces, some of >them NCO-generated, some are slow, and some are fast. Can you get rid of all the slow clocks by turning each rising edge into a clock-enable pulse on a fast clock? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 66511
In comp.arch rickman <spamgoeshere4@yahoo.com> wrote: > > The older Xilinx parts have small LUT based rams that have true 3 port > memory. But how they implemented it shows that you can always make a 3 > port memory from a pair of two port memories. They tied the two write > ports together so that the two RAMs always were written with the same This would also work with any ram arhicture, no? > data. But the read ports were kept separate allowing any two words to > be read at the same time. > But there are other things you can do - you can convert the lack of ports into a scheduling restriction where you get a pipeline bubble if one of the source operands is not being forwarded from a previous instruction. The other option is doubling clock cycle and having two pipelines that can pair instructions whenever there are enough ports (including forwards) - things like the right code mix and immediate argumnets (plus some help from scheduling) can make for a very nice result. There are others. -- Sander +++ Out of cheese error +++Article: 66512
I have communicated with Tal about this off-line. For those of you who may see something similar - The problem was that the EPC16 address and data lines were also connected to a microprocessor. This microprocessor was supposed to tristate the lines when a certain signal was active. Once the connection between the EPC16 and the microprocessor was physically cut, then the configuration worked. So something funny is going on with the microprocessor. The reason this is a problem is that the EPC16 has the flash die and the controller die in one package. During configuration, the controller is exercising the flash. This activity is on the flash address and data pins, which are connected to external pins. So if an external device is doing something to those pins then configuration can fail. To help future customers we will add this scenario to our Configuration Troubleshooter tool on the Altera web site. Regards, Greg Steinke gregs@altera.com Altera CorporationArticle: 66513
If you maximum serial clock is 52 MHz, and you have a 160 MHz clock
available, resynchronize the clock and data to the 160 MHz clock, then use
a synchronous edge detect on the resynchronized clock to generate a one
clock wide write enable into your fifo. Using other than a clock net to
distribute clocks opens you to all sorts of potential timing maladies, not
to mention sensitivity to the place and route solution.
>
>
> Sincerely,
> Vladislav.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 66514it seems I need to program a few 84-pin PLCC ALTERA 7128E's and 7160E's, but haven't got the "right" adapter for my programmers. Has anybody got an old Altera Programming Unit (APU) that works with these parts, including the PLCC-84 adapter, with which they'd be willing to part? Some other capable unit would be suitable as well, provided it will actually do the job. This gig won't last long, so I'd consider a reasonably priced rental. thanks, Richard ErlacherArticle: 66515
Miaz371240@austromail.at (Nicky) wrote in message news:<c7068a2e.0402180404.71afeaa@posting.google.com>... > Hello, > > I have to design a universal PCI card according to PCI spec 2.2 with > 33Mhz and 32 pins. However for several reasons I have to use a FPGA > that is not 5V but only 3.3V tolerant. Since nearly all motherboards > just offer 5V slots I have to make this card somehow 5V compliant. I > thought of using a quickswith from IDT. Is this a good idea? What are > the things I have to take care of when using this method? Are there > any other ways to make my card 5V compliant? > > thanks+regards, > Nicky Altera has published AN330: Connecting Altera 3.3-V PCI Devices to a 5-V PCI Bus. This AN describes the technique of using an IDT Quickswitch, and also addresses devices from TI, Pericom, and Fairchild. We have used this technique on the Stratix PCI Development Board to implement a universal (3.3V/5.0V) board. Not strictly compliant due to the added capacitance, but it works. You can find the AN here: http://www.altera.com/literature/an/an330.pdf You can find info on the PCI Dev Kit board here: http://www.altera.com/products/devkits/altera/kit-pci_stx.html This info includes details on how the QuickSwitches were wired up. Sincerely, Greg Steinke gregs@altera.com Altera CorporationArticle: 66516
Steve Casselman <sc.nospam@vcc.com> wrote: > > We are in the process of completing a LZ based compression core that > > is very similar to LZS, but does not violate the patents. The > > performance in a Xilinx V2Pro is expected to be on the order of 100M > > bytes/second, with a 512 byte dictionary. We expect to release this > > core for Xilinx v2/v2pro/s3 and Altera Stratix by the end of March. > > Good info Erik. How does the above performance compare to a 2 or 3 GHz 64 > bit processor? > I find this to be a very stupid - and irrelevant - question. Not only is this majorly affected by the bitness of the CPU, a 2Ghz genral purpose CPU is going to have (comapred to FPGA) very large amounts of very fast "blockram". CPUs do most things faster than FPGA-s, and that includes most kinds of compression. This doesn't mean they aren't interesting in FPGA-s or that FPGA-s couldn't do even those things alongside CPU-s - but it does reduce the number of things for which FPGA-s are practical if they are alongside CPUs. Now of course, if you are power limited then said CPU-s go missing from the picture (though not entirely - look at the performance and power needs of say VIA C3). > > Steve > > -- Sander +++ Out of cheese error +++Article: 66517
I would suggest that past history of Xilinx should be taken here you won't get any for a year after the announcement! there aren't any unless you have a spare million so don't bother asking :-) "Thomas Heller" <theller@python.net> wrote in message news:65e1twtj.fsf@python.net... > I have read several posts here about the difficulties to get Spartan 3 > parts in small quantities. > > Is it realistic to start a project using spartan 3 (actually the XC3S50 > in the VQ100 package is what I probably want to use) when I only need > small quantities - starting with getting some 10 samples, in full > production lets say 100 to 500 pieces per year? > > Thanks for opinions, > > ThomasArticle: 66518
Hey all.
I'm having a problem with transitioning to EDK 6.1 with a custom OPB
peripheral.
I started out with EDK 3.2/ISE 5.2 with a custom OPB peripheral in a
Microblaze system on a V2 with a well populated OPB bus. That system
works fine, but we have new hardware and need to transistion. I'm moving
to EDK 6.1/ISE 6.1 with a V2Pro/PPC system with the same OPB peripheral.
The new system has a PLB->OPB bridge and on the OPB bridge is 3 OPB UART
Lites and the custom OPB peripheral. The PPC is running a simple "hello
world" type program. The program runs fine without the custom core
connected. With the core connected and not accessed, the OPB bus resets
after any of the UARTS tries to spit out more than 16 characters at a time.
The custom core started out using opb_ipif_ssp0_v1_00_a, then I upgraded
it to v1_00_b. Both exhibited the same behavior. It isn't connected to
drive to any resets and only the OPB bus resets. Not the PLB. When I
address the peripheral with more than 16 addresses in a row or more than
16 access to the same address, there doesn't seem to be any OPB bus resets.
Is there a transition guide somewhere that I missed?
What I haven't tried/am planning to try:
1) Go back to a Microblaze system but on the V2Pro.
2) Downgrade to EDK 3.2/ISE 5.2 and use the V2Pro. (bit of a pain, this
one).
3) Port the OPB Peripheral to PLB.
I'm just trolling to make sure I didn't miss anything obvious.
Thanks!
--Carlos V.
Article: 66519ghjrtyweq@yahoo.com (Glenn Heraty) wrote in message news:<5278e2c8.0402152122.3480b3cb@posting.google.com>... > cmos_nand_gate@yahoo.com (Simon S. IBM) wrote in message news:<3520d403.0402131953.7b664fee@posting.google.com>... > > Can you provide a pointer to a good random logic verilog > > gate netlist generator? > > Such a tool does not exist. Pardon me, but, you're absolutely wrong! I have seen a handful of these tools (often used for p&r tests). In fact, I have a perl program (gateGen.pl) and a C program (genGates.c) which I'll send to you (as soon as I dig them out of my src directory). They work wonders. I even seem to remember a skill program (generateVerilog.il ???) posted to comp.lang.verilog or comp.cad.cadence a few years back (someone refresh my failing memory). The perl program was provided to me by an application engineer at Cadence who used it to generate test fixtures. It could use some work, for example, it asks you the number of pins but then splits that number in half to make half input and half output pins of names it chooses. This necessitates manual editing of the resultant verilog gate netlist to get the pins correct, but, that's generally an easy task. It does generate as many gates as you tell it, in random arrangement, all hooked up properly. The C program works fine but I hate compiling (I never was that good at it), so I use the perl program almost exclusively with a bit of vi editing of the results. I use the Cadence verilogin feature to generate, place, and route a schematic so that the nearly instantaneous DFII schematic and layout results are Assura DRC/LVS correct. I often use the Cadence design kit at 180nm (I hear they have a new kit at 90 and another at 65nm) which contains plenty of standard cells, LEF, TLF, CDL, EDIF symbols, Pcells, DRC/LVS/RCX rules, etc. for my purposes. Let the group know how my two programs work for you. tenlayermatalArticle: 66520
On Fri, 20 Feb 2004 18:33:12 -0500, Ray Andraka wrote: > If you maximum serial clock is 52 MHz, and you have a 160 MHz clock > available, resynchronize the clock and data to the 160 MHz clock, then use > a synchronous edge detect on the resynchronized clock to generate a one > clock wide write enable into your fifo. Using other than a clock net to > distribute clocks opens you to all sorts of potential timing maladies, not > to mention sensitivity to the place and route solution. > >> >> >> Sincerely, >> Vladislav. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 There is a maximum skew constraint that can be applied to a clock signal which makes it possible to use a clock that's not driven by a clock buffer. Here is an example, NET "ddr_interface_1_ddr_fifo_1/wr_stb" USELOWSKEWLINES; NET "ddr_interface_1_ddr_fifo_1/wr_stb" MAXSKEW=330 ps; Also 52Mhz is slow enough that you can use both edges of the clock which would allow you to alternate negative edge stages with positive edge stages which will allow you to get away with a lot of clock skew. Generally you want to limit the use of non-clock buffer clocks to things like the input side of async FIFOs. The FIFOs can be used to transition between the external clock domains and your master clock domain.Article: 66521
Sander Vesik wrote: > > Steve Casselman <sc.nospam@vcc.com> wrote: > > > We are in the process of completing a LZ based compression core that > > > is very similar to LZS, but does not violate the patents. The > > > performance in a Xilinx V2Pro is expected to be on the order of 100M > > > bytes/second, with a 512 byte dictionary. We expect to release this > > > core for Xilinx v2/v2pro/s3 and Altera Stratix by the end of March. > > > > Good info Erik. How does the above performance compare to a 2 or 3 GHz 64 > > bit processor? > > > > I find this to be a very stupid - and irrelevant - question. Not only is > this majorly affected by the bitness of the CPU, a 2Ghz genral purpose > CPU is going to have (comapred to FPGA) very large amounts of very fast > "blockram". CPUs do most things faster than FPGA-s, and that includes > most kinds of compression. This doesn't mean they aren't interesting > in FPGA-s or that FPGA-s couldn't do even those things alongside CPU-s > - but it does reduce the number of things for which FPGA-s are practical > if they are alongside CPUs. > > Now of course, if you are power limited then said CPU-s go missing from > the picture (though not entirely - look at the performance and power needs > of say VIA C3). Your comments seem odd. You have no understanding of why Steve was asking the question. So how can you presume to judge it to be "stupid"? Your analysis is just one way of looking at the comparison. If nothing else, perhaps he wanted the comparison just as a way of judging the speed in less technical terms, for presentation to management, for example. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66522
The max current rating for Vcore, Vaux and vcco are 2A so you can use any power supply with regulated 5v that has less current rating less than 2A Ram "Jianyong Niu" <cop00jn@shef.ac.uk> wrote in message news:<c14qna$32t$1@hermes.shef.ac.uk>... > Anybody knows the specs of the power supply for the Xilinx HW-AFX-FF1152-300 > board? The mannual doesn't provide information that how much current > consumed for the 5V power connected to the powr brick. > > JY.Article: 66523
Albert van der Horst wrote: > Where the 6502 is the nicest > true 8 bit processor, Rockwell's R65F11 was a nice 6502 + Forth chip. I still have a dozen or so wire-wrapped R65F11 boards in the garage somewhere. I built them back around '85 for a light-industrial robot arm I designed as well. One processor per axis. Hardware (as in wire-wrapped 'HC parts) PWM. An additional processor for supervision and yet another to communicate with a PC/programming console. That was a fun project. Today you could probably stuff all of into a single FPGA. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 66524
>Is it realistic to start a project using spartan 3 (actually the XC3S50 >in the VQ100 package is what I probably want to use) when I only need >small quantities - starting with getting some 10 samples, in full >production lets say 100 to 500 pieces per year? Where would you buy them? What do they say? Can you get samples now? Are there any features on the Spartan 3 that you absolutely need? (Can you use some other chip?) What are the costs of alternatives? What are the costs of not being able to get the chips when you need them? How long is it going to take you to do the design? (When do you absolutely need the samples?) Can you work on the design with two plans in mind and make the choice a month or two from now? My rule of thumb is to not design in a chip unless I have parts in hand or a distributor has stock that I'm sure I can get. If an interesting chip has some features that would make a project a lot better (or even possible), then you have to decide if you want to stick your neck out. Do you like fighting with not-quite-debugged tools? Do you have good contacts at the vendor? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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