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What is avaialbe in terms of 10 GigE/FPGA demoboards? Are there any early/ES V2Pro-X demoboards? Likewise, suitable MAC cores for the V2PRo-X? Thanks. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 66126
Thank you for your reply Mr. Alfke. Your project does sound very interesting. I think that what I'm looking for is way too much simpler than that. 1 Hz granularity would be very nice, but I could work with 1Mhz steps ok. At this point I really just need clocks ~60Mhz, ~100Mhz and 150Mhz, but having some -+ range arround these frequencies would help me a lot too. Ideally I could use the PLL core on the FPGA to input a fixed frequency clock (150Mhz) and have it output the frequencies I need (~60, ~100, ~150 MHz) -- one at a time, not all three at the same time, I would select which one through internal logic or JTAG. This ouput clock is the one driving my whole FPGA logic inside. I've been having a hard time understanding the usage of the PLL component in ACTEL and the documentation is not really helping me much. So, I'm open to suggestions, while I keep trying to even get the PLL core to synthezise. I'll keep an eye on Xilinx's magazine for your published project because it does sound interesting. Thanks again, David.Article: 66127
Today I was playing with the Xilinx FPGA Editor tool, trying to learn a little about manual P&R, in case I someday need that skill. I've had some luck, but it seems that what I need to know (when I'm selecting wires for a manual route) is which pins on a switch box can be connected. Do you just have to guess, or can that info be displayed somehow? Or maybe there is some pattern to the switch box innards that I don't understand? Also, the Help file is a bit terse. Are there tutorials, app notes, resources for self-study on operating this tool? Thanks, Barry BrownArticle: 66128
I was trying to load data values in the 8Mb SDRAM of the xsa-50 board. Can someone please let me know how I can do that ?Article: 66129
Is http://www.parallax.com/detail.asp?product_id=60002 a sensible thing to buy as an introduction to working with FPGAs? If not, can you recommend anything else at the same kind of price with no-charge development tools? The parallax board seems to be reasonably priced, has a Stratix core so you get the DSP components and the large memories, lots of header pins to connect to externals (DRAM is presumably impractical on a breadboard, for signal-integrity reasons and the difficulty of putting 184-pin sockets on a breadboard if nothing else, but I can't see why SRAM and an ADC or DAC wouldn't work). Is it at all conceivable to get VGA out of something like that, or would the signals degrade hopelessly on their way from the headers to the 15-pin plug for the monitor? TomArticle: 66130
11C90, 10/11 ECL variable modulus prescaler, memories of the early 'seventies...It's amazing that we could build frequency synthesizers running close to a GHz at that time. Lots of power though, and tricky pc-board layout. Now it's so much more integrated, and one can easily recover from design mistakes. I love FPGAs ! The trouble with a fast front-end in our FPGAs is that almost everything has gotten much faster ( and more sophisticated ) in the past 5 years, but the raw toggle frequency of a LUT+flip-flop has not doubled from the 400 MHz we could do 5years ago in XC4000XL. The flip-flop is much faster, but the routing, although flexible, is less direct. That's why I have given up doing it that way. The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means 1.5 GHz. And there is an easy way to bypass lots of stuff, and represent 20 incoming bits in parallel. The rest is just design at 150 MHz. Not difficult. Anybody need a counter with resolution between 1.5 and 5 GHz ? Peter Alfke ================================= Jim Granville wrote: > > Peter Alfke wrote: > > Frequency counter is the next project. Since we have case, power supply, > > display and all the mechanical trivia established, it is easy to build a > > separate frequency counter, 1 Hz to 1.5 GHz with 9 digits of display. > > Time base oscillator promises < 3 ppm (Maxim). > > The "reciprocal" concept made it into a Xilinx "UltraController" > > presentation and demo. > > I will use the MultiGigabit Transceiver for the input. 3 Gbps = 1.5 MHz. > > I could use the newest Virtex-II ProX which is 3 times faster, but I do > > not see so much demand for a 5 GHz input resolution (LVDS). Gettinga > > bit esoteric, but the chip can do it... > > Keep you posted. > > Thanks, > Will this fit into your 'small spartan 3', alongside the Synth ? > Can you feed the 1.5GHz into a flip flop / ring counter reliably ? > What about Fmax of a variable modulus divider 1st stage ? > (was it the 11C90 (?) from fairchild ?) > > -jgArticle: 66131
If you actually click on the "circle" where the route terminates at the switchbox, it will show you what connections are posssible. The lines in yellow indicate forward signal paths (i.e. places you can go from where you clicked). The lines in olive green indicate the opposite (i.e. places from which you could arrive at the point you clicked). Hope that helps, Eric Barry Brown wrote: > > Today I was playing with the Xilinx FPGA Editor tool, trying to learn a > little about manual P&R, in case I someday need that skill. I've had some > luck, but it seems that what I need to know (when I'm selecting wires for a > manual route) is which pins on a switch box can be connected. Do you just > have to guess, or can that info be displayed somehow? Or maybe there is > some pattern to the switch box innards that I don't understand? > > Also, the Help file is a bit terse. Are there tutorials, app notes, > resources for self-study on operating this tool? > > Thanks, > Barry BrownArticle: 66132
Let me put in a plug for the Digital Clock Manager in Virtex-II. It can take in any frequency between 1MHz and >300 MHz, and simultaneously multiply and divide it by two numbers in the range of 1...32. (Output frequency must be >24 MHz, though). You can do 200 MHz times 15, divided by 19 if you feel like it. The fact that 200 MHz times 15 is very high does not matter, the DCM does the mathematical manipulation without going to GHz... So you can generate your frequencies from many different input sources, but only one frequency per DCM. You can reprogram the DCM on the fly, but it is somewhat complicated in today's circuits. Peter Alfke ================= dave wrote: > > Thank you for your reply Mr. Alfke. > > Your project does sound very interesting. I think that what I'm > looking for is way too much simpler than that. 1 Hz granularity would > be very nice, but I could work with 1Mhz steps ok. At this point I > really just need clocks ~60Mhz, ~100Mhz and 150Mhz, but having some -+ > range arround these frequencies would help me a lot too. > > Ideally I could use the PLL core on the FPGA to input a fixed > frequency clock (150Mhz) and have it output the frequencies I need > (~60, ~100, ~150 MHz) -- one at a time, not all three at the same > time, I would select which one through internal logic or JTAG. This > ouput clock is the one driving my whole FPGA logic inside. > > I've been having a hard time understanding the usage of the PLL > component in ACTEL and the documentation is not really helping me > much. So, I'm open to suggestions, while I keep trying to even get the > PLL core to synthezise. > > I'll keep an eye on Xilinx's magazine for your published project > because it does sound interesting. > > Thanks again, > > David.Article: 66133
http://www.xess.com/ Has some very nice inexpensive platforms. These are used for universities, colleges, and schools. They are inexpensive enough that a student can buy a simple one for about the price of a textbook. Austin Thomas Womack wrote: > Is http://www.parallax.com/detail.asp?product_id=60002 a sensible > thing to buy as an introduction to working with FPGAs? If not, can > you recommend anything else at the same kind of price with no-charge > development tools? > > The parallax board seems to be reasonably priced, has a Stratix core > so you get the DSP components and the large memories, lots of header > pins to connect to externals (DRAM is presumably impractical on a > breadboard, for signal-integrity reasons and the difficulty of putting > 184-pin sockets on a breadboard if nothing else, but I can't see why > SRAM and an ADC or DAC wouldn't work). > > Is it at all conceivable to get VGA out of something like that, or > would the signals degrade hopelessly on their way from the headers > to the 15-pin plug for the monitor? > > TomArticle: 66134
Peter Alfke wrote: <snip> > > The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means > 1.5 GHz. What does a Spartan 3 allow ? > And there is an easy way to bypass lots of stuff, and represent 20 > incoming bits in parallel. The rest is just design at 150 MHz. Not difficult. How do you use a Ser.Des as a freq divider/counter ? > > Anybody need a counter with resolution between 1.5 and 5 GHz ? Just to give you a target, to fully challenge the grey matter, :) this company offers 10 digits/second ($2K), and 12 digits/second models($3K). http://we.home.agilent.com/cgi-bin/bvpub/agilent/Product/cp_Product.jsp?NAV_ID=-11154.0.00&LANGUAGE_CODE=eng&COUNTRY_CODE=ZZ 8 digits / second is realively easy, but 10/12 are much more challenging... -jgArticle: 66135
Jim, The DCM has a divide by two input prescalar. I was able to get the clock in to the prescalar at 1.15 GHz, which then gets divided by two quite nicely. This was LVDS input, with everything just right to drive the input (as reflections, matching, etc. becomes really tricky at GHz speeds, so simulations and matching stubs and tricks becomes necessary, but a Mini-Circuits -> 6 GHz amplifier is about $1.50, so the front end is challenging, but not expensive). Need a differential balun, etc. Looks more like a microwave LNA than a clock input to an FPGA.....the same techniqies would get applied to drive a 2vp2 MGT receiver as well, but the SI is a lot easier, as the MGT is designed for 3.125 Mb/s rates, wheras the clock inputs are not designed for GHz frequencies (because the clock trees don't work there). Peter's comment about 4K is true: a hand placed route from an input pin to the nearest CLB FF can toggle (divide by two) up to about 1 Ghz in Virtex II, or II Pro, or S3. It is just tricky because you have to find the shortest and best path. How many people need GHz divide by capability? Would it be nice to have a 10GHz prescalar built into some pins? What would you use it for? I am afraid it would be too much trouble for too little business. Austin Jim Granville wrote: > Peter Alfke wrote: > <snip> > >> >> The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means >> 1.5 GHz. > > > What does a Spartan 3 allow ? > >> And there is an easy way to bypass lots of stuff, and represent 20 >> incoming bits in parallel. The rest is just design at 150 MHz. Not >> difficult. > > > How do you use a Ser.Des as a freq divider/counter ? > >> >> Anybody need a counter with resolution between 1.5 and 5 GHz ? > > > Just to give you a target, to fully challenge the grey matter, :) > this company offers 10 digits/second ($2K), and 12 digits/second > models($3K). > > http://we.home.agilent.com/cgi-bin/bvpub/agilent/Product/cp_Product.jsp?NAV_ID=-11154.0.00&LANGUAGE_CODE=eng&COUNTRY_CODE=ZZ > > > 8 digits / second is realively easy, but 10/12 are much more > challenging... > > -jg >Article: 66136
Barry Brown wrote: > Today I was playing with the Xilinx FPGA Editor tool, trying to learn a > little about manual P&R, in case I someday need that skill. I've had some > luck, but it seems that what I need to know (when I'm selecting wires for a > manual route) is which pins on a switch box can be connected. Do you just > have to guess, or can that info be displayed somehow? Or maybe there is > some pattern to the switch box innards that I don't understand? The switch box detail can be displayed - it's one of the icons in the toolbar. If you zoom in close enough, then click on one of the ports of the switch box (the little diamonds around the edge), it will show the internal connections from that port. They aren't all displayed simultaneously, since they are so massively connected it would be a completely unintelligible mess. Even just showing one source port at a time, it's pretty hard to follow. Regards, JohnArticle: 66137
Jim Granville wrote: > > Peter Alfke wrote: > <snip> > > > > The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means > > 1.5 GHz. > > What does a Spartan 3 allow ? Nothing, no MGTs. Flip-flops counting perhaps at 500 MH ( with care, remember Spartan emphasizes low cost, not high speed). > > > And there is an easy way to bypass lots of stuff, and represent 20 > > incoming bits in parallel. The rest is just design at 150 MHz. Not difficult. > > How do you use a Ser.Des as a freq divider/counter ? Just as a oversampled input, generating a parallel 10 or 20 bit word, then processing this as data ( accumulator, etc) > > > > > Anybody need a counter with resolution between 1.5 and 5 GHz ? > > Just to give you a target, to fully challenge the grey matter, :) > this company offers 10 digits/second ($2K), and 12 digits/second > models($3K). Well, I will use internal "time base" of 100 MHz for 1 sec = 8 digits. When the input signal is >100 MHz, the resolution goes up, of course. My time base is "only" 3 ppm worst case, but the Maxim oscillator can be trimmed. I have no intentions of driving Agilent out of business. They have a 65 year head start... Peter Alfke >Article: 66138
Austin Lesea wrote: > Jim, > > The DCM has a divide by two input prescalar. I was able to get the > clock in to the prescalar at 1.15 GHz, which then gets divided by two > quite nicely. <snip> > > Peter's comment about 4K is true: a hand placed route from an input pin > to the nearest CLB FF can toggle (divide by two) up to about 1 Ghz in > Virtex II, or II Pro, or S3. It is just tricky because you have to find > the shortest and best path. > > How many people need GHz divide by capability? Frequency synthesisers would be one, and precise time/phase measurements could be another. Precise time is a little more difficult, as you need to capture, but this would, of course, clock on both edges :) > Would it be nice to have a 10GHz prescalar built into some pins? Yes. Would not need to be many. > What would you use it for? See above. > I am afraid it would be too much trouble for too little business. Possibly, but consider that the resolution of a FPGA in terms of jitter, and Register Apertures are in the some picosecond region, but that currently to get a frequecy above ~500MHz (2000ps) into the fpga needs special care.. That would indicate a dedicated Ctr/Capture block, like the MGTs. -jgArticle: 66139
Thanks Eric. I did receive 2 drivers (and their source codes, after I ask) from Memec Design Services, but they only let us access the USERAPP. No provision for configuring the PCI core. I understand what you described is needed for writing the driver. But when Memec sells the PCI development board, shouldn't it cater to the need to configure PCI master? The example files are all similar to Xilinx example (ping64), including the ucf file. I am just dissappointed that we have to do these extra bits. We had assumed it will be there. Regards, LC "Eric Crabill" <eric.crabill@xilinx.com> wrote in message news:402BF6C4.D142FCD5@xilinx.com... > > Hello, > > > I figured that either BIOS or Windows configures the PCI board > > at bootup, and assigns the BAR0 etc. I am using an FPGA with the > > Xilinx PCI32 LogiCore. Hence, the Command and Status Register bit 2 > > is '0' at startup. How can I set it to '1' after startup? > > This is the responsibility of the device driver for your device. > If you don't have one, you will need to write one. You can get > the Windows 2000 DDK from Microsoft for examples of how to do it. > Alternately you can purchase a device driver development kit. I > can think of at least three vendors of such kits. > > Basically, when your driver loads, it needs to locate the hardware > and then read what's in the BARs to know what addresses it should > use to access the hardware. Also, at that time, you would want to > clear all the bits in the status regisiter, and then set whatever > bits you want in the command register. After that, your hardware > is ready to go... > > > For those of you familiar with the Xilinx PCI32 LogiCore, I've > > thought about hard setting the CFG_SELF bit to '1', which will > > fool the core to initiate master transactions. But in simulation, > > I see that the ADIO bus does not get the date from the AD bus! > > Don't do that; this signal is intended to be used only to enable > the core to perform CONFIG reads and writes to its own SELF. And > you would only want to do that if you were in some kind of an > embedded system with no host. > > > A more tedious way is to self configure the PCI core to master, > > but I am seeking an easier way. > > You still shouldn't do that, unless you are in an embedded system > with no host (or you are the host) but that isn't the case if you > are in a Windows 2000 system. > > I'm not a device driver writer (or even a programmer) and I was > able to leverage stuff in the DDK and a commercial device driver > development kit to get a driver working in Windows 2000. I took > one of the examples that was closest to what I wanted to do and > then modified it. > > Eric >Article: 66140
Peter Alfke wrote: >> Just to give you a target, to fully challenge the grey matter, :) >>this company offers 10 digits/second ($2K), and 12 digits/second >>models($3K). > > Well, I will use internal "time base" of 100 MHz for 1 sec = 8 digits. > When the input signal is >100 MHz, the resolution goes up, of course. > My time base is "only" 3 ppm worst case, but the Maxim oscillator can be trimmed. > I have no intentions of driving Agilent out of business. They have a 65 > year head start... here's another one : http://www.coherent.com.au/physical/prod_instrum_time.htm Uses a 10GHz VCO, and gives 11 digits/second. this claims 25ps single shot time interval resolve, rather ahead of Agilent's 500ps or 150ps. with some smart thinking, 25ps should be close to a Spartan 3? -jgArticle: 66141
I wonder if it is possible to synthesize on one chip VHDL and Verilog IP cores. I suppose the VHDL to Verilog or vice versa translator could be used. Ideas are welcome. Remis -- ************************************************ To reply, remove >.spam< and >.fake<Article: 66142
Can't you do that with Synplify? If not, you can always synthesize blocks of, say, VHDL, separately and then instantiate them as EDIF black boxes in the Verilog design. -Kevin "Remis Norvilis" <Norvilis.spam@charter.net.fake> wrote in message news:102of4grl3t4n38@corp.supernews.com... > I wonder if it is possible to synthesize on one chip VHDL and Verilog IP > cores. I suppose the VHDL to Verilog or vice versa translator could be > used. > Ideas are welcome. > > Remis > -- > > ************************************************ > To reply, remove >.spam< and >.fake<Article: 66143
"Kenneth Land" <kland1@neuralog1.com1> wrote in message news:<102nc03snlh3i67@news.supernews.com>... > If you can sqeak by with 240 pins I've got a custom 4 layer board running > Nios with SDRAM and USB 2.0 incredibly stable at 110-120 MHz. > > Stack is Signal-GND-PWR-Signal. Made 10 with ground pours, 10 without. > Both sets function the same. I have not compared the external signals on an > analog scope, but the clocks look good, the logic analyzer looks good, and > they all work without glitch. > > If you go to CompUSA and buy a few highspeed PCI cards you'll see they're > doing their magic with only 2 layers with ground pours. > > I was originally told by the board expert the same 8-layer requirement on > our design. I talked him down to 6 and then went with 4 based on a lot of > reading, looking at examples, and applying common sense. > > I say listen to experts, but beware the advice of people who make more money > if your design is more complex. > > IMO > Ken > > "Andre" <armcc@lycos.com> wrote in message > news:ae5c06e9.0402120029.4ea5405d@posting.google.com... > > How many layers are normally needed for PCBs using low cost FPGAs ?? > > > > I've just been told by a supposed board layout expert that the 256 pin > > BGA version of a Cyclone EP1C6 would require an 8 layer board > > (apparently having the entire underside of the device covered by balls > > with no free space at the centre makes signal routing a big problem). > > > > Is this really true ?? Hi Andre, You should be able to break a 256-ball 1mm BGA in 4 routing layers and perhaps even 2 or 3 routing layers depending on the pin usage and FPGA design pinout choice. The details depend on your exact board technology, such as trace width. These are the signal layers, not including VCC and Ground planes. You may have VCCIO be different from VCCINT so you would have to take that into account. Potentially you could have a split VCC plane to cover VCCIO and VCCINT to save a layer. The center pins are VCCint power and ground so they should be connected directly to planes. Via breakouts should go out in four different directions opening a space shaped like a cross to place VCCint decoupling caps under the BGA pattern. It's hard to give a fixed answer for all circumstances as it's very dependent on both the FPGA design and the board technology that is available. Ken (above) has a good suggestion about the Q240 - actually the EP1C6 Q240 and the EP1C6 F256 both have 185 IOs, so you would not lose any IOs by going to the Q240. However the F256 does have the advantage of being much smaller, so you can choose between board cost and size. Another option to consider. Sincerely, Greg Steinke Altera Corporation gregs@altera.comArticle: 66144
Sean Durkin wrote: > John Williams wrote: > >> Hi Sean, >> >> Thanks for your response. It confirmed a few things I was starting to >> think, but it's nice to know I'm not alone! > > Us partial reconfigurators sure are a rare species. We should stick > together, or have some "RA" (Reconfigurators Anonymous) meetings some > time... :) I agree 100% Hopefully I'll be at ERSA in Las Vegas June this year, it would be good to have a commiseration/counselling session! :) >> I found the problem - I had disobeyed golden rule #465 of having a >> non-module IOB "above" a module area location... I was secretly >> hoping there might be some edge-following routing resources that would >> let me get away with it, but it seems not... > > Yeah, should've thought about that, I think that must've been what > caused it in my case, too... But I notice that this only produces errors > when you use ISE6. ISE5 routes the thing without warning, which of > course leaves you with a useless design. > > So did that solve the problem with the corrupt .NCD as well? Yes and no - I can generate a bitstream, but only if I turn off the DRC. If I leave the DRC on, it generates errors (not warnings) deep in the microblaze core, which is odd since I'm not doing anything in there.. but, I still can't open the file in fpga_editor... shrug... I had to put that aside and move onto some other stuff, i'll be back on it when i get the chance. But at least I have built a modular/partial microblaze system, so it's a proof of concept if nothing else. Cheers, JohnArticle: 66145
Hi Greg, I was thinking more in terms of SI rather than routing difficulty. In that case let me share how we handled that on only two signal layers. (We did to a split PWR plane, BTW) It was a challenge with all the pins and signals and we wound up using a routing service. The company does nothing but apply a full up SPECTRA auto-routing system as a service to others. They were so knowledgeable and helpful and the whole transaction was done by email and phone over a few days. The price was incredible and now we'll save much more than their fee every batch of boards due to the fewer number of layers. I suspect their routing experience has a bit to do with the stability of our boards as well. Email me privately if you'd like the contact info. (remove the 1's) Ken "Greg Steinke" <gregs@altera.com> wrote in message news:5c1de958.0402121904.62f8897@posting.google.com... > "Kenneth Land" <kland1@neuralog1.com1> wrote in message news:<102nc03snlh3i67@news.supernews.com>... > > If you can sqeak by with 240 pins I've got a custom 4 layer board running > > Nios with SDRAM and USB 2.0 incredibly stable at 110-120 MHz. > > > > Stack is Signal-GND-PWR-Signal. Made 10 with ground pours, 10 without. > > Both sets function the same. I have not compared the external signals on an > > analog scope, but the clocks look good, the logic analyzer looks good, and > > they all work without glitch. > > > > If you go to CompUSA and buy a few highspeed PCI cards you'll see they're > > doing their magic with only 2 layers with ground pours. > > > > I was originally told by the board expert the same 8-layer requirement on > > our design. I talked him down to 6 and then went with 4 based on a lot of > > reading, looking at examples, and applying common sense. > > > > I say listen to experts, but beware the advice of people who make more money > > if your design is more complex. > > > > IMO > > Ken > > > > "Andre" <armcc@lycos.com> wrote in message > > news:ae5c06e9.0402120029.4ea5405d@posting.google.com... > > > How many layers are normally needed for PCBs using low cost FPGAs ?? > > > > > > I've just been told by a supposed board layout expert that the 256 pin > > > BGA version of a Cyclone EP1C6 would require an 8 layer board > > > (apparently having the entire underside of the device covered by balls > > > with no free space at the centre makes signal routing a big problem). > > > > > > Is this really true ?? > > Hi Andre, > You should be able to break a 256-ball 1mm BGA in 4 routing layers and > perhaps even 2 or 3 routing layers depending on the pin usage and FPGA > design pinout choice. The details depend on your exact board > technology, such as trace width. These are the signal layers, not > including VCC and Ground planes. You may have VCCIO be different from > VCCINT so you would have to take that into account. Potentially you > could have a split VCC plane to cover VCCIO and VCCINT to save a > layer. > > The center pins are VCCint power and ground so they should be > connected directly to planes. Via breakouts should go out in four > different directions opening a space shaped like a cross to place > VCCint decoupling caps under the BGA pattern. > > It's hard to give a fixed answer for all circumstances as it's very > dependent on both the FPGA design and the board technology that is > available. > > Ken (above) has a good suggestion about the Q240 - actually the EP1C6 > Q240 and the EP1C6 F256 both have 185 IOs, so you would not lose any > IOs by going to the Q240. However the F256 does have the advantage of > being much smaller, so you can choose between board cost and size. > Another option to consider. > > Sincerely, > Greg Steinke > Altera Corporation > gregs@altera.comArticle: 66146
"Barry Brown" <barry_brown@remove_this.agilent.com> wrote in message news:<1076629663.122091@cswreg.cos.agilent.com>... > Today I was playing with the Xilinx FPGA Editor tool, trying to learn a > little about manual P&R, in case I someday need that skill. I've had some > luck, but it seems that what I need to know (when I'm selecting wires for a > manual route) is which pins on a switch box can be connected. Do you just > have to guess, or can that info be displayed somehow? Or maybe there is > some pattern to the switch box innards that I don't understand? > > Also, the Help file is a bit terse. Are there tutorials, app notes, > resources for self-study on operating this tool? > > Thanks, > Barry Brown Hi Barry, If you select a pin on a switch box (point and click)FPGA Editor will display all of the possible switch box paths to/from that pin. The editor is well documented, but there is a lot more functionality than meets the eye, so ask away. Regards, BretArticle: 66147
Hello group. We would like you to share with us your comments and opinions about a product we are planning to launch. Your feedback will be very helpful to determine the interest in this kind of product, and important to establish its development path and features (including, of course, price, so by helping us you may be helping yourself ;^) This is a low cost, low power little board (3"x2") we designed to use in our own custom control & data acquisition projects, but the concept turned out so nice and nifty that we are evaluating the possibility to commercialize it as a line product. It currently has an AT91M42800A MCU from Atmel (ARM7TDMI with an external bus), up to 1MB RAM, 1MB to 8MB Flash, integrated power supply and a Xilinx SpartanIIe FPGA (XC2S50E or XC2S100E) with a programmable clock oscillator. Expansion headers are provided for all important board signals (120, including power pins), with top and bottom stack mount capability. Most MCU and FPGA pins are shared to provide a flexible interfacing architecture. The FPGA can be used for logic interfacing, data processing, video output and LCD interface, hardware UARTs and other kind of communications, etc. We would like to introduce this first as a basic kit with all the necessary tools to get one started (core module, adapter board with serial transceivers, wiggler-like JTAG programmers, software). The board itself is a wonderful combo-kit for learning about embedded systems with the ARM architecture and FPGAs. Most of the software and applications will be provided as open source and a web site with useful information (application notes, code and FPGA cores) will be set up. An eCos profile for the board will be made available too. We also have designs for a backplane and auto-configuring add-on modules with analog and digital IOs, Ethernet interface, IrDA and RF transceivers, CompactFlash interface, etc. Our idea is to make them available once we can reinvest and verify enough demand for each kind of device. The board can be configured for 1V-3.6V input operation using an efficient step-up regulator, targeted mainly for battery powered applications. Another configuration allows not installing the FPGA and using a cheap LDO regulator for cost-sensitive applications where the FPGA is not necessary and power efficiency is not of concern. You can take a look at some pre-production kit items at http://www.embedded.cl/gallery/ARMermelator In particular, you would help us a lot with your answers and suggestions for the following: - How much will you be willing to pay for a kit like this. How much for core boards in quantities? - Do you think the FPGA configuration (ie, FPGA present on the board) will be useful for you? Would you choose this board over other similar products because of its FPGA functionality? - Concerning the kit, do you think a base board with integrated programmers, serial transceivers and prototyping area would be more useful to you than an adapter board and separated programmers? - What kind of applications and solutions to your needs do you envision using a board like this? - Without knowing further details, your overall impression about this product. Well, thank you very much in advance. Sorry for the long post and sorry if the content of this post sounded too much like marketing instead of technical matters -- we are not trying to offend anyone but to help us all. Warmest regards. -- PabloBleyerKocik / pbleyer /"Simplicity is prerequisite for reliability." @embedded.cl / -- Edsger Wybe DijkstraArticle: 66148
Steve wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<402ABE46.861C779A@yahoo.com>... > > > Hey Steve, why don't you get off the soapbox. What you are doing is not > > getting you anywhere and is starting to tick me off. Until you give a > > call to your distributor and *ask* what price you can get, I don't want > > to listen to your rants. > > So far in this thread I've been accused of not understanding > economics, pricing or capitalism; seemingly just because I've had the > audacity to question Xilinx's low quantity prices. Basically, if > they're going to patronise me then I'm not going to just sit here > quietly and take it. You are not making any sense. By definition X and A have an oligopoly. So what is your point? Your questions have no point. Your statments are about the obvious. You are not telling anyone here anything they don't already know. You are just acting like a spoiled brat throwing a tantrum because he can't have dessert. Are you just trolling or do you have a point? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66149
he, I may have a solution http://www.fpga4fun.com/shop_I2CPLL.html Did this project just a few weeks back... Jean
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