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rickman <spamgoeshere4@yahoo.com> wrote in message news:<40390862.222DCE7F@yahoo.com>... > I am trying to decide if I should use a chip wide reset on an Altera > ACEX 1K part. In reading how this works, it appears that the FFs are > actually only able to be reset or "loaded with a '1'" using an async > signal. So if I am not using a signal to preset a FF in my design, but > just want the power on/chip wide reset state to be a '1', how would I > code that in VHDL? Is this like the Xilinx tools where you code in a > chip wide reset and then drive it with a special module? Or do I > explicitly drive it from the chip wide reset pin and the tool figures it > out? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX Rick, When the ACEX device is initialized after configuration, or when you assert the Chip Wide Reset, the FFs are all set to 0. There are two ways of achieving your goal of having an FF power up to 1. 1. You can code the VHDL so that you end up with a NOT gate before the D of the FF, and another NOT gate after the Q of the FF. Any logic that the FF drives would actually be driven by the NOT gate in the HDL. When the FF powers up at 0, it will appear as 1 by the rest of the logic. But in normal operation, the double-negation will have no effect. You'll have to be careful with simulation however, since the FF's value will be the opposite of what you expect. This works in MAX+PLUS II or Quartus II as it's simply an HDL code. 2. Quartus II has an ACF setting called "POWER_UP_LEVEL". You can set this to HIGH or LOW for an individual register. You can apply this setting using the Assignment Editor or in the HDL using the "altera_attribute" syntax. Here's an example: signal my_reg : std_logic attribute altera_attribute : string; attribute altera_attribute of my_reg : signal is "POWER_UP_LEVEL=HIGH"; Either approach works - just depends on whether you would rather modify the HDL or change assignments. Sincerely, Greg Steinke gregs@altera.com Altera CorporationArticle: 66651
BEAUTIFUL!!! Thanks Jonathan! This is exactly what I was looking for! I appreciate your response! I'll move my further discussions to comp.lang.verilog. Thanks again! Kate "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:c1g15b$8rt$1$8302bc10@news.demon.co.uk... > "Kate Smith" <lsdjf@dlfjc.om> wrote in message > news:bNidnZqo8vXL4KbdRVn-uQ@comcast.com... > > The following code is my first Verilog program. It's running at 25MHz and > > that's what the counter is for. I'm trying to accomplish the same thing > by > > shifting bits instead of hard coding the output in case statements. I > tried > > LED<=LED>>1 to no avail. Any comments and suggestions are appreciated! > > > module ledbounce(clk, LED); > > input clk; > > output [3:0] LED; > > > > reg [19:0] cnt1; > > reg [2:0] cnt2; > > reg a, b, c, d; > > wire cnt1max = (cnt1==1000000); > > [snip code] > > First, it's worth noting that you are more likely to get an > answer on comp.lang.verilog than here - although many of us > read both groups. > > Second, you can't manipulate output LED as you tried, because > it's a wire, not a reg - you declared it correctly as an > output, but outputs are wires by default. You need to do the > shift operations on the register you've represented as > a,b,c,d. > > Third, although I can see the sense in your counter arrangement, > the second counter is not really necessary - you could use the > "bouncing bit" 4-bit register as its own counter. > > Fourth, you REALLY need to think about reset strategy - > in many FPGA and CPLD devices, flip-flops start life with > zero in them, but it's a bad idea to rely on this. > > So, here's my suggestion: > > (1) Throw away your cnt2 logic and registers a,b,c,d. > (2) Make the bouncing-bit counter like this: > > reg LeftNotRight; > reg [3:0] LED; // This in addition to the output declaration > ... > always @(posedge clk or posedge reset) > if (reset) begin > LED <= 1; > LeftNotRight <= 1; > end else if (cnt1max) begin > if (LeftNotRight) begin // Going left > if (LED[3]) > LeftNotRight <= 0; > else > LED <= LED << 1; > end else begin // Going right > if (LED[0]) > LeftNotRight <= 1; > else > LED <= LED >> 1; > end > end > > For lots of extra credit, see if you can work out > a) what happens if the LED register gets more than > one of its bits set, for any reason; > b) what happens if the LED register becomes zero > for any reason, and what you might do to fix it > > :-) > > -- > > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > > >Article: 66652
Hi, > The design in question is a custom CardBus module, > for which we are considering a Cyclone FPGA from > Altera. The functionality of the module is not too > complex. Beside the bus-related requirements > themselves (CIS, ConfigSpace), we also need a > FIFO. The bigger the FIFO, the better. Is Cyclone > an appropriate choice for this application, or are > there better solutions out there? I am sure you could implement this in many different devices. Your job is to pick the best one for your design. > Another issue is the time necessary for the FPGA > to load its configuration, which can be as high > as a couple of seconds. PCI 2.3, using 3.3v I/O, is very similar to Cardbus. For example, you can use the Xilinx PCI LogiCORE to implement a Cardbus design. I have seen it done. A significant difference between Cardbus and PCI is that PCI provides a 100 ms time window for you to get the device in order before reset deasserts, and then some additional time (large number of cycles) before the first allowed configuration access. Cardbus does not provide as much time. Your concern is legitimate, however you can certainly take steps to minimize any potential issue. Use a parallel configuration mode if available, and in any case use a high configuration clock rate. Use an FPGA with a small bitstream, like a 2s30. You can implement the Xilinx PCI LogiCORE in a 2s30, it has embedded memory with which you could implement a FIFO. > If not, I am afraid the only choice is to try with the > flash-based FPGAs from Actel, which does not come in too > handy. I don't like the idea of paying for the Actel > software, which is not even that good like ISE or Quartus. > And the Actel parts seem to be much too expensive and > difficult to program. If you want to write your own Cardbus interface, you might consider usinig a moderate sized CPLD, instead of an FPGA, but in this case you'll probably end up with an external memory device to serve as your FIFO. EricArticle: 66653
> How can I connect l_sram_data_out and l_sram_data_in
> in a appropriate way to the bidirectional bus?
My goal was to make Xilinx ISE use all the FF in the io-blocks ...
one ff for data_in, for the tristate-buffer and for data_out
the following has to be placed in the toplevel and was the
only way to make ISE do what I wanted ...
(Options: keep_hierarchy=true, use io-buffers=all/auto... can't
remember)
if clk'event and clk = 1 then
l_sram_data_in <= Sram_data;
if OE_bar = '1' then
Sram_data <= l_sram_data_out;
else
Sram_data <= (OTHERS => 'Z');
end if;
end if;
yes ... this produces latency ... but its synchronous
bye,
Michael
Article: 66654If anybody wants to look upany issued patents, just go to http://appft1.uspto.gov/netahtml/PTO/search-bool.html Peter Alfke, Xilinx ================== MaEs wrote: > > > > > > > Steve Casselman wrote: > > > > The earliest Xilinx patent is 4,870,302 Feb 19 1988. So it expires > next year > > > > > > > > Steve > > > > Is this the famous Freeman patent? > > > > > > > > Likely, although one company A. might refer to it as 'infamous' :) :) > > US4870302: > > "Configurable electrical circuit having configurable logic elements and > configurable interconnects" > > Inventor: Ross H. Freeman, San Jose, Calif. > > Assignee: Xilinx, Inc., San Jose, Calif.Article: 66655
Hello There is also an english version of the description and contact form page available by now. The title is "Free VHDL implementation of a PCI Brigde using Xilinx Spartan-IIE FPGA" for the design description page and "Design reuse of the free VHDL PCI Bridge Core" for the actual contact form. There is no direct download, but the source will be sent as attachement during a short email exchange. http://www.infotech.tu-chemnitz.de/~knoll/vhdl_pci_bridge/ http://www.infotech.tu-chemnitz.de/~knoll/vhdl_pci_bridge/kontakt.php Cheers, Thomas -- http://www.infotech.tu-chemnitz.de/~knoll/Article: 66656
Vadim Rusu <vrusu@hep.uchicago.edu> wrote in message news:<c1fr6u$6ra$1@info4.fnal.gov>... > Hi, > > When debugging a design one can assign inside the VHDL code debug pins. > However, if after compiling and everything I decide to look for some > other signal of choice (that are not pins), in the simulation, QUARTUS > will give me a list of uninteligible names. Is there any way around > this? Signal Tap seems to work only with a physical FPGA via JTAG. > > Thanks > Vadim Hi Vadim, This is a cut and paste from an earlier post. To preserve a combinatorial node through synthesis, place and route, you should do one of the following: a) If it is a BDF (schematic file) or TDF (AHDL file), feed the signal that you are interested in observing into a LCELL primitive, and give the LCELL primitive an interesting name, so that you can find it when you choose the Post Compilation filter in the node finder. You should feed the output of the LCELL to where the signal wof interes was previously connected. b) If you are using VHDL or Verilog, consider using the keep pragma/keyword. Its usage is described in the online help. Search for "keep". The Verilog help panel is shown below: ------------------- keep usage in Verilog ----------------------------------- A Verilog HDL language directive that directs Analysis & Synthesis to keep a particular wire intact. You can use this language directive to keep a combinational logic node so you can observe the node during simulation or with the SignalTap® II Logic Analyzer. You cannot use this language directive for nodes that have no fan-out. To use the keep language directive, you can specify the keep language directive in a comment that is on the same line as the register you want Analysis & Synthesis to preserve. In the comment, precede the language directive with the synthesis keyword. For example, in the following code, the comment /* synthesis preserve */ directs Analysis & Synthesis to not minimize the keep_wire register: wire keep_wire /* synthesis keep */; ------------------------------------------------------------------------------- You would search for keep_wire in the Mode Finder. Hope this helps. - Subroto Datta Altera Corp.Article: 66657
Sander Vesik <sander@haldjas.folklore.ee> wrote in message news:<1077324833.209845@haldjas.folklore.ee>...
> Steve Casselman <sc.nospam@vcc.com> wrote:
> > > We are in the process of completing a LZ based compression core that
> > > is very similar to LZS, but does not violate the patents. The
> > > performance in a Xilinx V2Pro is expected to be on the order of 100M
> > > bytes/second, with a 512 byte dictionary. We expect to release this
> > > core for Xilinx v2/v2pro/s3 and Altera Stratix by the end of March.
> >
> > Good info Erik. How does the above performance compare to a 2 or 3 GHz 64
> > bit processor?
> >
Steve,
We have not run optimized the reference encoder or run it on such a
fast machine yet. But I can make a guess as to the perfomance based
on the instruction flow. Best case one might get 2-3M bytes/second
throughput. I am being very generous with the estimate, unless I have
overlooked an optimization.
I am generally wary to give performance numbers for our reference
encoders, as we generally write them to prove an algorithm "works",
i.e. for test bench data generation and verification of compression
ratios. It would be rather misleading for us to say "our hardware
goes x-times faster than our software implementation" as we invest a
great deal of effort in the hardware optimizations and the algorithms,
and almost none in the software beyond demonstrating the correctness
of the implementation and algorithm. Our reference encoder probably
won't get anywhere near 2MB/sec.
Regards,
Erik Widding.
P.S. I grouped this response with one below, as they are closely
related.
*******************************************
Sander,
> I find this to be a very stupid - and irrelevant - question.
Actually I found Steve's question to be right on target, and quite
typical of those asked by our customers. I had not yet had a chance
to reply. As for the rest of your comments... just about everything
in your post is incorrect.
> Not only is
> this majorly affected by the bitness of the CPU, a 2Ghz genral purpose
> CPU is going to have (comapred to FPGA) very large amounts of very fast
> "blockram".
Most of these algorithms deal with memory access in a very
predetermined fashion globally, with random access on a much more
localized basis. So the lack of large amounts of blockram does not
benefit the processor implementation. If memory is needed, one
generally adds SDRAM next to the FPGA.
> CPUs do most things faster than FPGA-s, and that includes
> most kinds of compression.
If this were true the compression engines for tape drives would not be
located in the drive, but rather run on the host processors
themselves. As an example, for minimally compressible data in our
LZ-derivative (or LZS for that matter) with a 512 byte
history-buffer/dictionary there will be 512 comparisons and 512
address increments, requiring 1024 instructions minimum. In an FPGA
these 512 comparisons can be executed in a single clock period. The
FPGA clock rate may only be 100MHz to the processors 3GHz, or a ratio
of 1:30, whereas the FPGA only requires one clock cycle to the
processors 1000+.
I do not know of a single compression algorithm that will run faster
on a general purpose processor than it will run on an FPGA with
external SDRAM. Many won't even need the external memory to beat the
processor. Assume both implementations are done by experts in the
respective areas.
Feel free to propose an algorithm where I am wrong. It has been my
experience that the hardware implementations are generally one to
three orders of magnitude faster than the software, with the
performance normalized for the cost of the respective hardware.
Regards,
Erik Widding.
---
Birger Engineering, Inc. -------------------------------- 617.695.9233
100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com
Article: 66658"Mike Nicklas" <michaeln@nospamplease.slayer.com> wrote in message news:403b1cd3$0$4101$5a6aecb4@news.aaisp.net.uk... > The problem i have is that when i set the value of the INOUT signal in > my design, the testbench does not appear to assert it as desired and the > port stays at value zero. Can it be that you are initializing this signal in the test bench as zero? Assuming the signal is std_logic try setting it to 'L' or 'Z' instead. /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca")Article: 66659
Hi, is the new ALUT architecture of stratix 2 patented ? I have looked at the US patent office but could not find such a patent. Thank you for your help.Article: 66660
Sander Vesik wrote:
>
>
> Rather heavy-handed set of restrictions, don't you think?
>
> --
> Sander
>
> +++ Out of cheese error +++
That's because the licensee is paying only $100.
If the licensee is willing to pay much more than that, that person can
use my PCI IP core in a commercial project.
Kevin Brace
Article: 66661Lenz, I am sure that they have filed for their patents. Since it takes two or more years, we will just have to wait and see what it is that gets patented. How this is any different than f5/f6/f7/f8 muxes is also at issue: have they just "renamed" an already existing architecture? Do they now achieve the same packing that is already enjoyed by others? AustinArticle: 66662
Hi David, That restriction is there for legal reasons. If what I am dealing with wasn't an IP core, there won't be such a restriction. Kevin Brace David Brown wrote: > > > How can you possibly justify this restriction? You get a chance to explain > yourself before the rants arrive, but it'd better be *very* good. > > David Brown > Norway.Article: 66663
Kevin Brace <kev0inb1rac2e@m3ail.c4om> writes: > That restriction is there for legal reasons. If what I am dealing > with wasn't an IP core, there won't be such a restriction. Now I'm curious, too. What _are_ those legal reasons, precisely? -- GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3 331E FAF8 226A D5D4 E405Article: 66664
Hi Marius, I believe it is theoretically much harder to enforce contractual obligation like prohibition of redistribution or the requirement of non-profit use if the licensee resides in a foreign country. Kevin Brace Marius Vollmer wrote: > > Kevin Brace <kev0inb1rac2e@m3ail.c4om> writes: > > > That restriction is there for legal reasons. If what I am dealing > > with wasn't an IP core, there won't be such a restriction. > > Now I'm curious, too. What _are_ those legal reasons, precisely? > > -- > GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3 331E FAF8 226A D5D4 E405Article: 66665
mike writes >Dear newsgroup, > >I am quite new to FPGAs but experienced enough in digital ASIC design (VHDL, >Verilog & stuff). Recently, we encountered some problems with the selection >of >the best FPGA for a design we are attempting. >The design in question is a custom CardBus module, >Another issue is the time necessary for the FPGA to load its configuration, >which can be as high as a couple of seconds. >within a short interval after insertion (less than 1 sec). Is there any >reliable >solution to this problem? >If not, I am afraid the only choice is to try with the flash-based FPGAs from > >Actel, which does not come in too handy. You should look at Lattice XPGA - this is an EECMOS/SRAM device - boots up <100us, no external prom needed - free tools - LSC SFAE New York/New Jersey 631-874-4968 fax 631-874-4977 michael.thomas@latticesemi.com for the latest info on Lattice products - http://www.latticesemi.com LATTICE - BRINGING THE BEST TOGETHERArticle: 66666
Thanks much Jonathan!!! Worked like a charm!!! I'll move all further discussions to comp.lang.verilog Thanks again! "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:c1g15b$8rt$1$8302bc10@news.demon.co.uk... > "Kate Smith" <lsdjf@dlfjc.om> wrote in message > news:bNidnZqo8vXL4KbdRVn-uQ@comcast.com... > > The following code is my first Verilog program. It's running at 25MHz and > > that's what the counter is for. I'm trying to accomplish the same thing > by > > shifting bits instead of hard coding the output in case statements. I > tried > > LED<=LED>>1 to no avail. Any comments and suggestions are appreciated! > > > module ledbounce(clk, LED); > > input clk; > > output [3:0] LED; > > > > reg [19:0] cnt1; > > reg [2:0] cnt2; > > reg a, b, c, d; > > wire cnt1max = (cnt1==1000000); > > [snip code] > > First, it's worth noting that you are more likely to get an > answer on comp.lang.verilog than here - although many of us > read both groups. > > Second, you can't manipulate output LED as you tried, because > it's a wire, not a reg - you declared it correctly as an > output, but outputs are wires by default. You need to do the > shift operations on the register you've represented as > a,b,c,d. > > Third, although I can see the sense in your counter arrangement, > the second counter is not really necessary - you could use the > "bouncing bit" 4-bit register as its own counter. > > Fourth, you REALLY need to think about reset strategy - > in many FPGA and CPLD devices, flip-flops start life with > zero in them, but it's a bad idea to rely on this. > > So, here's my suggestion: > > (1) Throw away your cnt2 logic and registers a,b,c,d. > (2) Make the bouncing-bit counter like this: > > reg LeftNotRight; > reg [3:0] LED; // This in addition to the output declaration > ... > always @(posedge clk or posedge reset) > if (reset) begin > LED <= 1; > LeftNotRight <= 1; > end else if (cnt1max) begin > if (LeftNotRight) begin // Going left > if (LED[3]) > LeftNotRight <= 0; > else > LED <= LED << 1; > end else begin // Going right > if (LED[0]) > LeftNotRight <= 1; > else > LED <= LED >> 1; > end > end > > For lots of extra credit, see if you can work out > a) what happens if the LED register gets more than > one of its bits set, for any reason; > b) what happens if the LED register becomes zero > for any reason, and what you might do to fix it > > :-) > > -- > > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > > >Article: 66667
Hi, there: I am using a Virtex-2's DCM to convert a 40MHz clock into synchronized 12MHz (40X3/10) and 4MHz (40/10) clocks. In the attributes I set these constrainsts...Simulation and synthesis were correct. The min frequency seems to be within the specification of DCM. but I don't want to see this warning...What constraint do I need to set? (Not the trick suppress the warning) WARNING:Timing:2799 - The output clock clk_12m_rx from DCM DCM0 has a period (frequency) specification of 83333 ps (12.00 Mhz). This violates the maximum period (minimum frequency) of 41670 ps (24.00 Mhz). //synthesis translate_off defparam .......................blah blah............................ //synthesis translate_on // synthesis attribute CLKIN_PERIOD of DCM0 is 25 // synthesis attribute DLL_FREQUENCY_MODE of DCM0 is "LOW" // synthesis attribute DUTY_CYCLE_CORRECTION of DCM0 is "TRUE" // synthesis attribute STARTUP_WAIT of DCM0 is "TRUE" // synthesis attribute DFS_FREQUENCY_MODE of DCM0 is "LOW" // synthesis attribute CLKDV_DIVIDE of DCM0 is 10 // synthesis attribute CLKFX_DIVIDE of DCM0 is 10 // synthesis attribute CLKFX_MULTIPLY of DCM0 is 3 // synthesis attribute CLK_FEEDBACK of DCM0 is "1X" // synthesis attribute CLKOUT_PHASE_SHIFT of DCM0 is "FIXED" // synthesis attribute PHASE_SHIFT of DCM0 is 0 Best Regards, KelvinArticle: 66668
Hi:
I am building my first Verilog project with Xilinx WebPack 5.2i.
I have a module test_delay8 that instantiates a module Delay8Bit, which
in turn instantiates two further modules, an 8-bit comparator and an
8-bit counter, where the counter is inferred from the XST library.
But I get lots of warnings about inputs and signals not used:
--------------------------------------------------------------------
Synthesizing Unit <CB8CE>.
Related source file is cb8ce.v.
Found 8-bit up counter for signal <Q>.
WARNING:Xst:647 - Input <CE> is never used.
Summary:
inferred 1 Counter(s).
Unit <CB8CE> synthesized.
Synthesizing Unit <Delay8Bit>.
Related source file is Delay8Bit.v.
WARNING:Xst:647 - Input <Delay<7>> is never used.
WARNING:Xst:647 - Input <Delay<6>> is never used.
WARNING:Xst:647 - Input <Delay<5>> is never used.
WARNING:Xst:647 - Input <Delay<4>> is never used.
WARNING:Xst:647 - Input <Delay<3>> is never used.
WARNING:Xst:647 - Input <Delay<2>> is never used.
WARNING:Xst:647 - Input <Delay<1>> is never used.
WARNING:Xst:647 - Input <Delay<0>> is never used.
Unit <Delay8Bit> synthesized.
Synthesizing Unit <test_delay8>.
Related source file is test_delay8.v.
WARNING:Xst:646 - Signal <Delay_td> is assigned but never used.
Unit <test_delay8> synthesized.
---------------------------------------------------------------------
The logic all seems to work, however.
What are these warnings all about? The signals certainly appear to be
used from my perspective. I would like to understand how to code so
that the warnings are not generated, since they are not confidence
inspiring.
Thanks for assistance
Good day!
P.S. Here are all the modules if you'd like to see. Feel free to
criticize my methods in addition to considering my original question:
module test_delay8(Trig_td, Out_td, Clk_td);
input wire Trig_td, Clk_td;
output wire Out_td;
wire [7:0] Delay_td;
assign Delay_td = 83;
Delay8Bit D1 (.Trig_in(Trig_td), .Out(Out_td), .Clk_in(Clk_td),
.Delay(Delay_td));
endmodule
module Delay8Bit(Trig_in, Out, Clk_in, Delay);
input wire Trig_in, Clk_in;
input wire [7:0] Delay;
output wire Out;
wire [7:0] Qc;
wire CompMatchOut;
wire nowhere1, nowhere2;
supply1 h;
CB8CE Counter1 ( .Q(Qc), .TC(nowhere1), .CE0(nowhere2),
.C(Clk_in), .CLR(~Out), .CE(h) );
Compare8 Comp1 (CompMatchOut, Qc, Delay);
FDC FF1 ( .Q(Out), .C(Trig_in), .CLR(CompMatchOut), .D(h) );
endmodule
module Compare8(Q, A, B);
output wire Q;
input wire [7:0] A;
input wire [7:0] B;
wire X7, X6, X5, X4, X3, X2, X1, X0;
xnor
XNOR7 (X7, A[7], B[7]),
XNOR6 (X6, A[6], B[6]),
XNOR5 (X5, A[5], B[5]),
XNOR4 (X4, A[4], B[4]),
XNOR3 (X3, A[3], B[3]),
XNOR2 (X2, A[2], B[2]),
XNOR1 (X1, A[1], B[1]),
XNOR0 (X0, A[0], B[0]);
and (Q, X7, X6, X5, X4, X3, X2, X1, X0);
endmodule
module CB8CE(Q, TC, CE0, C, CLR, CE);
output reg [7:0] Q;
output reg TC, CE0;
input wire C, CLR, CE;
/* Here is the "Counter binary 8-bit async. clear with enable (CB8CE)"
inference code
from the Xilinx lib.pdf document: */
always @ (posedge C or posedge CLR)
begin
if (CLR)
Q <= 0;
else if (CE)
Q <= Q + 1;
end
always @ (Q)
begin
if (Q == 255)
TC <= 1;
else
TC <= 0;
end
always @ (CE or TC)
begin
CE0 <= TC && CE;
end
/* END of CB8CE inference code */
endmodule
--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov
Article: 66669W. S. Carter et al., "A user programmable reconfigurable logic array," in Proc. Custom Integr. Circuits Conf., 1986, pp. 233--235. I need this paper badly. Who can help me on this paper? TIA! :)Article: 66670
I upgraded to webpack 6.1i from 4.2 and when I compile my design I get the following error. Loading device for application Xst from file 'v100.nph' in environment C:/Xilinx. FATAL_ERROR:DeviceResourceModel:basnpdevice.c:620:1.23 - bad nph file Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com I searched through answer database but did not find anything. Does anybody has any ideas ? Sumit -------------------- http://www.c-nit.netArticle: 66671
Hi, I'm undergrad working on project that invovles data transfering from a PCB to computer using removable media. I had been studying the smartMedia format for some time now. I think I can write a custom VHDL firmware that will work on one type of SmartMedia card(8mb) 1. write the serial input command to the command latch 2. sets up the col and row address to the address register(starting from the very first byte of the first block of the first page) 3. left the program in a waiting state 4. once the write enable signal is triggered, output the actual data(ascii decimal) to the card 5. once the write enable signal is dropped, terminate the writing action 6. now that the raw data is in the chip, I use the unix utility dd (disk dump) to convert this raw data to an ascii file... I know that the SSFDC forum has the full functional firmware for free, but I don't want to use it since we do not all the *junk features, like the ECC and power code. I don't even have a proper smartmedia card connector. I'm just going to connect 22 wires to the card... I will be using Xilinx foundation to implment my design. The PCB is already set up. Hardware shouldn't be an issue. The clk is definitely fast enough for smartmedia what I want to know is: 1. has someone done something similar before. If so, does what I'm about to do sound feasible? Am I overlooking any issue? 2. if you know a better way to transfer data from a PCB to computer using standard removable media(can be non-smartmedia), what is it? 3. tips? Thanks for any input!Article: 66672
Thanks for your reply! It seems in my case the problem is the one addressed by Xilinx Answer Record 18558 (should have looked there before wasting so much time over this): > When running BitGen with the "-bm" option with an empty BMM file, > BitGen seg faults. > Solution 1: > The issue is that BitGen cannot accept an empty BMM file. > The work-around is to remove the "-bm" option and the BMM file > from the BitGen command line. In my toy example, the .bmm file was indeed empty. Of course, what they really mean to say apparently is that I have to nuke the -bm option from ngdbuild. I did this by removing this option from the default fast_runtime.opt file that Xilinx Platform Studio uses, and now bitgen is able to handle my toy example without crashing. Mahim Sean Durkin <23@iis.42.de> wrote in message news:<4039bc6f$1@news.fhg.de>... > Mahim Mishra wrote: > > I am trying to generate a configuration bitstream for a small design > > using Xilinx's Embedded Development Kit. The design has a small > > PowerPC component and a small FPGA component. When I run bitgen on the > > FPGA component, it crashes silently without producing any error > > messages. I have tried doing this using the EDK GUI front-end (Xilinx > > Platform Studio) as well as from the command line, with the same > > result. Bitgen works fine if I try to compile a design that does not > > use the embedded PowerPC core. > Have you tried opening the .NCD file bitgen tries to convert in FPGA > Editor? My guess is it's the underlying .NCD that is corrupt. In that > case, FPGA Editor will crash if you try to open it... > > John Williams described somnething like this not long ago. I too have > encoutered corrupt .NCD-files from time to time, but I can't put my > finger on it, i.e. I can't reproduce it or narrow down where it comes from. > > Have a look at the logfiles, especially from the par stage, and see if > there's anything unusual there. In my case par seems to finish without > errors, bit generates a corrupt .NCD... > > If you can reproduce this reliably, maybe you could open a WebCase with > Xilinx. Since you're now the third person with the same problem, I'm > beginning to believe it's not just me being too stupid to use the tools. :)Article: 66673
Martin Euredjian wrote: > The other interesting choice today is V2 Pro. Could you give a link for that? See you, UweArticle: 66674
>2. if you know a better way to transfer data from a PCB to computer > using standard removable media(can be non-smartmedia), what is it? The usual way to get data from a random project to a PC is over a serial port. (RS-232) I haven't worked with Smart Media. They are used in digital cameras. The usual way to get pictures from a camera is via USB where the storage device looks like a disk. That means you (probably) have to write things in a file-system format. Is your software going to support that? I don't know why you want to use Smart Media. I'll assume you want to put it where a serial cable won't reach. If the file system software turns out to be too complicated, you might be able to build a chunk of hardware that reads the SM card and sends the bits out a serial port. Mostly the reverse of writing it. (Or you could add a serial port to your existing board and load new firmware.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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