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This is clearly not offering anyone anything of any import. I hope my explanations have been clear and understood by the others out there. Have a nice day. AustinArticle: 66851
hi,
yesterday i read about DLL block which will give 2xclkin as
output. This is avilable in XILINX fpga. anybody how to use that means
in VHDL how we have to write to get that block.
thanking you all.
Article: 66852On 27 Feb 2004 07:03:22 -0800, johnjakson@yahoo.com (john jakson) wrote: >Philip Freidin <philip@fliptronics.com> wrote in message news:<n38t30lqn0um4pthhp6us1tparpscbt3m0@4ax.com>... >> >> http://www.fpga-faq.com/FPGA_Boards.shtml > >Philip, are there any sp3 boards that have shipped AFAYK, NuHorizons >has a $150? board but not sure if available yet. I expect there are >quite a few in the wings sans parts. > >johnjakson_usa_com I have no idea of which boards are shipping and which are sleeping in little boxes waiting for parts. The data on my web site is based only on what I find by cruising the web. By the way, thanks for the acknowledgement of my early work on FPGA CPU's that you wrote a few days ago. I was chatting with Jan yesterday, and he says thanks too. =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 66853
Patrik <pclad.adr@firemail.de> wrote in message news:<opr3znynuohr4cxo@news.t-online.de>... > Hi Greg, > > the problem is, that I have to program the devices with a microcontroler, > not an embedded Processor. Therefor I cannot use the JAM language, because > the JAM Interpreter wouldn't compile on an microcontroler (maybe a ATMEL, > it's not decisioned, yet). > > Thanks, > Patrik Hi Patrik, Altera has developed a Jam solution (include code) for the 8051 microcontroller, which is one of the Atmel options. This is documented in App Note 111, Embedded Programming using the 8051 and Jam Byte-Code. http://www.altera.com/literature/an/an111.pdf The source code is available on: https://www.altera.com/support/software/download/programming/jam/dnl-8051_player.jsp It took some optimization to get this to go into the 8051, but it does work and is easy to use after this optimization was complete. Sincerely, Greg Steinke gregs@altera.com Altera CorporationArticle: 66854
mrather@altera.com (Michael) wrote in message news:<250d58c1.0402251837.32d4855c@posting.google.com>... <snip> > Logic Structure Comparison Between Stratix & Virtex-Based > Architectures > http://www.altera.com/literature/wp/wpstxiixlnx.pdf <snip> The idea of an architecture comparison using "real" designs is of great interest, however the choice of comparison metric used in the white paper above is woolly. A much better metric for comparison would be the silicon area required (normalised to the same process technology). "Normalized Relative Logic Capacity" in terms of the "ALUT" has little meaning.Article: 66855
rickman <spamgoeshere4@yahoo.com> wrote in message news:<403E4742.1F02D0B8@yahoo.com>... > Martin Thompson wrote: > > > > gregs@altera.com (Greg Steinke) writes: > > > > > Martin Thompson <martin.j.thompson@trw.com> wrote in message news:<uishvxwee.fsf@trw.com>... > > > > gregs@altera.com (Greg Steinke) writes: > > > > <snip> > > > > > The IO Element has a programmable inversion in it to accomodate the > > > NOT technique. So for example if an LE register drives a pin, and the > > > design calls for the register to be async preset, the compiler will > > > use the NOT technique and implement the after-register NOT in the IOE. > > > However, the best tCO is obtained by using the IOE register, and the > > > programmable inversion is before the D of the IOE register. So there > > > is no way to implement an async preset in the IOE, which is probably > > > the reason for the tCO pushout that you saw - the register was moved > > > into an LE which increases tCO. > > > > > > If you see a design where an async-preset LE drives a pin, and there's > > > an extra LE put into the path to implement the NOT gate, this is a bug > > > and should be reported to Altera and/or Synplicity. But I'll bet that > > > the tCO pushout is due to the register moving from the IOE to the LE. > > > > > > > Yes, that is what was happening - it was a while ago, I remember now! > > What happens to the power-up (not reset) behaviour? Does it still > > power up low until the reset occurs? > > The data sheet is one thing. But I was asking about how to get the FF > to use whatever is available. From what I read in the data sheet, it > looks like a preset can be done by putting a 1 on DATA3. This will also > become part of the power on reset as well as the reset pin function. > But it also appears that to use it I have to provide an async set in my > code separate from the global reset. > > Either way this does not look good. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX Rick, If you do a preset by putting the 1 on the DATA3 and doing an async load, then the register will power up low, and the Chip Wide Reset will force the register low. The advantage here is that you can have async preset and async clr as separate controls. The disadvantage is that it takes up one of the LUT inputs. If you do the preset by putting a NOT gate before the D, and another after the Q, then the register will appear to power up high, and the Chip Wide Reset will appear to force the register high. (In reality it is low, but it seems high due to the NOT.) The advantage here is that it is free (unless you need fast tCO as this technique can't be done in the ACEX IOE). The disadvantage is that you cannot have a preset and clear on the same FF. Sincerely, Greg Steinke gregs@altera.com Altera CorporationArticle: 66856
valentin tihomirov wrote: > I have some questions regarding Xilinx design flow. > > What NGD and NGC files are? Is edif file created by the 2edif tools > synthesizable? The NGD file is the output of NGDBUILD and is written in a database format in terms of SIMPRIMs similar to NCD (the output of Map and Par). NGC is the output of XST and is a slightly different database format in terms of UNISIMs. Below, I will go into more explanation of SIMPRIMs and UNISIMs for your other question. In terms of NGD2EDIF, that tool's purpose was to create a simulation EDIF file for the Mentor QuickSim products. Since we no longer support QuickSim, ngd2edif is no longer shipped starting with the 6.1i release. As for ngc2edif, that tools main purpose is to supply edif versions of the NGC file as input to third-party synthesis tools in order to understand the contents of the NGC files for timing and area optimization and reporting. The output EDIF from either tool is not intended to be synthesizable or be using as an input for all or part of a design for ngdbuild. > According to > http://toolbox.xilinx.com/docsan/xilinx4/data/docs/dev/ngdbuild2.html, > NGDBuild converts netlist (Edif, Ngc, Xnf) into logical design (ngd - logic > elements like AND gates, decoders, FFs, RAMs). This is called translation. > But what is a role of synthezier, isn't it XST that should generate netlist > of logic gates from RTL description? The general purpose of a synthesis tool to to take an HDL description of a design in RTL (Register Transfer Level) and/or structural primitive components and create an output netlist in which specifies the base components and connectivity in terms of UNISIM components. Ngdbuild then takes that netlist, performs DRCs (Design Rule Checks) on the input netlist and translates the design from the logical domain (UNISIM) to the physical domain (SIMPRIM). Again I will talk more about UNISIM and SIMPRIM below to answer your other question. > ActiveHDL IDE allows for functional, > post-synthess and timing (post-implementation) simulations. Sinthesis is > done using Sinplify; it includes two stages: compilation and mapping. After > syntesis, Xilinx implementation tools are used to get timing information. > Implementation consists of translation, mapping (again?) and P&R. Why > mapping is done twice? Mapping might be an over used term here. In the sense of how the syntheisis tool is mapping, it takes the logic functions described by the engineer and "maps" it into a LUT (Look-Up Table) as well as other functions described in the code to their proper primitives. The Map function in ISE takes those primitives and maps them into larger blocks like IOBs and Slices. This is also knows as packing and I generally like to use the term packing when referring to Map's function since it is less likely to be confused with the mapping that the synthesis tool performs. > Why two different libraries (Unisim and SimPrim) are used for syntesis and > implementation? Wouldn't it be more effective to use only one? Can I write a > structural edif file based on elements of those libraries (which one?) and > synthetize it effectively creating design from scratch bypassing synthesis? This is a good question I get from time to time and there are actually several answers to this question and I will only touch a few of them. First off the decision to use two separate libraries for the front-end design (UNISIM) and back-end design (SIMPRIM) was made several years ago as we transitioned from the XACT tools to the ISE tools that you use today. Back in the XACT days we ran into some issues with having the same library in the front-end and back-end design and decided to use separate libraries for each would some many of those issues and thus the SIMPRIM library was born. Some of the issues we though this could address included the fact that each library was used in different stages of the design and each simulation actually serves different purposes. In the early stages of the design, you want a fast behavioral representation of the component that is easy to use (instantiate and understand), runs fast and integrates well in an RTL design. During timing simulation, you want a model that works well in a pure-gate model (no RTL), very accurately reflects exactly how it is implemented in silicon and have very accurate timing information however since the tools generate the netlist, you would never need to instantiate them and for this case, absolute accuracy is more important than fast runtime (although both are always nice). By having separate libraries we are able to remove all timing information from the UNISIM library, create convenience macros like the BUFGDLL and the FDCE, able to add attribute checking to give initial DRCs to the design, and able to optimize and accelerate the library in way not possible if used for back-end simulation (as well as other things). As for the SIMPRIM library, without having to worry about people using it in front-end simulation which is where most people spend most of their time simulating, we are able to remove attribute checking (this is done as a part of the DRC in Build and Map), put full timing checks in the models, use models that more accurately reflect the actual silicon and add models that are used only for timing simulation like the X_BUF_PP in VHDL which does glitch checking that is not necessary or useful for front-end design. There were actually many more reasons than this why we went to a two library system but I think what is said above illustrates the main points and benefits for this. I know this is somewhat unique and does take some getting used to but hopefully most will see benefits in every stage of simulation due to this forward thinking. Hope this explains things for you. It is not always clear why decisions like these are made but when you know the background behind the decisions, it generally becomes much more clear why things are the way they are. Good luck with your design, -- Brian > > Thanks. > >Article: 66857
In article <a0f83dd1.0402271208.375ef764@posting.google.com>, Irwin Kennedy <iokennedy@hotmail.com> wrote: >The idea of an architecture comparison using "real" designs is of >great interest, however the choice of comparison metric used in the >white paper above is woolly. A much better metric for comparison would >be the silicon area required (normalised to the same process >technology). "Normalized Relative Logic Capacity" in terms of the >"ALUT" has little meaning. It depends. If your metric is throughput (parallel/pipeline/multitask), then it has to be normalized to area or cost. LEs is a funny metric, it has to be silicon area. But if the metric is latency, then actually area is secondary altogether, and its just the clock cycle. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 66858
I am trying to configure a toy application with a small FPGA component and a small PoewerPC component on a Xilinx xc2vp20 FPGA mounted on an AFX development board. I am using Xilinx EDK 6.1.2 and Xilinx ISE 6.1.03i. I am able to generate run all the compilation steps, but when I try to configure the FPGA using the generated .bit, .bmm and .elf files, Impact crashes with the error message "FATAL_ERROR:GuiUtilities:WinApp.c:657: $Revision - ...." The Xlinx Answers Database is not being very useful. Does anyone have any idea what I may be doing wrong? Thanks, MahimArticle: 66859
Hi Kolja,
This will be of interest to you. The EU has apparently included a
loop hole in the Lead free spec. Is your PCB < 0.1% lead/tin?
cheers, Syms
http://tinyurl.com/3d486
Article: 66860Irwin Kennedy wrote: > > mrather@altera.com (Michael) wrote in message news:<250d58c1.0402251837.32d4855c@posting.google.com>... > > <snip> > > > Logic Structure Comparison Between Stratix & Virtex-Based > > Architectures > > http://www.altera.com/literature/wp/wpstxiixlnx.pdf > > <snip> > > The idea of an architecture comparison using "real" designs is of > great interest, however the choice of comparison metric used in the > white paper above is woolly. A much better metric for comparison would > be the silicon area required (normalised to the same process > technology). "Normalized Relative Logic Capacity" in terms of the > "ALUT" has little meaning. Likewise, logic capcity per silicon area has no real meaning. I have never bought a chip because it had a given area. I care about the cost. But that brings in another coefficient/variable that would have to be measured. In the real world manufacturers don't charge according to their costs. They charge according to the market making as much profit as they can squeeze out. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66861
Greg Steinke wrote: > > Rick, > If you do a preset by putting the 1 on the DATA3 and doing an async > load, then the register will power up low, and the Chip Wide Reset > will force the register low. The advantage here is that you can have > async preset and async clr as separate controls. The disadvantage is > that it takes up one of the LUT inputs. > > If you do the preset by putting a NOT gate before the D, and another > after the Q, then the register will appear to power up high, and the > Chip Wide Reset will appear to force the register high. (In reality it > is low, but it seems high due to the NOT.) The advantage here is that > it is free (unless you need fast tCO as this technique can't be done > in the ACEX IOE). The disadvantage is that you cannot have a preset > and clear on the same FF. At this point, I understand the ACEX hardware. But I can't put gates anywhere. I am asking how to control this from my VHDL. In the Xilinx parts, you use a symbol to drive a global reset net. The tools then remove the symbol and use the GSR feature to control the FFs reset function. I have no idea how to do this in VHDL for the ACEX parts. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66862
I have to agree with rickman ( in spite of his harsh wording) The issue is not square millimeters, the issues are: Capacity, performance, and price (and power, familiarity and software support) The connection between price and silicon area is very tenuous: Defect density, process maturity, manufacturing volume, package cost, and market conditions are equally important factors. Thank God we are not (yet) selling FPGAs by the square millimeter. And BMW, Lexus and Cadillac are still not selling their cars by the pound, or even the cubic inch. And those products have more than a hundred-year evolution behind them... Peter Alfke > > Likewise, logic capcity per silicon area has no real meaning. I have > never bought a chip because it had a given area. I care about the > cost. But that brings in another coefficient/variable that would have > to be measured. In the real world manufacturers don't charge according > to their costs. They charge according to the market making as much > profit as they can squeeze out. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66863
We're currently running a 3 GHz Pentium with 2 GB memory under Windows 2000. We hope to speed things up by 15-20%, by going to AMD X86-64 and / or Linux. Has anybody tried this? Any feedback?Article: 66864
Peter Alfke wrote: > > I have to agree with rickman ( in spite of his harsh wording) Geeze Peter, I don't know what I said that you thought was harsh... or are you responding to my statement about companies charging as much as the market will allow? That was not meant as an insult, just a simple statement of fact. If companies did not make a profit, they would not exist. That is the nature of our system, in order for companies to form there has to be a profit motive. No insult intended, I just wanted to clarify that there is only an indirect relationship between a product's cost and its price. Likewise there is only an indirect relationship between the silicon area and the price. Heck, I am in business to make money. I don't price my products by their cost, I price them by how useful they are to my customers. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66865
I am looking at the data sheet for the Spartan 3 parts trying to figure out how to configure them. It seems like it is the same as most of the other families, but there is one note that I don't completely understand. Section 3, page 12, has the following text... Figure 5: Waveforms for Master and Slave Parallel Configuration Notes: 1. In a given CCLK cycle, when RDWR_B transitions High or Low while holding CS_B Low, the next rising edge on the CCLK pin will abort configuration. This is not exactly the same as XAPP176 describing the Spartan II configuration, page 14... While CS is High, the Slave Parallel interface does not expect any data and ignores all CCLK transitions. However, WRITE must continue to be asserted while CS is asserted. If WRITE is High during a positive CCLK transition while CS is asserted, the FPGA aborts the operation. In the first case it sounds as if the abort condition is created by CS- being low and an edge on the RDWR- signal followed by a rising edge on CCLK (without making it clear if this also has to be during CS- low). In the second case, it is just the state of the two signals, sampled at the rising edge of CCLK which will create an abort. If I am trying to use the CS- WR- and IO signals from an MCU to control this, the difference between these two descriptions is significant. Am I making this more difficult than it is? Can I connect the signals as shown below and make this work ok? MCU FPGA Write NO --- ---- Byte Write CS- RD_WR- ----_______------______--- WR- CCLK -----_____--------____---- IO CS- -_____________------------ The other thing I am not clear about is how to use these same signals after configuration. It looks like I have to set "persist" to off if I want to put these signals on the MCU bus after config in order to have a bus interface to the chip. But if I want to perform partial reconfiguration, I think I have to have "persist" set to on, no? Does this mean I will have to double up on all these signals, one for (re)configuration and one for operation? I seem to recall that the Lucent chips allowed you to use the MCU interface after configuration. Do the Xilinx chips have that as well? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66866
On a sunny day (Fri, 27 Feb 2004 03:21:31 GMT) it happened "p" <chaosdynasty@hotmail.com> wrote in <%Iy%b.626113$ts4.526502@pd7tw3no>: >Hi, > >www.sfu.ca/~pyuan/sm/ > >enjoy! > >All the doc are free. But you need to register in the SSFDC forum to get >them. So I will save everybody the trouble... Thank you, got the .pdfs appreciated :-) lots of info, presented in a nice way too. JPArticle: 66867
Austin Lesea <austin@xilinx.com> wrote in message news:<c1nvd9$lnm1@cliff.xsj.xilinx.com>... > This is clearly not offering anyone anything of any import. > > I hope my explanations have been clear and understood by the others out > there. No, you never answered the question. How many logic cells does the XC3S1000 have? The data sheet says 17,280. Is that correct? My understanding is that this number is meaningless and that I have to figure it out for myself. If I know that there are 8 LCs per CLB, then I can multiply 1,920 * 8 = 15,360. Funny, that is not the same as 17,280, is it? Can you explain? Perhaps I don't understand what a logic cell is...Article: 66868
On 27 Feb 2004 19:27:47 -0800, sense_1909S_VDB@yahoo.com (google_guy) wrote: >Austin Lesea <austin@xilinx.com> wrote in message news:<c1nvd9$lnm1@cliff.xsj.xilinx.com>... >> This is clearly not offering anyone anything of any import. >> >> I hope my explanations have been clear and understood by the others out >> there. > >No, you never answered the question. How many logic cells does the >XC3S1000 have? The data sheet says 17,280. Is that correct? > >My understanding is that this number is meaningless and that I have to >figure it out for myself. If I know that there are 8 LCs per CLB, >then I can multiply 1,920 * 8 = 15,360. Funny, that is not the same >as 17,280, is it? > >Can you explain? Perhaps I don't understand what a logic cell is... Well google_guy, maybe you should try Google :-) Google is your friend (if you talk to it nicely). Google search "counting logic cells" and you get a link (without much effort) to http://www.fpga-faq.com/archives/65200.html#65218 and also: http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/xbrf/xbrf011.pdf But one of my favorites is this: http://www.fpgacpu.org/log/jan01.html#marketing_gates The short story is that the marketing weenies got to gate counts and butchered it to the point of meaninglessness, so engineers turned to LUT/LC counting, and now it is being abused too. Although I have not looked recently, in the past I found that Actel's gate-count claims were fairly honest, as were Xilinx's back around the XC4000 family (See the table in the "marketing_gates" link). I particularly hate the new meaningless term "System Gates". When I do estimates, I use E-Gates, which are gates that an engineer may actually get to use. Philip =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 66869
I'd like to support the ARM and IA32 ISA on an FPGA. At the moment Im unsure if I can do this. So what I thought is that if only I have some small clean test bench of both ISA's, then I could start supporting those small set of instructions. Later on I would add in the rest. Im wondering if there's anyone that happens to have some small clean test benchs or even applications, then could you forward them to me. thanks heaps.Article: 66870
inaganti_suni@yahoo.com (sunil) wrote in message news:<9f28d282.0402270956.6c177648@posting.google.com>... > hi, > yesterday i read about DLL block which will give 2xclkin as > output. This is avilable in XILINX fpga. anybody how to use that means > in VHDL how we have to write to get that block. > thanking you all. Take a look at this: http://toolbox.xilinx.com/docsan/xilinx6/de/libs/dcm.pdfArticle: 66871
"Avinash Sharma" <asharma3@REMOVETHIS.uiuc.edu.NOSPAM> wrote in message news:<c1k4qp$sq7$1@news.ks.uiuc.edu>... > is it true that one-hot encoding for FSM's is used in FPGA's? If so, > why? is it due to the large amount of registers available i.e: enough > registers to store all states? what kind of encoding is using in ASIC's? > > thanks much With a good synthesizer, you can specify any encoding you want. One hots can run at higher frequencies and usually result in less combinatorial logic.Article: 66872
"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in message news:<c0qnad$1ac2h2$1@ID-212430.news.uni-berlin.de>... > The planned architecture: > telephone line -> ADCs (8k samples pre second)-> FPGA (samples into > ram) -> AXIS controller (with Ethernet) > > The goal is to tap several (about 8) telephone channels and convert them > into TCP/IP stream. TCP server will run on Axis controller. I consider to > use FPGA for polling ADCs and storing samples into Block RAM. When FPGA > buffers are say 50% full, the FPGA would interrupt the controller. AXIS runs > at 100MHz. The interrupted controller would address FPGA by address bus and > reads all samples from FPGA memory. I think 1 kbyte sample buffer would be > enaught for an audio channel. Is this for research, or a product. If product, is cost a concern? Is your heart set on using an FPGA, or would you consider cheaper alternatives even if it means you don't get to play with those neat FPGAs? Is this for a VoIP system? If so, 512 samples at 8kHz will add 64 mS of latency. I.e., lag would make conversation quality suffer. If this is for record only/lawful intercept only, it wouldn't matter. > > I'm new to this filed and want to ask whether the architecture choosen is > feasible? Which FPGA families suit better for the task? > AXIS is a risk processor; I'm thinking to implement addressing scheme where > there is an address for each audio channel. That is, any two sequential > reads from the same address would read two sequential samples from FPGA. It > it normal solution? You could probably use 8 dual ported FIFOs and the AXIS reads from these FIFOs could be decoded. E.g., base+0 for ch 0, base+1 for ch 1, etc. > > Thanks, any references are highly appretiated!Article: 66873
Miaz371240@austromail.at (Nicky) wrote in message news:<c7068a2e.0402180404.71afeaa@posting.google.com>... > Hello, > > I have to design a universal PCI card according to PCI spec 2.2 with > 33Mhz and 32 pins. However for several reasons I have to use a FPGA > that is not 5V but only 3.3V tolerant. Specifically, which FPGA? > I thought of using a quickswith from IDT. Is this a good idea? Assuming you are designing a product, get the PCI specification, and make sure your circuitry to convert from one signaling level to the other doesn't violate it. I don't have it handy right now but if you're an engineer designing a PCI card you really should have it. If this is for a one or two of a kind board (not a product), you can cheat or hack as you wish. > What are the things I have to take care of when using this method? Are > there any other ways to make my card 5V compliant? Loading, trace lengths, capacitence. > > thanks+regards, > NickyArticle: 66874
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<S46Yb.24448$9T5.5086@newssvr27.news.prodigy.com>...
> Working on a polyphase decimator and interpolator. I'm trying to use the
> same chunk-o-logic to implement both functions. In either case, it is
> easiest to drive the control logic from the fastest of the two clocks. I'm
> trying to figure out the most elegant way to achieve this. Any thoughts,
> ideas, links?
>
> Thanks,
If you can work this out, it would be the easiest:
Say you have a set of frequencies you want to handle:
{f1, f2, f3, f4...fn}
Clock your control logic at a frequency that can generate all of these
other frequencies. E.g., for {2,3,5,6 whateverHz}, select your
control clock to be 30 whateverHz. To clock data in or out of the
decimator/interpolators, use clock enables that are synchronous to the
data and the control clock but have a duration of 1 control clock.
Slightly off topic, but if you're doing this fixed point, you might
have to adjust gains depending on input and output rate for consistent
scaling.
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