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I want to bring my knowledge about Forth processors up to date, so I'm posting some questions. Who is currently selling Forth processors? What happened to forthchip.com? Is there a community that is actively involved in discussing and/or developing FPGA-based Forth chips, or more generally, stack machines? Has anyone done any substantial DSP work in Forth? Are there libraries of code available? How about hardware Forth implementations that include dedicated DSP hardware? Thanks in advance! -- DavkaArticle: 66251
cmos_nand_gate@yahoo.com (Simon S. IBM) wrote in message news:<3520d403.0402131953.7b664fee@posting.google.com>... > Can you provide a pointer to a good random logic verilog > gate netlist generator? Such a tool does not exist. It will never exist. I tried to write one long ago but I failed. What you'll need to do is find some generic RTL and just place and route that generic RTL. I use ARM or Sparc code which is out there in the public domain. Just snatch a few tens of thousands of lines and place and route it. Send me an email and I'll send you the complete ARM core or Sparc. GlennArticle: 66252
Davka wrote: > > I want to bring my knowledge about Forth processors up to date, so I'm > posting some questions. > > Who is currently selling Forth processors? > > What happened to forthchip.com? > > Is there a community that is actively involved in discussing and/or > developing FPGA-based Forth chips, or more generally, stack > machines? You will get a lot of replies from at least one of the groups you posted to. But from what I can tell, there is only a small collection of Forth chips or cores that have been done. The effort is not mainstream and so it is not cohesive in any way that I can see. If you want to reach into the past, HP used to make a minicomputer that was stack oriented. I don't know anything about the design other than it was in the days of LSI rather than VLSI. Geeze, we must be working on SuperUltraLSI by now! > Has anyone done any substantial DSP work in Forth? Are there libraries > of code available? Again, I think you will find that forth is very much not mainstream for DSP. In general, DSP does not favor any typical processing archtecture. That is why they design chips just for DSP. If you want to do DSP, then I suggest that you learn about DSP. If you want to use Forth, then do that. But I would not expect to see Forth be a significant benifit when doing DSP. > How about hardware Forth implementations that include dedicated DSP > hardware? That would not be hard to do in an FPGA. Or you can run Forth on a DSP chip. The latter might gain you more benifit depending your DSP application. Some DSP apps are much better done on an FPGA. It depends on whether you can make use of multiple MAC units or if just the typical one or two found in a DSP chip will do. Davka -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66253
Hi, I have a design which does not fit on my Altera Stratix device. I need to split it onto 2 Stratix devices. Is it possible to manually do this? I can't afford a partitioning software. The clock frequency for the design after fitting will be around 30MHz and I can run the design at a speed slower than that achieved after fitting. So can I safely operate the design at say 20Mhz if Quartus was to ensure a speed of 30Mhz on a single larger FPGA? Slowing the FPGA by 10 MHz would mean I have an extra 100ns delay which will be used up by the interconnect delay between the 2 FPGAs(due to rise time/fall time of IO pins). Assuming this approach works, approx. how much extra delay should I leave for the interconnect delays? Are there any other issues I should be aware of? Thanks TushitArticle: 66254
In article <T%XXb.70$pM3.121810@news.uswest.net>, mygarbagepail@hotmail.com says... >Is there a community that is actively involved in discussing and/or >developing FPGA-based Forth chips, or more generally, stack >machines? Our motion control system runs a subset of Forth in a PLD. It is a very simple 16 bit two stack Harvard architecture RISC processor that uses less than 128 macro cells. Execution speed with the slowest parts is 25Mips Code 6Mips Forth. It has 128 spare macro cells that run at 50Mhz for customer options. such as encoders(6@10Mhz), step&direction(4axis@1Mhz), data capture(100M samples/sec), PWMs, etc. >How about hardware Forth implementations that include dedicated DSP >hardware? Do you want the Forth to supervise a set of DSPs, or be a DSP? jrhArticle: 66255
jrh wrote: > In article <T%XXb.70$pM3.121810@news.uswest.net>, mygarbagepail@hotmail.com > says... > > >>Is there a community that is actively involved in discussing and/or >>developing FPGA-based Forth chips, or more generally, stack >>machines? > > > Our motion control system runs a subset of Forth in a PLD. > It is a very simple 16 bit two stack Harvard architecture > RISC processor that uses less than 128 macro cells. > Execution speed with the slowest parts is 25Mips Code 6Mips Forth. > It has 128 spare macro cells that run at 50Mhz for customer options. > such as encoders(6@10Mhz), step&direction(4axis@1Mhz), data capture(100M > samples/sec), PWMs, etc. Interesting - what PLD / Speed spec gives the above numbers ? You probably should watch for the Altera MAX II family, when they release.Article: 66256
On Sun, 15 Feb 2004 21:52:01 -0700, "Davka" <mygarbagepail@hotmail.com> wrote: >Who is currently selling Forth processors? MPE is selling a VHDL clone of the RTX2000 for use in FPGAs. Stephen -- Stephen Pelc, stephenXXX@INVALID.mpeltd.demon.co.uk MicroProcessor Engineering Ltd - More Real, Less Time 133 Hill Lane, Southampton SO15 5AF, England tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691 web: http://www.mpeltd.demon.co.uk - free VFX Forth downloadsArticle: 66257
"jrh" <no@spam.com> wrote in message news:Si_Xb.57494$P17.17621@fed1read03... > Do you want the Forth to supervise a set of DSPs, or be a DSP? I want the Forth to direct the operation of a multiply-and-accumulate module, and to have access to a fast complex multiply. -DavkaArticle: 66258
hi PLD gurus - especially those with grey hair :-) For a fun project, and also on behalf of someone who asked me about it, I was hoping to mimic the functionality of the AMD 29PL141 programmable state machine (vintage ~1988) in an FPGA of some kind. But my old copy of the '141 data sheet has gone missing, probably lost in one of my rare and often disastrous domestic-rubbish purges. Does anyone have a copy, somewhere in their archives, that they could let me see by some means or other? There doesn't seem to be a copy of it anywhere on the web, which is not surprising because it wasn't very long-lived and it was POPped (*) long before the days of web-published data sheets. (POP: Planned Obsolescence Program, euphemism for dropping a part from your product line and consequently dropping a few customers in the fertilizer) Thanks in advance -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 66259
"Davka" <mygarbagepail@hotmail.com> wrote in message news:T%XXb.70$pM3.121810@news.uswest.net... > I want to bring my knowledge about Forth processors up to date, so I'm > posting some questions. [...] Have you seen http://www.ultratechnology.com/chips.htm ? I used to have a rather soft spot for the Harris RTX processors, which is more than I can say for FORTH which I regard as an invention of the devil ;-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 66260
Jonathan Bromley wrote:
>
> "Davka" <mygarbagepail@hotmail.com> wrote in message
> news:T%XXb.70$pM3.121810@news.uswest.net...
> > I want to bring my knowledge about Forth processors up to date, so I'm
> > posting some questions.
>
> [...]
>
> Have you seen http://www.ultratechnology.com/chips.htm ?
>
> I used to have a rather soft spot for the Harris RTX
> processors, which is more than I can say for FORTH which
> I regard as an invention of the devil ;-)
De gustibus non disputandum est.
> --
> Jonathan Bromley, Consultant
>
--
Julian V. Noble
Professor Emeritus of Physics
jvn@lessspamformother.virginia.edu
^^^^^^^^^^^^^^^^^^
http://galileo.phys.virginia.edu/~jvn/
"God is not willing to do everything and thereby take away
our free will and that share of glory that rightfully belongs
to us." -- N. Machiavelli, "The Prince".
Article: 66261I have a simple partial reconfig design. Under ISE6 SP2 it is only routable using fpga editor, command line PAR fails with the message 'abnormal program termination'. Not a big problem as fpga editor does the job! But after installing SP3, command line PAR and fpga editor fail reporting the design is unroutable. The problem is confirmed as being SP3 as I have now uninstalled it and the design routes OK. If anyone is having similar problems routing a design you may want to do the same. I would also like to thank Kamal Patel at Xilinx for his help and for creating a Spartan 2 bus macro, amazing service!! Cheers :)Article: 66263
On Mon, 16 Feb 2004 10:34:35 -0000, "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote: >I used to have a rather soft spot for the Harris RTX >processors, which is more than I can say for FORTH which >I regard as an invention of the devil ;-) An RTX2000 clone core is available from us in VHDL for FPGAs. A C compiler is also available. The CPU runs at 20 MIPs in a Xilinx Spartan. This is twice as fast as the original Harris (Intersil) part, with an interrupt latency of 200ns before starting useful work. Stephen -- Stephen Pelc, stephenXXX@INVALID.mpeltd.demon.co.uk MicroProcessor Engineering Ltd - More Real, Less Time 133 Hill Lane, Southampton SO15 5AF, England tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691 web: http://www.mpeltd.demon.co.uk - free VFX Forth downloadsArticle: 66264
The planned architecture:
telephone line -> ADCs (8k samples pre second)-> FPGA (samples into
ram) -> AXIS controller (with Ethernet)
The goal is to tap several (about 8) telephone channels and convert them
into TCP/IP stream. TCP server will run on Axis controller. I consider to
use FPGA for polling ADCs and storing samples into Block RAM. When FPGA
buffers are say 50% full, the FPGA would interrupt the controller. AXIS runs
at 100MHz. The interrupted controller would address FPGA by address bus and
reads all samples from FPGA memory. I think 1 kbyte sample buffer would be
enaught for an audio channel.
I'm new to this filed and want to ask whether the architecture choosen is
feasible? Which FPGA families suit better for the task?
AXIS is a risk processor; I'm thinking to implement addressing scheme where
there is an address for each audio channel. That is, any two sequential
reads from the same address would read two sequential samples from FPGA. It
it normal solution?
Thanks, any references are highly appretiated!
Article: 66265"tushit" <tushitjain@yahoo.com> wrote in message news:ec6aab0.0402152209.5f58efb6@posting.google.com... > Hi, > I have a design which does not fit on my Altera Stratix device. I need > to split it onto 2 Stratix devices. Is it possible to manually do > this? I can't afford a partitioning software. The clock frequency for > the design after fitting will be around 30MHz and I can run the design > at a speed slower than that achieved after fitting. Apart from the obvious organisational problem - how to make the split - there may be some tricky issues about clock synchronisation. You need to be sure that setup AND HOLD times are met in both devices. > So can I safely operate the design at say 20Mhz if Quartus was to > ensure a speed of 30Mhz on a single larger FPGA? Slowing the FPGA by > 10 MHz would mean I have an extra 100ns delay Sorry? 30MHz is 33ns period, 20MHz is 50ns period; sounds like only 17ns extra, to me. > which will be used up by > the interconnect delay between the 2 FPGAs(due to rise time/fall time > of IO pins). Assuming this approach works, approx. how much extra > delay should I leave for the interconnect delays? Remember that the propagation delay of a typical output driver is dominated by the capacitance it is driving. Propagation delay across a typical PCB is around 2ns per foot, so that should be OK unless your FPGAs are a long way apart or you let your PCB autorouter do silly things. Data sheet specs for FPGA output drivers usually tell you how the delay increases as a function of capacitance, so it should all be fairly predictable. If you are splitting one FPGA into two, it seems likely that the signals from one FPGA to the other will drive only one FPGA input in most cases. Therefore the capacitive slowdown should be modest. Be ready to add pipeline stages in the design, to cope with the very large propagation delays of FPGA I/O pad structures. But 30MHz should be easy to achieve across the boundary. Key suggestion: DON'T supply one FPGA's clock from an output on the other FPGA. Instead, be sure to supply BOTH FPGA's clocks from the same source. The worst-case skew between the two FPGA's clock buffer delays should be very much smaller than propagation delays of each FPGA's output pads; if this is true, you will have no problems with hold time. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 66266
Fron the Constraints guide: CLKIN_PERIOD specifies the period of the clock used to drive the CLKIN pin of the DCM. It must be specified to provide software with enough information for optimal frequency synthesis operation given an M and D value when using the CLKFX or CLKFX180 outputs. It is not needed for other DCM clock outputs. In your case, it looks like it's not used. clk0 will have the same frequency as the input clock. CLKDV will be 2/3 of this frequency (56 MHz in your case).Article: 66267
Jonathan - If for some reason Philip Freidin doesn't see your post, send him an e-mail. He was the father of the 29PL141. Bob Perlman Cambrian Design Works On Mon, 16 Feb 2004 10:16:17 -0000, "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote: >hi PLD gurus - especially those with grey hair :-) > >For a fun project, and also on behalf of someone who >asked me about it, I was hoping to mimic the functionality >of the AMD 29PL141 programmable state machine (vintage ~1988) >in an FPGA of some kind. But my old copy of the '141 data sheet >has gone missing, probably lost in one of my rare and often >disastrous domestic-rubbish purges. > >Does anyone have a copy, somewhere in their archives, that they >could let me see by some means or other? There doesn't seem >to be a copy of it anywhere on the web, which is not surprising >because it wasn't very long-lived and it was POPped (*) long >before the days of web-published data sheets. > >(POP: Planned Obsolescence Program, euphemism for dropping a >part from your product line and consequently dropping a few >customers in the fertilizer) > >Thanks in advanceArticle: 66268
Working on a polyphase decimator and interpolator. I'm trying to use the same chunk-o-logic to implement both functions. In either case, it is easiest to drive the control logic from the fastest of the two clocks. I'm trying to figure out the most elegant way to achieve this. Any thoughts, ideas, links? Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 66269
"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message news:csp13016toguahpob0fnon53r1jjms0qm1@4ax.com... > On Mon, 16 Feb 2004 10:16:17 -0000, "Jonathan Bromley" > <jonathan.bromley@doulos.com> wrote: > >hi PLD gurus - especially those with grey hair :-) > If for some reason Philip Freidin doesn't see your post, send him an > e-mail. He was the father of the 29PL141. OK, I give in. Is there some kind of ex-AMD conspiracy going on here? I already know that Peter Alfke was with AMD for a while; Bob, unless I'm much mistaken, I attended your presentation on proposals for the 29050 CPU at an AMD FAE meeting; now you tell me about Philip Freidin... Will all those who are *not* AMD alumni please stand up? :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 66270
Hello, I use Xilinx Chipscope for ISE 6.1. My question. What's the sample rate. I couldn't find any documentation about it. If I use a fast clock signal in my design, I do have to use a big sample rate, isn't it ? Otherwise I won' get the exact result. Right? Greatings, Tobias MöglichArticle: 66271
Hello I use Xilinx ISE 6.1 for synthesis. I discovered in the floorplanner that there are used very much IOB's. Even more than used IO pads. Why that ?? Is it for the reason of timing constraints (for example delays)?? As far as I know, I haven't made any timing constraint in my design. Is it possible not to use so many IOB's. How can I tell ISE to do so ? Greatings Tobi.Article: 66272
> The goal is to tap several (about 8) telephone channels and convert them > into TCP/IP stream. OK, what about control signal bits? Are you using CAS or CCS? Signalling? R2? What does your far-end look like? What type of telephone network do you want to connect to? You may need CCS if your far past the PSTN and in a private network . Is your box going to appear as an FXS and FXO? If so the context of the signal bits are different. Your going to need a ring generator and voltage sources for talk and ring, do you also need cadence control? I would strongly suggest you look at some of the third generation codec/audio processors out there. Another issue, regarding buffering is echo - the depth of your buffer affects the impulse response time in an FIR filter. There are Bell Pub. specs for this. Do you want ADPCM? I developed an FXS and FXO cards with no processor for a drop/insert T1/E1 box as well as a broadband wireless network , with just a Spartan XC2S200, so if you want to go on the cheap (processors take up board space and silicon) let me know. I can tell you that your going to have to clarify you requirements a great deal more.Article: 66273
"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in message news:c0qnad$1ac2h2$1@ID-212430.news.uni-berlin.de... > The planned architecture: > telephone line -> ADCs (8k samples pre second)-> FPGA (samples into > ram) -> AXIS controller (with Ethernet) I've never designed telephone stuff, but considering the speeds and speech quality requirements I think you can get away with a single A/D and an analog mux at the input. There are some A/D chips with the mux onboard. > The goal is to tap several (about 8) telephone channels and convert them > into TCP/IP stream. TCP server will run on Axis controller. I consider to > use FPGA for polling ADCs and storing samples into Block RAM. When FPGA > buffers are say 50% full, the FPGA would interrupt the controller. AXIS runs > at 100MHz. The interrupted controller would address FPGA by address bus and > reads all samples from FPGA memory. I think 1 kbyte sample buffer would be > enaught for an audio channel. The things will be a little easier if you use a FIFO structure for storing your data. Perhaps that's what you actually meant. > I'm new to this filed and want to ask whether the architecture choosen is > feasible? Which FPGA families suit better for the task? If what you describe is the only task for this FPGA, then you can use pretty much any FPGA, which has enough RAM. I would probably use something like XC2S50E. On the other hand you could choose Virtex-II Pro and run your TCP stack on the embedded PowerPC... /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca")Article: 66274
Hello, Ian: I saw you mentioned the Spartan-2 bus macro, could you exchange it with me? I am willing to trade for it with a complete partial reconfig design (vertex-2)...that was the tutorial I did, though...My email address is kelvin8157@hotmail.com... Best Regards, Kelvin "Ian" <tau14@sussex.ac.uk> wrote in message news:63c49b7e.0402160714.4a20dd45@posting.google.com... > I have a simple partial reconfig design. Under ISE6 SP2 it is only > routable using fpga editor, command line PAR fails with the message > 'abnormal program termination'. Not a big problem as fpga editor does > the job! > > But after installing SP3, command line PAR and fpga editor fail > reporting the design is unroutable. The problem is confirmed as being > SP3 as I have now uninstalled it and the design routes OK. > > If anyone is having similar problems routing a design you may want to > do the same. > > I would also like to thank Kamal Patel at Xilinx for his help and for > creating a Spartan 2 bus macro, amazing service!! Cheers :)
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