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Hello Brian. "Brian Drummond" <brian@shapes.demon.co.uk> escribió en el mensaje news:0o9s205ugmsf0k6efk6oianhcgvqq8m9bs@4ax.com... > > Another vote for headers. > > If one of them bears some relationship to a SODIMM socket, you could > conceivably support SDRAM through a controller in the FPGA, for those > who need it. Just a thought. > All the available MCU and FPGA signals have been exported to the headers (120 pins total). The idea of dual headers is to be able to stack modules up or down and keep things compact. We have also a design for a backplane, where the core module fits in dual headers and there are AGP132 connectors for the add-on modules that also have an edge connector (these have a length of ~2.7"that fits that format). So, yes, it's possible to have a module with SDRAMs controlled by the FPGA, although this will take some pins of the headers for the SDRAM control signals. If the module has an external controller that would be better, but perhaps a cleaner choice would be to use PSRAMs. The extra 12 signals of the AGP132 connectors are used for alternative voltages (eg negative voltages for bipolar DACs), and 4 pins are used for module auto-detection. Thanks for your comments. Regards.Article: 66226
Hi, there: I am running ngdanno & ngd2ver...not netgen yet. (netgen gave me no error, but it ignored my NGM file!!!) My design has been P&Red with 100% pass. However, it won't allow me to generate a hierarchical netlist. Below is the transcrpits. Thank you for your time. Kelvin D:\modulator\top_qpsk\assemble>ngdanno switch_top.ncd switch_top_map.ngm Release 6.1.03i - ngdanno G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line : ngdanno switch_top.ncd switch_top_map.ngm WARNING:Anno - Ngdanno and the netlist writers (ngd2ver, ngd2vhdl) are combined into one new executable: netgen. It is highly recommended that the user convert their scripts (flows) from ngdanno, ngd2ver and ngd2vhdl as soon as possible. Please see netgen command line help or refer to netgen user documentation for further details on the replacement executable. Writing .nga file "switch_top.nga"... D:\modulator\top_qpsk\assemble>ngd2ver -sdf_path . -w switch_top.nga Release 6.1.03i - ngd2ver G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. WARNING:NetListWriters:601 - Ngdanno and the netlist writers (ngd2ver, ngd2vhdl) are combined into one new executable: netgen. It is highly recommended that the user convert their scripts (flows) from ngdanno and ngd2ver as soon as possible. Please see netgen command line help or refer to netgen user documentation for further details on the replacement executable. Using netgen to create verilog netlist. Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Loading device database for application netgen from file "switch_top.ncd". "switch_top" is an NCD, version 2.38, device xc2v250, package fg256, speed -4 Loading device for application netgen from file '2v250.nph' in environment D:/Xilinx. The STEPPING level for this design is 1. FATAL_ERROR:Anno:Engine.c:476:1.44 - Xdm Exception: Xdm_Exception::DuplicateObjectFound object='switch_top' (XDM_DESIGN), parent='Annotated' (XDM_DESIGN_MGR) . Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com Created ngd2ver log file 'ngd2ver.log'. D:\modulator\top_qpsk\assemble>if errorlevel 1 goto DONEArticle: 66227
Hello, How can i program a configuration Device (EPC1PC8) for my Altera EP1K30 FPGA? It is not in system programmable. I´m using for coniguring the FPGA a ByteblasterMV-Cable. Now I´m looking for a method to program the EPC1. I have found some information in the web, that there is a adapter available to programm the EPC1. Is there any description available?, Schematic?. Thanks.Article: 66228
Michael Werner wrote: > Hello, > How can i program a configuration Device (EPC1PC8) for my Altera EP1K30= =20 > FPGA? It is not in system programmable. > I=B4m using for coniguring the FPGA a ByteblasterMV-Cable. > Now I=B4m looking for a method to program the EPC1. > I have found some information in the web, that there is a adapter avail= able=20 > to programm the EPC1. Is there any description available?, Schematic?. Did you have a look at AN116 from Altera. Configuring APEX20k, Flex10k & Flex6k Devices. Eventhough this application notes also applies to the ACEX family, Altera didn't find the need to include it in the title of the application note. There are plenty of notes for different setups with schematic and everything. Rene --=20 Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 66229
"Michael Werner" <unimatrix9@t-online.de> wrote in message news:c0nvj5$kjl$01$1@news.t-online.com... > Hello, > How can i program a configuration Device (EPC1PC8) for my Altera EP1K30 > FPGA? It is not in system programmable. > I´m using for coniguring the FPGA a ByteblasterMV-Cable. > Now I´m looking for a method to program the EPC1. > I have found some information in the web, that there is a adapter available > to programm the EPC1. Is there any description available?, Schematic?. > > Thanks. You will need some kind of device programmer that supports EPC1 device.As an alternative, you can use ATMEL FPGA configuration devices, which are MUCH cheaper and are ISP. The ISP software is free and you can build ISP programming adapter for nothing. All relevant datasheets and software are downloadable from ATMEL site ( http://www.atmel.com/products/Config/ ) I'm using them with various ALTERA devices and everything works flawlessly. Only be careful - there are 2 types - XILINX,ATMEL compatible and ALTERA compatible (A suffix) ! regards DejanArticle: 66230
Rene Tschaggelar <none@none.net> wrote in news:402f86d2$0$715 $5402220f@news.sunrise.ch: > > Did you have a look at AN116 from Altera. Yes, i have. > Configuring APEX20k, Flex10k & Flex6k Devices. Eventhough this > application notes also applies to the ACEX family, Altera didn't > find the need to include it in the title of the application note. > > There are plenty of notes for different setups with schematic > and everything. The acex works very fine , but my problem is , i want to program the epc1pc Chip. It don´t support in system programming. I have to programm it "stand alone" i have only a byteblasterMV and the Software says (MaxPlus) that the hardware does not support this device. I found a schematic to modify the Byteblaster MV, so that the software thinks it is an BB2. When this works, how do i connect the epc1 to the byteblaster? sorry for my bad english Michael WernerArticle: 66231
"Dejan Durdenic" <dejan.XremovethisX.durdenic@zg.htnet.hr> wrote in news:c0o0t0$r1j$1@ls219.htnet.hr: > You will need some kind of device programmer that supports EPC1 > device.As an alternative, > you can use ATMEL FPGA configuration devices, which are MUCH cheaper > and are ISP. > The ISP software is free and you can build ISP programming adapter for > nothing. All relevant > datasheets and software are downloadable from ATMEL site > ( http://www.atmel.com/products/Config/ ) > I'm using them with various ALTERA devices and everything works > flawlessly. Only be careful - there are 2 types - XILINX,ATMEL > compatible and ALTERA compatible (A suffix) ! Yes, i´ve seen them, but i can buy only 100 pieces at one time, and i need only 6. Wich Programmer do i need for the altera devices? Michael WernerArticle: 66232
Michael Werner wrote: > Rene Tschaggelar <none@none.net> wrote in news:402f86d2$0$715 > $5402220f@news.sunrise.ch: >=20 >=20 >>Did you have a look at AN116 from Altera. >=20 > Yes, i have. >=20 >>Configuring APEX20k, Flex10k & Flex6k Devices. Eventhough this >>application notes also applies to the ACEX family, Altera didn't >>find the need to include it in the title of the application note. >> >>There are plenty of notes for different setups with schematic >>and everything. >=20 >=20 > The acex works very fine , but my problem is , i want to program the=20 > epc1pc Chip. It don=B4t support in system programming. > I have to programm it "stand alone" i have only a byteblasterMV and the= =20 > Software says (MaxPlus) that the hardware does not support this device.= > I found a schematic to modify the Byteblaster MV, so that the software = > thinks it is an BB2. > When this works, how do i connect the epc1 to the byteblaster? I used the bigger brother, the EPC2 together with an 1k30. The EPC2 can be programmed with the ByteblasterMV. Ah, there is a new configuration handbook to be downloaded. Yes. chapter 6, page 6-18 shows that it works with EPC2 or EPC1. So they appear to be compatible. Then further page 6-34. However, when I did the ACEX1k30 design, I was told to use the EPC2. So there is a chance it may not work. Rene --=20 Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 66233
In article <402c61d2_2@nova.entelchile.net>, Pablo Bleyer <pbleyerN@SPAMembedded.cl> wrote: >This is a low cost, low power little board (3"x2") we designed to use in our >own custom control & data acquisition projects, but the concept turned out >so nice and nifty that we are evaluating the possibility to commercialize it >as a line product. It currently has an AT91M42800A MCU from Atmel (ARM7TDMI >with an external bus), up to 1MB RAM, 1MB to 8MB Flash, integrated power >supply and a Xilinx SpartanIIe FPGA (XC2S50E or XC2S100E) with a >programmable clock oscillator. Expansion headers are provided for all >important board signals (120, including power pins), with top and bottom >stack mount capability. One thing to be aware of: Cost, and bigtime. <$200 gets a Spartan 2 150 board with SRAM and FLASH which fits into a gameboy advance. Thus the total system cost is <$300 for processor, a couple MB of memory, a couple MB of flash, ~50 header pins, a nice little display, and a battery power supply. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 66234
wo when i have 0.002100205514 as a coefficient i enter it in the COE file as 2100205514 with the radix=10 and the width as i want it to be (with changing the coefficient to the size that it can fit the width!)? greetings, Yttrium > <ccon> wrote in message news:ee82680.2@WebX.sUN8CHnE... > scale your numbers to integer, the coef width depends on the resolution(decimal points)you wish.Article: 66235
"Michael Werner" <unimatrix9@t-online.de> wrote in message news:c0o1pn$kjl$01$3@news.t-online.com... > "Dejan Durdenic" <dejan.XremovethisX.durdenic@zg.htnet.hr> wrote in > news:c0o0t0$r1j$1@ls219.htnet.hr: > > You will need some kind of device programmer that supports EPC1 > > device.As an alternative, > > you can use ATMEL FPGA configuration devices, which are MUCH cheaper > > and are ISP. > > The ISP software is free and you can build ISP programming adapter for > > nothing. All relevant > > datasheets and software are downloadable from ATMEL site > > ( http://www.atmel.com/products/Config/ ) > > I'm using them with various ALTERA devices and everything works > > flawlessly. Only be careful - there are 2 types - XILINX,ATMEL > > compatible and ALTERA compatible (A suffix) ! > Yes, i´ve seen them, but i can buy only 100 pieces at one time, and i need > only 6. > > Wich Programmer do i need for the altera devices? > > Michael Werner Well, there are several that support EPC1 - Xeltek SuperPro Z (www.xeltek.com ), for example...(about 250 US$) regards DejanArticle: 66236
Clark Pope wrote: > performance. The ADC clock is 56 MHz. The source clock will be 8MHz so I > need 7x in the DCM. The DCM won't work with an input frequency of 8MHz. The minimum input is somewhere around 24MHz. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 66237
HI All,
Was wondering if someone could point me in the right direction on a
couple of problems?
I am using webpack 4.1 and trying to create a 74ls193. I first basically
built it from scratch using the logic diagram from the TTL datasheet but it
would not work correctly in a circuit.
Looking at the counters in the xilinx library there is none that clock
using the UP or Down like the ls193. They all use up/down pins and then
clock with a seperate pin.
Anyone have a solution or idea of how I could design a ls193 with either
descrete logic (like I tried) or using the library counters?
I am not a student and I am just doing this for fun and to learn a bit.
I have successfully made other TTl chips work (not included in the library)
like a 74ls670 (I built this one all discreet also in webpack)
I am not looking for someone to hold my hand (although I am a newbee to
webpack and xilinx devices), but maybe someone that has done this before (
made a ls193 or similiar) and could point me in the right direction.
Thanks,
Fred
Article: 66238I have two Xilinx DB-01 demo boards with the XC2064-33 FPGA, and the ML 4 cable and connector. Does anyone have any info about these? I have no real use for them, and was thinking about eBay... unless there is someone here who makes me an offer. JohnArticle: 66239
>I have two Xilinx DB-01 demo boards with the XC2064-33 >FPGA, and the ML 4 cable and connector. > >Does anyone have any info about these? I have no real >use for them, and was thinking about eBay... unless there >is someone here who makes me an offer. They are very old. Best use would be in a museum. I don't think software that supports them is available any more. If you can find it, it probably needs an old version of DOS. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 66240
> I am using webpack 4.1 and trying to create a 74ls193. I first basically >built it from scratch using the logic diagram from the TTL datasheet but it >would not work correctly in a circuit. > Anyone have a solution or idea of how I could design a ls193 with either >descrete logic (like I tried) or using the library counters? The party line is don't-do-that, Do something else, for example use a different part. The basic rule is that you have to meet both setup and hold times on all flip-flops in your design. That gets tricky if you have a complicated clock distribution system. Xilinx FPGAs have a very low skew clock distribution system. They promise that the hold time will be 0. (or really that the min prop time will be enough to cover the hold time) That means you only have to worry about the setup time. Their software is smart enough to figure that out and tell you the max speed your design will run at. Where are your up/down pulses coming from? If they come out of a state machine (flip-flop), then you want to use the same clock that drives that state machine to drive a counter, and use the up/down signals to decide if your counter goes up, down, hold... It will all make sense after you get used to it. It's much cleaner/simpler for high speed designs. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 66241
steve41@totalise.co.uk (Steve) writes: > The other reason that has been given is that distributors have to earn > a living. My heart bleeds for the poor loves... Well, their hearts aren't bleeding for yours either. They spend 90% of their time going for 10% customers. Or the one customer having 50% of their business... > I believe there are ways that Xilinx could improve their service to > smaller companies such as significantly increasing the number of > distributors to increase competition. Peter Alfke said: So that no disti would make any effort at all except maybe send an invoice. Not so good. Homann -- Magnus HomannArticle: 66242
Given the calamitous drop in the dollar recently, find a distributor who quotes in dollars and accepts payment in Euros...Article: 66243
Hi,
I am confused at how to set DCM generic parameters on Xilinx FPGA, I
know the input clock is 84MHz, and I see my colleague set
CLKDV_DIVIDE = 1.5
CLKIN_PERIOD = 10
then it seems he can get 66MHz from output pin CLKDV.
I am confused: Does 84MHz have any use here? It seems the actual
input clock frequency does not matter here, the output frequency is
totally depending on how you set these parameters.
Then my question is what's the frequency of clk0? 84MHz or 100MHz?
Thanks.
Article: 66244On Fri, 13 Feb 2004 09:26:44 -0000, "John Adair" <newsreply@loseinspace.co.uk> wrote: >You can usually do mixed language if you are prepared to pay lots of money >for licenses. But if your doing Xilinx, or maybe something else, then have a >look at the second method outlined here >http://www.enterpoint.co.uk/techitips.html . You can synthesis with XST in >both Verilog and VHDL. I can't confirm if you can do both at once in one >project I would need to check that. You can use both at once in the current version of XST. Regards, Allan.Article: 66245
Hal Murray wrote: >> I have two Xilinx DB-01 demo boards with the XC2064-33 >> FPGA, and the ML 4 cable and connector. >> >> Does anyone have any info about these? I have no real >> use for them, and was thinking about eBay... unless there >> is someone here who makes me an offer. > > They are very old. Best use would be in a museum. > > I don't think software that supports them is available any more. > If you can find it, it probably needs an old version of DOS. Thanks. That's what I thought. I also have a FPGA DEMO BOARD, with a XC3020A-7 and a XC4003A-6, with the XChecker cable and flying leads. I think this is more recent, but I can't find what software works with this. JohnArticle: 66246
In article <zxVXb.8259$PY.4716@newssvr26.news.prodigy.com>, John Patrick <j.s.paNOtrick@ieNOee.orgNO> wrote: >I also have a FPGA DEMO BOARD, with a XC3020A-7 and a XC4003A-6, >with the XChecker cable and flying leads. I think this is more >recent, but I can't find what software works with this. Not by much. Back, oh, in the old days (Fall 94, well, its the old days in terms of FPGAs!) the class project was build a MIDI synthesizer into a 4005. So this is still pretty darn old! -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 66247
I guess I need to read as much as I can to try and understand the FF's
in xilinx.......as even using there library counter I can't get a 193's
equiv. to work in a circuit designed for a 74ls193.
Fred
"Hal Murray" <hmurray@suespammers.org> wrote in message
news:102vrnvnm16debb@corp.supernews.com...
> > I am using webpack 4.1 and trying to create a 74ls193. I first
basically
> >built it from scratch using the logic diagram from the TTL datasheet but
it
> >would not work correctly in a circuit.
>
> > Anyone have a solution or idea of how I could design a ls193 with
either
> >descrete logic (like I tried) or using the library counters?
>
> The party line is don't-do-that, Do something else, for example use
> a different part.
>
> The basic rule is that you have to meet both setup and
> hold times on all flip-flops in your design. That gets tricky
> if you have a complicated clock distribution system.
>
> Xilinx FPGAs have a very low skew clock distribution system. They
> promise that the hold time will be 0. (or really that the min prop
> time will be enough to cover the hold time) That means you only
> have to worry about the setup time. Their software is smart enough
> to figure that out and tell you the max speed your design will
> run at.
>
> Where are your up/down pulses coming from? If they come out of
> a state machine (flip-flop), then you want to use the same clock
> that drives that state machine to drive a counter, and use the
> up/down signals to decide if your counter goes up, down, hold...
>
> It will all make sense after you get used to it. It's much
> cleaner/simpler for high speed designs.
>
> --
> The suespammers.org mail server is located in California. So are all my
> other mailboxes. Please do not send unsolicited bulk e-mail or
unsolicited
> commercial e-mail to my suespammers.org address or any of my other
addresses.
> These are my opinions, not necessarily my employer's. I hate spam.
>
Article: 66248Hello Brian. Brian Drummond <brian@shapes.demon.co.uk> wrote in message news:<0o9s205ugmsf0k6efk6oianhcgvqq8m9bs@4ax.com>... > > Another vote for headers. > > If one of them bears some relationship to a SODIMM socket, you could > conceivably support SDRAM through a controller in the FPGA, for those > who need it. Just a thought. > All the available MCU and FPGA signals have been exported to the headers (120 pins total). The idea of dual headers is to be able to stack modules up or down and keep things compact. We have also a design for a backplane, where the core module fits in dual headers and there are AGP132 connectors for the add-on modules that also have an edge connector (these have a length of ~2.7" that fits that format). So, yes, it's possible to have a module with SDRAMs controlled by the FPGA, although this will take some pins of the headers for the SDRAM control signals. If the module has an external controller that would be better, but perhaps a cleaner choice would be to use PSRAMs. The extra 12 signals of the AGP132 connectors are used for alternative voltages (eg negative voltages for bipolar DACs), and 4 pins are used for module auto-detection. Thanks for your comments. Regards.Article: 66249
Brian Drummond wrote: > > On 13 Feb 2004 19:19:07 -0800, pablobleyer@hotmail.com (Pablo Bleyer > Kocik) wrote: > > >[Sorry to repost. Seems my news server screwed up.] > > > >Hello Lewin. Thanks for replying. > > > >larwe@larwe.com (Lewin A.R.W. Edwards) wrote in message news:<608b6569.0402130650.717890c2@posting.google.com>... > >> Hi Pablo, > >> > >> Interesting product. Some comments: > >> > > >> Lose the prototyping area. Bring the signals to headers. I'm not > >> hacking stuff onto an eval board. > > > > Thanks, that is worthful. We were into the discussion of how valuable > >was the prototyping area for some people. > > Another vote for headers. > > If one of them bears some relationship to a SODIMM socket, you could > conceivably support SDRAM through a controller in the FPGA, for those > who need it. Just a thought. My vote would be for both headers and a proto area. The extra square inches of board space is not very much cost. When it comes to the headers, I always make the pinout compatible with the HP logic analyzer pinout. But not many agree with me on that. I find it so much more convenient to be able to plug in the pods rather than to have to clip all those little leads on. :) If anyone is interested, I can provide the HP doc on how to do this. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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